JPS5884453A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5884453A
JPS5884453A JP18226981A JP18226981A JPS5884453A JP S5884453 A JPS5884453 A JP S5884453A JP 18226981 A JP18226981 A JP 18226981A JP 18226981 A JP18226981 A JP 18226981A JP S5884453 A JPS5884453 A JP S5884453A
Authority
JP
Japan
Prior art keywords
power supply
supply element
power source
integrated circuit
charging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18226981A
Other languages
Japanese (ja)
Inventor
Shinji Katono
上遠野 臣司
Katsumi Miyauchi
宮内 克己
Keiichi Kanebori
恵一 兼堀
Tetsuichi Kudo
徹一 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18226981A priority Critical patent/JPS5884453A/en
Publication of JPS5884453A publication Critical patent/JPS5884453A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To lengthen the battery life time, by providing a circuit detecting the voltage drop of a power source element in an IC and allowing it to be charged before the discharge in 100%. CONSTITUTION:When the output voltage of the power source element 203 becomes V1 or less resulting in a state that a charging is required, a flip-flop 214 is set, and the power source element 203 is charged by an external power source 202 via a charge control circuit 205. Next, when the charge is finished, i.e. the output voltage of the power source element 203 becomes V0, the flip-flop 214 is reset, and the charging control circuit 205 breaks the connection between the external power source 202 and the power source element 203 and finishes the charging. Thereby, since the power source element 203 is not charged to V0 or more, overcharging is simultaneously prevented.

Description

【発明の詳細な説明】 本発明は電源素子内蔵型集積回路に関し、特に内蔵した
電源素子の寿命を長くするのに好適な集積回路の構成に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit with a built-in power supply element, and more particularly to a configuration of an integrated circuit suitable for extending the life of the built-in power supply element.

従来、電源を印加しないと内容が消去される揮発性メモ
リを用いる場合、電源オフ時にもその内容を消去させな
いためには、バッテリ等による電源のバックアップが必
要である。tた、電卓のように消費電力が小さいシステ
ムでは、外部電源と乾電池の両方の電源で動作するよう
に設計されている。従って、電源素子を内蔵した集積回
路の実現が強く要望されているが、電源素子の小型化と
ともにこの要望が実現可能になってきた。ここで、CM
OSスタティックRAMt例にとって電源素子内蔵型集
積回路を説明する。第1図は、この電源素子内蔵型集積
回路の断面構造を示す図でろる。
Conventionally, when using a volatile memory whose contents are erased when power is not applied, a backup power source such as a battery is required to prevent the contents from being erased even when the power is turned off. Additionally, systems with low power consumption, such as calculators, are designed to operate on both an external power source and a dry cell battery. Therefore, there is a strong desire to realize an integrated circuit with a built-in power supply element, and this demand has become possible with the miniaturization of power supply elements. Here, CM
An integrated circuit with a built-in power supply element will be described as an example of an OS static RAM. FIG. 1 is a diagram showing the cross-sectional structure of this integrated circuit with a built-in power supply element.

第1図において、CMOSスタティックRAMはnタイ
プシリコン基板1、pタイプウェル2、n−領域3、p
′″領域4、絶縁膜5、配線金属6゜61 、6// 
、 6111およびゲート7.7′から構成される。電
源素子は、このRAMチップの表面に施されたSi、N
、  などのパッシベーション膜8の上に作られる。つ
まり、電源素子の正または負極材料膜9、固体電解質1
0、電源素子の負または正極材料膜11を次々に形成す
ることにより作られる。電源素子の正極材料としては%
T’81svse など、負極材料としテf1% L 
i −AtiLt−Bt金合金どを用いる。また固体電
解質膜としては、L i4s io、 −Li、PO,
化合物薄膜、Li、N−t、tx  化合物薄膜などを
用いる。電源素子とRAMチップとの接続は、RAMチ
ップの接続端子Vgs6と電源端子Vcc6’がそれぞ
れ集電体12,12’を介して電源素子の正極および負
極に接続することにより行なわれる。最後にパッシベー
ション膜13を形成し、ボンディングした後パッケージ
ングする。なお、第1図では、RAMチップの上に電源
素子を形成し九場合を示したが、RAMチップと電源素
子を別々に作り、パッケージ内の配線により接続するこ
とも可能であることは勿論である。
In FIG. 1, a CMOS static RAM consists of an n-type silicon substrate 1, a p-type well 2, an n-region 3, a p
''' area 4, insulating film 5, wiring metal 6゜61, 6//
, 6111 and gate 7.7'. The power supply element consists of Si and N applied to the surface of this RAM chip.
, etc. is formed on the passivation film 8. That is, the positive or negative electrode material film 9 of the power supply element, the solid electrolyte 1
0. It is made by sequentially forming the negative or positive electrode material films 11 of the power supply element. % as a positive electrode material for power supply elements
As a negative electrode material such as T'81svse, te f1% L
i-AtiLt-Bt gold alloy or the like is used. Moreover, as a solid electrolyte membrane, Li4s io, -Li, PO,
A compound thin film, Li, Nt, tx compound thin film, etc. is used. The power supply element and the RAM chip are connected by connecting the connection terminal Vgs6 and the power supply terminal Vcc6' of the RAM chip to the positive and negative electrodes of the power supply element via current collectors 12 and 12', respectively. Finally, a passivation film 13 is formed, bonded, and then packaged. Although FIG. 1 shows the case where the power supply element is formed on the RAM chip, it is of course possible to make the RAM chip and the power supply element separately and connect them with wiring inside the package. be.

しかし、このように電源素子を内蔵し穴集積回路の寿命
は、例えば集積回路チップ自−身が10年以上ろるのに
対して、電源素子は5年以下というように、電源素子の
寿命により決まることが殆んどでめシ、特に電源素子の
寿命は、電源素子が充電可能な2次電池の場合には、電
池容量を何%放電した後に充電を行なうかということや
、充放電のくり返し回数により決まる。
However, the lifespan of a hole integrated circuit with a built-in power supply element depends on the lifespan of the power supply element, for example, the lifespan of the integrated circuit chip itself is more than 10 years, whereas the lifespan of the power supply element is less than 5 years. In most cases, the lifespan of a power supply element is determined by determining the lifespan of a power supply element, especially when the power supply element is a rechargeable secondary battery. Determined by the number of repetitions.

本発明は、このような電源素子を内蔵した集積回路にお
いて、電源素子の寿命を長くすることにより、長寿命の
集積回路を提供することを目的とする。
An object of the present invention is to provide an integrated circuit with a long life by extending the life of the power supply element in an integrated circuit incorporating such a power supply element.

一般に、充電可能な2次電池の場合、100%放電する
前に充電を行なえば、100%放電した後に充電する場
合に比べて電池寿命は長く、さらに充放電の〈シ返し回
数が少ない程電池寿命は長い。また放電量は電池の出力
電圧をセンスすることにより検出できる。本発明は、か
かる2次電池の特徴を利用し友ものでめり、集積回路に
電源素子の電圧降下を検出する回路を設け、100%放
電する以前に充電を行なわせるようにして電池寿命を長
くするものである。さらに、本発明は外部電源が印加さ
れている場合は外部電源によシ集積回路が動作するよう
にして電池の放電量を少くすることによって、充放電の
くり返し回数を少なくして電池寿命を長くするものであ
る。
In general, in the case of rechargeable secondary batteries, if you charge the battery before it is 100% discharged, the battery life will be longer than if you charge it after 100% discharge. It has a long lifespan. Further, the amount of discharge can be detected by sensing the output voltage of the battery. The present invention takes advantage of the characteristics of such secondary batteries, provides an integrated circuit with a circuit that detects the voltage drop of the power supply element, and charges the battery before it is 100% discharged, thereby extending the life of the battery. It is meant to be long. Furthermore, the present invention enables the integrated circuit to operate on external power when the external power is applied, thereby reducing the amount of battery discharge, thereby reducing the number of charging/discharging cycles and extending the battery life. It is something to do.

以下、本発明を実施例を用いて詳細に説明する。Hereinafter, the present invention will be explained in detail using Examples.

第2図は本発明の一実施例の構成を示す図でるる。FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

集積回路201は、集積回路外部の電源202が印加さ
れている場合は電源202により動作し、電源202が
印加されていない場合は内蔵した電源素子203によシ
動作するように電源切換回路206を通して電圧が供給
される。203は2次電池である。204は電源素子2
03の電圧降下を検出する検出回路でるる。205は、
検出回路204からの指示により、外部電源202を用
いて電源素子203を充電させるための充電制御回路で
るる。電源素子203は、時間が経過すると第3図に示
すように出力電圧が降下する。第3図において電圧Vo
 、 Vxはそれぞれ電源素子203が100%充電、
100%放電した時の出力電圧である。vlは電源素子
203の寿命が集積回路素子の寿命とはぼ等しくなるよ
うにした場合の充電を開始すべき電圧であり、vlは外
部電源が印加されるまでの時間遅れtlを考慮した場合
に充電を開始すべき電圧である。第2図の検出回路20
4内の214は、電源素子203の出力電圧がV、以下
になり充電を必要としている状態でるるか、あるいは充
電中であるということを記憶するための7リツプフロツ
プでるる。抵抗211゜212.213は、電源素子2
03の出力電圧viO時信号215が、出力電圧Voの
時信号216がそれぞれフリップフロップ214t−セ
ット、リセットする閾値電圧になるよう抵抗値が設定し
である。電源素子203t−充電する時1dVaより高
い電圧V(1+V、 (V、は例えば0.5v前後)で
行なう。この場合、外部電源202の出力電圧はV、+
V、に設定し、電源切換回路206内に電圧変換回路を
設けて206の出力217が電源素子203で動作する
場合も外部電源202で動作する場合も同じ電圧になる
ようにする。第2図から明らかなように、電源素子20
3の出力電圧がV、以下になるとフリップフロップ21
4がセットされ、充電制御回路205を介して外部電源
202により電源素子203が充電さる。次に充電が終
了すると、つまり電源素子203の出力電圧がvoにな
ると、フリップフロップ214がリセットされ、充電制
御回路205は外部電源202と電源素子203間の接
IRt−切ム充電を終了する。このため、電源素子20
3はWe以上′には充電さnないので、同・時′に過充
電も防止される。抵抗211,212,213は、可能
な限9大きい抵抗値にすれば抵抗211,212゜21
3により消費する電力は小さい。以上の説明から明らか
なように、本発明を用いれば、外部電源が接続されてい
る場合、集積回路は外部電源によシ動作するので、内部
電源素子の放電量は殆んど零であり、内部電源素子の充
放電のくり返し回数は少ない、しかも内部電源素子は1
00%放電する前に充電を始めるので寿命の長い電源素
子内蔵型集積回路を実現できる。
The integrated circuit 201 is operated by the power supply 202 when the power supply 202 external to the integrated circuit is applied, and is operated by the built-in power supply element 203 when the power supply 202 is not applied. Voltage is supplied. 203 is a secondary battery. 204 is power supply element 2
This is a detection circuit that detects the voltage drop of 03. 205 is
A charging control circuit is configured to charge the power supply element 203 using the external power supply 202 according to instructions from the detection circuit 204 . As time passes, the output voltage of the power supply element 203 drops as shown in FIG. In Figure 3, the voltage Vo
, Vx is 100% charged by the power supply element 203,
This is the output voltage when the battery is 100% discharged. vl is the voltage at which charging should be started when the lifespan of the power supply element 203 is approximately equal to the lifespan of the integrated circuit element; This is the voltage at which charging should start. Detection circuit 20 in FIG.
214 in 4 is a 7 lip-flop for storing that the output voltage of the power supply element 203 is below V and requires charging, or that charging is in progress. Resistors 211, 212, and 213 are power supply element 2.
The resistance value is set so that the signal 215 at the output voltage viO of 03 and the signal 216 at the output voltage Vo become the threshold voltage for setting and resetting the flip-flop 214t, respectively. When charging the power supply element 203t, it is charged at a voltage V (1+V, (V, for example, around 0.5V) higher than 1 dVa. In this case, the output voltage of the external power supply 202 is V, +
V, and a voltage conversion circuit is provided in the power supply switching circuit 206 so that the output 217 of the power supply switching circuit 206 has the same voltage both when operating with the power supply element 203 and when operating with the external power supply 202. As is clear from FIG. 2, the power supply element 20
When the output voltage of 3 becomes below V, the flip-flop 21
4 is set, and the power source element 203 is charged by the external power source 202 via the charging control circuit 205. Next, when charging ends, that is, when the output voltage of the power supply element 203 becomes vo, the flip-flop 214 is reset, and the charging control circuit 205 ends the connection IRt-disconnection charging between the external power supply 202 and the power supply element 203. For this reason, the power supply element 20
Since the battery 3 is not charged to more than We, overcharging is also prevented at the same time. If the resistance values of the resistors 211, 212, and 213 are made as large as possible,
3, the power consumption is small. As is clear from the above description, when the present invention is used, when an external power supply is connected, the integrated circuit operates on the external power supply, so the amount of discharge of the internal power supply element is almost zero, The number of repetitions of charging and discharging of the internal power supply element is small, and the number of times the internal power supply element is charged and discharged is small.
Since charging starts before 00% discharge, it is possible to realize an integrated circuit with a built-in power supply element that has a long life.

なお、第2図において、信号215が電圧V。In addition, in FIG. 2, the signal 215 is a voltage V.

になった時、フリップフロップ214をセットするよう
に述べたが、電圧v1の設定値は色々ある。
Although it was stated that the flip-flop 214 should be set when the voltage v1 is reached, there are various setting values for the voltage v1.

例えば、フリップフロップ214の出力218を用いて
集積回路外部に設は次液晶等の表示素子を点灯し、これ
を人間が検知して、直ちに外部電源202を印加すれば
、電圧v1は電圧Vsとほぼ等しく設定できる。まt外
部電源を印加しない時間の最大値が判っておれば、その
量大時間t1 を考慮してVs t−設定すればよい。
For example, if the output 218 of the flip-flop 214 is used to light up a display element such as a liquid crystal mounted outside the integrated circuit, and a human detects this and immediately applies the external power supply 202, the voltage v1 becomes the voltage Vs. Can be set approximately equal. If the maximum time during which no external power is applied is known, Vs t- may be set in consideration of the maximum time t1.

第2図において、電源素子203を充分充電できる程長
い時間外部電源202が連続して印加されない可能性が
める場合には、フリップフロップ214の出力218を
用いて表示素子を点灯するようにして、表示素子点灯中
は外部電源202を印加するようにすれば、電源素子2
03をV(l tで充電できる。
In FIG. 2, if there is a possibility that the external power source 202 will not be continuously applied for a long enough time to sufficiently charge the power source element 203, the output 218 of the flip-flop 214 is used to light up the display element. If the external power supply 202 is applied while the element is lit, the power supply element 2
03 can be charged with V(lt).

tた、第2図の電源素子203の電圧降下時間や充電時
の電圧上昇時間が長いため、クリップ70ツブ214が
高レベルでも低レベルでもない中間レベルにある時間が
長くなり、これがフリップフロップ214の誤動作させ
る可能性がある時はフリップフロップ214の入力にシ
ュミット・トリガ回路を設けてもよい。
In addition, since the voltage drop time of the power supply element 203 in FIG. If there is a possibility of malfunction, a Schmitt trigger circuit may be provided at the input of the flip-flop 214.

さらに、第2図では、検出回路204として抵抗とフリ
ップ70ツブを用いたが、他の回路例えば差動回路のよ
うなものを用いても構成できる。
Further, in FIG. 2, a resistor and a flip 70 tube are used as the detection circuit 204, but other circuits such as a differential circuit can also be used.

以上の説明しえように、本発明によれば、集積回路に組
込まれた電源素子の放電時間を少なくでき、これが几め
充放電のくり返し回数が少なくできる。さらに電源素子
が100%放電する前に充電できるので、電源素子の寿
命を長くでき、電源素子を内蔵した集積回路の寿命を長
くできるという大きな効果がある。
As explained above, according to the present invention, the discharge time of the power supply element incorporated in the integrated circuit can be reduced, and the number of repeated charging and discharging operations can be reduced. Furthermore, since the power supply element can be charged before it is 100% discharged, there is a great effect that the life of the power supply element can be extended, and the life of the integrated circuit containing the power supply element can be extended.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は電源素子を内蔵した集積回路の断面構造の一例
を示す図、第2図は本発明の一実施例を示す図、第3図
は第2図の集積回路に用いられている電源素子の放電特
性の一例を示す図である。 代理人 弁理士 薄田利幸 ¥I  1  国 ′″fJ2図 ′!fj3図 r 吟間
Fig. 1 is a diagram showing an example of the cross-sectional structure of an integrated circuit incorporating a power supply element, Fig. 2 is a diagram showing an embodiment of the present invention, and Fig. 3 is a diagram showing a power supply used in the integrated circuit of Fig. 2. FIG. 3 is a diagram showing an example of discharge characteristics of an element. Agent Patent Attorney Toshiyuki Usuda¥I 1 Country'''fJ2 Figure'! fj3 Figure R Ginma

Claims (1)

【特許請求の範囲】[Claims] 1、内蔵する電源素子により電源電圧を供給してなる集
積回路において、上記電源素子の電圧降下を検出する検
出回路を具備し、上記検出回路の出力によって上記電源
素子の充電を制御することを特徴とする集積回路。
1. An integrated circuit configured to supply power supply voltage from a built-in power supply element, comprising a detection circuit for detecting a voltage drop in the power supply element, and controlling charging of the power supply element by the output of the detection circuit. integrated circuit.
JP18226981A 1981-11-16 1981-11-16 Integrated circuit Pending JPS5884453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18226981A JPS5884453A (en) 1981-11-16 1981-11-16 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18226981A JPS5884453A (en) 1981-11-16 1981-11-16 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5884453A true JPS5884453A (en) 1983-05-20

Family

ID=16115299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18226981A Pending JPS5884453A (en) 1981-11-16 1981-11-16 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5884453A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS518537A (en) * 1974-06-10 1976-01-23 Gates Rubber Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS518537A (en) * 1974-06-10 1976-01-23 Gates Rubber Co

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