JPS5883462A - Transmission system for terminal controlling signal - Google Patents

Transmission system for terminal controlling signal

Info

Publication number
JPS5883462A
JPS5883462A JP18122081A JP18122081A JPS5883462A JP S5883462 A JPS5883462 A JP S5883462A JP 18122081 A JP18122081 A JP 18122081A JP 18122081 A JP18122081 A JP 18122081A JP S5883462 A JPS5883462 A JP S5883462A
Authority
JP
Japan
Prior art keywords
terminal
format
microprocessor
signal
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18122081A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
浩 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18122081A priority Critical patent/JPS5883462A/en
Publication of JPS5883462A publication Critical patent/JPS5883462A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/60Semi-automatic systems, i.e. in which the numerical selection of the outgoing line is under the control of an operator
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To reduce the quantity of hardware and to make the extension of input/output ports easy, by converting the terminal controlling information from parallel into serial format with a microprocessor at a terminal controller. CONSTITUTION:A central controller 1 transmits the terminal controlling information of parallel format to a terminal controller 5 via a signal reception distributor 2. The controller 5 reads the control information with a microprocessor 6 and stores the data in an RAM8 tentatively. The microprocessor 6 converts the terminal controlling information of parallel format into that of serial format based on the specified program picked up from an ROM7. An output circuit 9 of the terminal controller 5 transmits the serial signal to a desired terminal (e.g., attendant board 3, and a lamp display 4) in the specified format.

Description

【発明の詳細な説明】 本発明は、電話交換機、特に、構内電話交換機において
、多くの制御、操作情報等を必要とする端末機器(例え
ば、中継台、ランプ表示装置、多機能電話機等であって
、以下、単に「端末」という。)に対する各種の制御情
報をシリアル信号に変換して送出するための端末制御信
号送出方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention is intended for use in telephone exchanges, particularly private branch exchanges, for terminal equipment (for example, relay boards, lamp display devices, multi-function telephones, etc.) that require a large amount of control and operation information. The present invention relates to a terminal control signal transmission method for converting various control information for a terminal (hereinafter simply referred to as a "terminal") into a serial signal and transmitting the serial signal.

この種の端末は、一般に、その各個に必要な制御情報量
は少なくても装置数が多いもの、または装置数は少なく
ても必要な制御情報量が多いものがある。
This type of terminal generally requires a small amount of control information for each terminal but has a large number of devices, or a terminal that requires a small number of devices but requires a large amount of control information.

したがって、その制御情報線(制御信号線)の本数を減
らして経済化を図るには、端末制御装置から各端末に対
する制御信号をシリアルに送出する必要がある。
Therefore, in order to achieve economy by reducing the number of control information lines (control signal lines), it is necessary to serially send control signals to each terminal from the terminal control device.

この種の従来の端末制御信号送出方式は、−例として、
端末制御装置が中央制御装置から受けたパラレル情報を
、その変換のだめに特別に設けられたパラレル・シリア
ル変換回路によって変換・送出するようにしていたので
、この送出回路のノ・−ドウエア量が増大するとともに
、そのデータ処理、転送タイミング制御が複雑となり、
経済的でなく、ま″た、その入出力ポートの増設も困難
であった。
This type of conventional terminal control signal transmission method is as follows:
Since the parallel information received by the terminal control device from the central control device was converted and sent out using a parallel-to-serial conversion circuit that was specially provided for the conversion, the amount of hardware in this sending circuit increased. At the same time, data processing and transfer timing control become complicated.
It was not economical, and it was also difficult to add more input/output ports.

本発明の目的は、上記した従来技術の欠点をなくシ、ハ
ードウェア量の削減をし、入出力ポートの増設を容易と
し、処理、制御を簡略化することができる経済的な端末
制御信号送出方式を提供することにある。
It is an object of the present invention to eliminate the drawbacks of the prior art described above, reduce the amount of hardware, facilitate the addition of input/output ports, and provide an economical terminal control signal that can simplify processing and control. The goal is to provide a method.

本発明の特徴は、端末制御装置のマイクロプロセッサが
、中央制御装置から受けたパラレル形式の端末制御情報
を所定のプログラムに基づいてシリアル形式の端末制御
情報への変換処理をすることにより、当該情報に従って
上記端末制御装置の出力回路から当該シリアル信号を所
望の端末に対して所定の形式で送出しうるようにした端
末制御信号送出方式にある。
A feature of the present invention is that the microprocessor of the terminal control device converts the parallel format terminal control information received from the central control device into serial format terminal control information based on a predetermined program. Accordingly, there is provided a terminal control signal sending method in which the serial signal can be sent from the output circuit of the terminal control device to a desired terminal in a predetermined format.

以下、本発明の実施例を図に基づいて説明する。Embodiments of the present invention will be described below based on the drawings.

第1図は、本発明に係る端末制御信号送出方式の一実施
例の中継方式図、第2図は、そのフローチャート、第3
図は、同端末制御信号の波形図である。
FIG. 1 is a relay system diagram of an embodiment of the terminal control signal sending system according to the present invention, FIG. 2 is a flowchart thereof, and FIG.
The figure is a waveform diagram of the terminal control signal.

ここで、■は、中央制御装置、2は、信号受信分配装置
、3は、端末に係る中継台、4は、同ランプ表示装置、
5は、端末制御装置、6は、そのマイクロプロセッサ、
7は、同リードオンリメモリ(以下、R,OMという。
Here, ■ is a central control device, 2 is a signal reception distribution device, 3 is a relay stand related to a terminal, 4 is a lamp display device,
5 is a terminal control device; 6 is a microprocessor thereof;
7 is the same read-only memory (hereinafter referred to as R, OM).

)、8は、同ランダムアクセスメモリ(以下、RAMと
いう。)、9は、まず、中央制御装置1は、所望の端末
、例えば、中継台3.ランプ表示装置4等に対し制御情
報を転送して制御9表示等を行うときは、信号受信分配
装置2を介して端末制御装置5ヘパラレル形式の当該制
御情報を送信してくる。なお、信号受信分配装置2は、
このほかに通話路制御装置SPCその他に関し、その信
号の送受信をするものである。
), 8 is a random access memory (hereinafter referred to as RAM), and 9 is first, the central control device 1 connects a desired terminal, for example, a relay stand 3 . When transmitting control information to the lamp display device 4 or the like to perform a control 9 display or the like, the control information in parallel format is transmitted to the terminal control device 5 via the signal reception and distribution device 2. Note that the signal reception distribution device 2 is
In addition, it transmits and receives signals regarding the communication path control device SPC and others.

端末制御装置5は、そのマイクロプロセッサ6で当該制
御情報の読取りを行い、そのデータ(例えば、8ビツト
のもの)をデータバスBU8経由で11.AM8の所定
エリアに一時蓄積する(第2図のブロック10)。
The terminal control device 5 reads the control information using its microprocessor 6, and sends the data (for example, 8-bit data) to the 11. It is temporarily stored in a predetermined area of AM8 (block 10 in FIG. 2).

以下、マイクロプロセッサ6は、ROM6から端末制御
信号送出用のプログラムを取り出し、そのプログラム処
理を行う。
Thereafter, the microprocessor 6 retrieves a program for sending terminal control signals from the ROM 6 and processes the program.

まず、上記の制御情報データの最下位(まだは最上位)
のビットは“1″(マーク) 、  t(Q II(ス
ペース)のいずれであるかを判断しく同前ブロック11
)、そのマーク、スペースに応じ、出力回路9に対し、
その送信レジスタ(図示省略)における所望の端末に対
応するマークビット、スペースビットをセットせしめる
ようにする(同前ブロック12A、12B)。
First, the lowest level (still the highest level) of the above control information data
It is necessary to judge whether the bit is “1” (mark) or t (Q II (space)).
), according to the mark and space, for the output circuit 9,
The mark bit and space bit corresponding to the desired terminal in the transmission register (not shown) are set (blocks 12A and 12B).

これにより、出力回路9は、その送信レジスタのセット
内容に応じた所定の形式の7リアル信号(例えば、第3
図に示すような複流RZ方式による“1″、0”信号)
を所望の端末の中継台3゜ランプ表示装置4へ送出する
As a result, the output circuit 9 outputs a 7 real signal (for example, a 3rd
"1", 0 signals by double flow RZ method as shown in the figure)
is sent to the relay stand 3° lamp display device 4 of the desired terminal.

このシリアル信号は、当該端末に応じて所定の信号期間
t(例えば、10μs)9周期T(例えば、100μs
)のものでなければならない。
This serial signal has a predetermined signal period t (for example, 10 μs) and 9 periods T (for example, 100 μs) depending on the terminal.
).

出力回路9は、前記送信レジスタにマークピット、スペ
ースビットがセットされている期間だけマーク信号、ス
ペース信号を送出するので、マイクロプロセッサ“6は
、信号期間tの送信タイミングをとっだ後(同前ブロッ
ク13)、上記送信レジスタのマークピット、スペース
ビットのリセットを行い(同前ブロック14)、更に、
次の信号までの零復帰状態(RZ)を保つために必要な
時間(T−t)のリセットタイミングをとる(同前ブロ
ック15)。
Since the output circuit 9 sends out mark signals and space signals only during the period in which the mark pit and space bits are set in the transmission register, the microprocessor "6" sends out the mark signal and the space signal only during the period when the mark pit and space bits are set in the transmission register. Block 13), reset the mark pit and space bit of the transmission register (block 14), and further,
A reset timing is determined for the time (Tt) necessary to maintain the zero return state (RZ) until the next signal (block 15).

以上により、端末制御情報の1ビツト分のシリアル信号
が送出されたことになるので、当該情報′の全ビット(
例えば、8ピツト)の送出が完了されたか否かのチェッ
クを行い(同前ブロック16)、完了していなければ最
初に戻り、上述と同様に次のビットについてシリアル信
号の送出動作を繰り返す。
As a result of the above, a serial signal for one bit of terminal control information has been sent, so all bits of the information '(
For example, a check is made as to whether or not transmission of the 8 bits (8 bits) has been completed (block 16), and if it has not been completed, the process returns to the beginning and repeats the serial signal transmission operation for the next bit in the same manner as described above.

このようにして、所望の端末制御情報がシリアル信号で
所望の端末へ伝達されるが、中央制御装置1は、多量の
処理を高速で処理しなければならないので、当然、パラ
レル形式で端末制御情報を送出しなければならないのに
反し、端末は、動作速度が遅いので、むしろシリアル信
号で当該情報を受けた方がよく、これは当該信号線の本
数の減少化にもなりちる。
In this way, the desired terminal control information is transmitted to the desired terminal in the form of a serial signal. However, since the central control unit 1 must process a large amount of processing at high speed, it naturally transmits the terminal control information in parallel format. However, since the operating speed of the terminal is slow, it is better to receive the information in the form of a serial signal, which may also lead to a reduction in the number of signal lines.

なお、出力回路9は、この端末制御装置5が受は持つべ
き端末数に応じ、その送信レジスタのマ−クビット、ス
ペースビットを増減すれば、容易に人出力ポートの増減
となり、また、従来例のように特別にパラレル・シリア
ル変換回路等を設ける必要がないので、ハードウェア量
が減少して経済化される。
Note that the output circuit 9 can easily increase or decrease the number of output ports by increasing or decreasing the mark bits and space bits of the transmission register according to the number of terminals that the terminal control device 5 should have. Since there is no need to provide a special parallel-to-serial conversion circuit, the amount of hardware is reduced and economy is achieved.

以上、詳細に説明したように、本発明によれば、・・−
ドウエア量の削減をし、入出力ポートの増設を容易とし
、また、本来端末制御装置に有す処理機能によってデー
タ処理、転送タイミング制御が簡略化されるので、経済
的な端末制御信号送出方式が実現され、その効果は顕著
である。
As explained above in detail, according to the present invention...-
It is an economical terminal control signal sending method because it reduces the amount of hardware, makes it easy to add input/output ports, and simplifies data processing and transfer timing control using the processing functions originally included in the terminal control device. This has been achieved, and its effects are remarkable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明に係る端末制御信号送出方式の一実施
例q中継方式図、第2図は、そのフo −チャート、第
3図は、同端末制御信号の波形図である。 1・・・中央制御装置、2・・・信号受信分配装置、3
・・・中継台、4・・・ランプ表示装置、5・・・端末
制御装置、6・・・マイクロプロセッサ、7・・・RO
M、8・・・RAM。 9・・・出力回路。 ¥1 目 $z囚
FIG. 1 is a diagram of a q-relay system according to an embodiment of the terminal control signal transmission system according to the present invention, FIG. 2 is a flowchart thereof, and FIG. 3 is a waveform diagram of the terminal control signal. 1... Central control device, 2... Signal reception distribution device, 3
... Relay stand, 4... Lamp display device, 5... Terminal control device, 6... Microprocessor, 7... RO
M, 8...RAM. 9...Output circuit. ¥1st $z prisoner

Claims (1)

【特許請求の範囲】[Claims] 1、 端末制御装置のマイクロプロセッサが、中央制御
装置から受けたパラレル形式の端末制御情報を、所定の
プログラムに基づいてンリアル形式の端末制御情報への
変換処理をすることにより、当該情報に従って上記端末
制御装置の出力回路から当該シリアル信号を所望の端末
に対して所定の形式で送出しうるようにすることを特徴
とする端末制御信号送出方式。
1. The microprocessor of the terminal control device converts the terminal control information in parallel format received from the central control device into terminal control information in real format based on a predetermined program, thereby controlling the terminal according to the information. 1. A terminal control signal sending system characterized in that the serial signal can be sent from an output circuit of a control device to a desired terminal in a predetermined format.
JP18122081A 1981-11-13 1981-11-13 Transmission system for terminal controlling signal Pending JPS5883462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18122081A JPS5883462A (en) 1981-11-13 1981-11-13 Transmission system for terminal controlling signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18122081A JPS5883462A (en) 1981-11-13 1981-11-13 Transmission system for terminal controlling signal

Publications (1)

Publication Number Publication Date
JPS5883462A true JPS5883462A (en) 1983-05-19

Family

ID=16096913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18122081A Pending JPS5883462A (en) 1981-11-13 1981-11-13 Transmission system for terminal controlling signal

Country Status (1)

Country Link
JP (1) JPS5883462A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105920A (en) * 1977-02-28 1978-09-14 Nec Corp Control unit for exclusive processor control switchboard
JPS53116010A (en) * 1977-03-18 1978-10-11 Fujitsu Ltd Terminal control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105920A (en) * 1977-02-28 1978-09-14 Nec Corp Control unit for exclusive processor control switchboard
JPS53116010A (en) * 1977-03-18 1978-10-11 Fujitsu Ltd Terminal control system

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