JPS5882692U - timer device - Google Patents

timer device

Info

Publication number
JPS5882692U
JPS5882692U JP17775181U JP17775181U JPS5882692U JP S5882692 U JPS5882692 U JP S5882692U JP 17775181 U JP17775181 U JP 17775181U JP 17775181 U JP17775181 U JP 17775181U JP S5882692 U JPS5882692 U JP S5882692U
Authority
JP
Japan
Prior art keywords
circuit
timer
timer device
fine adjustment
timer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17775181U
Other languages
Japanese (ja)
Other versions
JPS6221996Y2 (en
Inventor
島谷 繁
吉原 正宏
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP17775181U priority Critical patent/JPS5882692U/en
Publication of JPS5882692U publication Critical patent/JPS5882692U/en
Application granted granted Critical
Publication of JPS6221996Y2 publication Critical patent/JPS6221996Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Measurement Of Predetermined Time Intervals (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の回路図、第2図は別の実施
例の回路図である。 1.4・・・タイマ回路、2.5・・・第1微調整回路
、3.6・・・第2微調整回路、7・・・フリップフロ
ップ、8・・・イニシャライズ回路、9・・・オアゲー
ト。
FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a circuit diagram of another embodiment. 1.4... Timer circuit, 2.5... First fine adjustment circuit, 3.6... Second fine adjustment circuit, 7... Flip-flop, 8... Initialization circuit, 9...・Orgate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] タイマ回路と、該タイマ回路による動作開始時刻を調整
する第1微調整回路と、上記タイマ回路による動作路f
蒔刻を調整する第2微調整回路とで成ることを特徴とす
るタイマ装置。
a timer circuit, a first fine adjustment circuit that adjusts the operation start time of the timer circuit, and an operation path f of the timer circuit;
1. A timer device comprising: a second fine adjustment circuit for adjusting seeding.
JP17775181U 1981-12-01 1981-12-01 timer device Granted JPS5882692U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17775181U JPS5882692U (en) 1981-12-01 1981-12-01 timer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17775181U JPS5882692U (en) 1981-12-01 1981-12-01 timer device

Publications (2)

Publication Number Publication Date
JPS5882692U true JPS5882692U (en) 1983-06-04
JPS6221996Y2 JPS6221996Y2 (en) 1987-06-04

Family

ID=29971919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17775181U Granted JPS5882692U (en) 1981-12-01 1981-12-01 timer device

Country Status (1)

Country Link
JP (1) JPS5882692U (en)

Also Published As

Publication number Publication date
JPS6221996Y2 (en) 1987-06-04

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