JPS5882574A - Power field effect transistor structure - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION +1) Field of the Invention The present invention relates to field effect transistors, and more particularly to structures for power field effect transistors.

MO8 field effect transistors (Mo5yET) typically include a date electrode or path separated from the semiconductor material by an insulating layer. A date electrode, often made of polysilicon, is placed over a channel of semiconductor material formed by the drain, gate, and source regions of the device. A second insulating layer is deposited over the date electrode and a metal such as aluminum is evaporated over the second insulating layer to create a source electrode metallization layer. To provide contact to the source region of semiconductor material, portions of metal are also deposited at various locations on the source region '7'
-) An opening is provided in the electrode and the insulating layer.

A power MO8FET generally includes one large drain region made up of a semiconductor substrate and an epitaxial layer on the substrate. Inside the semiconductor, the epitaxial layer is a number of 'l'-) regions, with a source region located within each r-) region. The r-toad electrode also often has a plurality of separate areas, each area overlying the semiconductor between adjacent source regions. The area of each r-t electrode is often referred to as a date path. A metallization layer contacts each source region and thereby interconnects the source regions. r −
The path also includes individual sources and ? -) regions are interconnected to operate in parallel. The device thus effectively operates as a single MOB transistor.

(2) Description of the Prior Art The source electrode layer in prior art devices typically covers most of the main active area of a transistor device in the form of a continuous layer. This creates an effective parasitic /r-) source capacitance, increasing turn-on and turn-off times along with the current drive required to switch the device. Additionally, the insulating layer between the date electrode and the source metal layer must provide a high degree of edging over a large area of the source electrode layer, avoiding pinholes or photomask defects that occur while the contacts in the insulating layer are open. Such imperfections can lead to the ultimate dating source short circuit. That is, during the metallization process, the metal f I that short-frosts the source and r-) electrode layers due to imperfections in the insulating layer between the source electrode layer and the underlying gate electrode layer.
) horns may be formed.

Another disadvantage associated with prior art power MO8FET devices concerns the "on-resistance" (Ron) of the devices. The on-resistance of power MO8FET devices is determined in part by the width of the individual date electrode paths between the source regions. Generally, the higher the on-resistance of a MO8FET device, the higher its power consumption.

The source regions of power transistors are generally constructed in relatively narrow parallel lines, each line often referred to as a source path. Each source path includes a plurality of expanded areas that accommodate contact pads of the source electrode layer. The expanded area of previous devices is octagonal and hexagonal.
It has a rectangular shape. Since each date path follows the outline of an adjacent source path, the expanded area of the source path serves to reduce the effective width of the date path. Also, the expanded area of previous devices consumes a large amount of space, which reduces the available storage density of the source path.

To minimize the effective width limitations of each date path, previous devices have been constructed such that the extended area adjacent to the source path is sandwiched.

Sandwiched structures complicate the generation of the masks used to assemble the device and do not lend themselves well to iterative (step-repeat) computer-controlled generation procedures.

SUMMARY OF THE INVENTION One object of the present invention is to provide an improved power field effect transistor device that does not require switching time or turn-on energy.

Another object of the present invention is to provide a power field effect transistor that requires less chip area than prior art designs while maintaining comparable on-resistance and rated breakdown voltage.

Yet another object of the present invention is to provide a power field effect device that has improved production yield and is easier to make than prior art devices.

The present invention is directed to a field effect transistor having a date electrode and a source electrode metallization layer having a plurality of isolated windows in the source electrode layer. This structure is
Reduce the capacitance between the source electrode layer and the date electrode. Furthermore, the risk of short circuits between the source electrode layer and the gate electrode is also reduced.

In another aspect of the invention, the semiconductor material of the device includes a source region having a rectangular expanded area that accommodates the contacts of the source electrode and a plurality of narrower source areas interconnecting the expanded area. including. The rectangular expanded area reduces the area of semiconductor material consumed by the expanded subregion, thus increasing the packing density of the source paths without reducing the effective date width of each date electrode path.

Another embodiment of the present invention provides for facilitating the generation of masks for use in making transistor devices.
Provides an orthogonal array of extended source areas.

The present invention will now be described in more detail with reference to the accompanying drawings, in which like numerals represent like elements.

DETAILED DESCRIPTION OF THE DRAWINGS FIG. 1 shows a cross-section of a single transistor element of a prior art power uosFm device. Device 10 includes an epitaxial layer (or epilayer) that is etched as an n-type to create a tunnel region 12, for example. Gate region 14 is diffused into drain region 12 and a sixth or source region 16 is diffused into date region 14. If the tunnel region is doped as n-, the date and source regions are typically doped as p and n+, respectively. Channels 18 on both sides of the source region 16 are formed with tunnel regions 121 extending across the gate bright region 14 from the source region 16 . A date electrode 20, often comprised of n-type silicon, is placed over the device 100 channel 18, with an insulating layer 22 separating the date electrode 20 from the channel 18. Device 10 includes a second insulating layer 2 separating metallization layer 26 from date electrode 20.
It is equipped with 4. The metallized layer 26 constitutes a source electrode layer and is made by depositing a metal such as aluminum on the surface of the insulating layer 24. Insulating layer 24 may consist of thermal silicon dioxide, CvD silicon dioxide, silicon nitride, or some other dielectric. Source electrode layer 26
contacts source region 16 through an opening in insulating layer 24 (not shown in cross-section in FIG. 1).

In prior art devices, the source electrode layer 26 typically covers most of the active area of the MO8FET device in one continuous layer. Since the source electrode layer 26 is greatly expanded, the capacitors 28a and 2 shown by dotted lines
8m), a relatively large parasitic capacitance occurs between the source electrode layer 26 and the gate electrode 20. The large extent of the source electrode layer 26 also requires a high degree of rim integrity provided by the insulating layer 24 over a relatively large area. Imperfections in insulating layer 24, such as pinholes and photomask defects, can lead to metal bridges created between source electrode layer 26 and date electrode 20. This risk is particularly great for areas of the device 100 where the vertical walls of the date electrodes 20 are found. An example of one such metal bridge shorting the source electrode layer 26 and the date electrode 20 near the date electrode wall 290 is 3.
0.

2 and 3, a power MO8F'ET device 32 is shown employing a preferred embodiment of the present invention. FIG. 3 shows the source electrode layer 26 and the insulating layer 2 to clarify the explanation of the underlying structure.
3 shows the device 32 of FIG. 2 with 4 removed. Transistor device 32 has multiple parallel source paths 3
4, each path including a source region 16 diffused into a date region 14 (date region 14 is in turn diffused into an invisible P-rain region). The plurality of date electrodes 20 are
It is placed over the semiconductor material between adjacent source/blue layers 34. Each date electrode 20 is sometimes referred to as a date path. Each source path 34 includes a plurality of expansion areas 36 interconnected by narrow areas 38 between expansion areas 360. Expanded area 36 is adapted to accommodate contact 40 (FIG. 2) between source region 1B and source electrode layer 26. Contacts 40 of source electrode layer 26 are made in openings provided in the insulating layer overlying extension area 36 . The extension area 36 of each source path 34 is made such that the subregion 14L of the date region 14 is retained within the source extension area 3B. Contact 40 also makes contact with small date region 14a of tate region 14, thereby shorting source region 1B to tate region 14 near each extension area 360.

Shorting the source region to the date region reduces parasitic bipolar transistor action since the shorted date region does not operate as a base region.

According to the present invention, as shown in FIG.
The source electrode layer 26 includes a plurality of windows or openings 42, but there is no metallization layer overlying the insulating layer 24. By providing the window 42, the source electrode layer 26
The parasitic interlayer capacitance between and date electrode 20 is correspondingly reduced. Furthermore, the risk of short circuits between source electrode layer 26 and date electrode 20 due to imperfections in insulating layer 24 is also reduced. Each window 42 shown is centered over a narrow portion 38 of the source path 34 to minimize overlapping of the source electrode layer 26 over the vertical walls 29 of the date electrode 20. desirable. This further reduces the risk of short circuits which are higher near the vertical wall 290.

Depending on the thickness of layer 26, between 20 and 40 inches of source electrode layer 26 can be removed to create the window. The larger the thickness of the source electrode layer 26, the larger the window 42 becomes.
The resistance of the source electrode layer 26 does not increase excessively.

Although opening 42 is preferably described and illustrated as a window, other shaped openings may be used in metallized source electrode layer 26.

Although the window provides a continuous current path in the remaining metal of the source electrode, some devices do not require this, and the removed metal of the electrode can be in the form of stops, rhizos, and other shapes.

As seen most clearly in FIG. 3, the shape of date electrode 20 generally follows the contour of adjacent source electrode 34. The effective width of date electrode 20 is a function of the size of widened area 36 and narrowed area 38 and the source bus 340 spacing shown by arrow 44. Furthermore, the effective date width is also a function of the shape of the expansion area. The expansion area 36 in the illustrative example is rectangular. In comparison, the source path extension area of many conventional devices is octagonal or hexagonal. These shapes accommodate similarly sized source electrode contacts, but typically occupy a larger chip area than the rectangular extension area of the illustrative example.

Thus, the rectangular expansion area 36 provides a wider effective date range per unit of time than conventional designs.

The source paths 34 can therefore be made closer together without reducing the effective width of the electrodes 2fl.

The power dissipated by a power MO8FET device is generally a function of its on-resistance.

The on-resistance of the device is determined in part by the effective width of each r-) electrode. As previously mentioned, the effective date width is a function of the size of the expansion area 36. In the illustrative example, the extended areas 36 of source region 16 each have a width of 12 microns (12 millionths of a meter). This width has been found to provide adequate space to accommodate the contact 40 of the source electrode layer 26 while minimizing the reduction in effective r-t width due to the presence of the expanded area 36.

Tate region 14a within expanded area 36 is also reduced in size compared to conventional designs. As a result, dating area 1
4a occupies less space within the expansion area 36, thereby providing a wider source area 16a around the date area 14a.

This improves current injection into the r-top region 14.

Thus, the total current of the device is improved, reducing on-resistance and increasing transconductance. The date region 14a within the expanded area 36 of the source region 16 is about 6z crons (10
It has dimensions of 6 millionths of a meter) x 6 microns (6 millionths of a meter).

Another advantage of the illustrative example is that each source
+ spaced apart by an expanded area 36 along the path 34.

In the illustrative example, the spacing is one expansion area 3
6 to the center of the adjacent extension area 36 along each source path 34 has been reduced to a distance of 58 millionths of a meter. This is an expanded area of 36
By increasing the frequency per unit area of the source electrode contact 400, and thus also increasing the frequency per unit area of the source electrode contact 400, the parasitic ΔIborer effect of device 32 is further reduced.

Furthermore, the high frequency of the expansion area 36 increases the total periphery of the source region 16, which further improves the transconductance gm. These improvements in transconductance are important for power MO8FF:T devices, especially for low breakdown voltage devices (such as those below 200 V) where on-resistance is significantly affected by channel resistance. Therefore, improved transconductance can also result in significant improvements in device on-resistance.

In the device 32 of FIG. 2, the expanded areas 36 of adjacent source paths 34 are inserted to minimize the narrowness of the date electrodes 20. However, this insert structure has been found to be unnecessary for power MO8FET devices with relatively high breakdown voltages, for example in excess of 200V breakdown voltage.

FIG. 4 shows an alternative embodiment of the device of FIG. The device has a plurality of source paths 34a that include expanded areas 36a arranged orthogonally rather than interleaved as in FIGS. 2 and 3.

The orthogonal arrangement of expanded areas 36a of the device of FIG. 4 facilitates simplifying the structure of the device. The source and r-) region patterns of the device are generally masked over the device. Masks used in masking operations are often created by automated procedures using a computer.

The orthogonal arrangement of FIG. 4 facilitates the use of a "Stetsuzo-Repeat" masking operation. Furthermore, since the expansion area 36a is not inserted but orthogonally arranged, the window 42a of the device
are also orthogonally arranged to further simplify and automate the manufacturing process. Another advantage of the orthogonal arrangement shown in FIG. 4 is that the source electrode contact spacing of the extended area 36a is reduced compared to the interleaved pattern. As a result, current conduction through the source electrode layer is improved.

The transistor devices of the present invention have improved performance characteristics and require less semiconductor chip area than conventional designs with on-resistance, transconductance, and breakdown voltage ratings such as -. It is clear from the description. Improved performance characteristics include faster switching times, less drive energy v required to turn on the device, and thus reduced interlayer capacitance. The unmetallized windows or openings in the source electrode layer further improve the production yield of the manufactured devices by reducing the chance of shorting the intermediate layers.

The improved production yield lowers the manufacturing cost of the child chair.

It goes without saying, of course, that variations in various aspects of the invention will be apparent to those skilled in the art, some becoming apparent only after study, and others simply a matter of routine semiconductor design problems.

Depending on the respective application, other embodiments are possible, as well as the specific design. As such, the scope of the invention is not to be limited by the specific embodiments described herein, but is to be defined only by the claims and their equivalents. Various features of the invention are set forth in the claims.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a prior art power MO8FRT device, FIG. 2 is a top view of a transistor device of the present invention with the underlying portion shown in dotted lines, and FIG. FIG. 4 is a plan view of an alternative implementation of the device of FIG. 2; IQ, 32-MO8EPT device: 12-drain region; 14-date region; 16-source region; 1
8-channel: 20-gate electrode; 22° 24-insulating layer; 26-metallized layer (source electrode layer); 2Ba, 2
8b-=t ridge; 29-vertical wall; 3G-f ridge;
34-source/child; 36-expansion area; 40-contact point;
42-Window (opening) agent Akira Asamura

Claims (1)

[Scope of Claim] A semiconductor material having P-rain, date and source regions forming a channel extending from the (11 source region to the 'F'-) region to the drain region. #11 insulation layer; a gate electrode layer placed on the first insulation layer over the channel; a second insulation layer placed on the date electrode layer; and a second insulation layer placed on the r-) electrode. a metallization layer comprising a source electrode overlying and having a contact through the insulating layer to the source region, the metallization layer having a plurality of isolated openings above the tate electrode thereby connecting the interlayer capacitance and the metallization layer; and the metallized layer in which the risk of short circuit with the date electrode is reduced. (2) In the transistor according to claim (1), the date is arranged vertically. Said transistor having a wall, characterized in that the front opening is in the form of a window and is placed on the vertical wall of the date electrode, whereby the risk of short circuit between the date electrode and the metallization layer is further reduced. (3) The transistor according to claim (1), wherein the window occupies approximately 20 to 40 inches of the area of the source electrode. (4) The date electrode and the source electrode. A field effect transistor having a metallization layer forming an electrode, wherein the metallization layer has a plurality of isolated windows that are not metallized, thereby increasing the threshold capacitance between the metallization layer and the gate electrode and the metallization layer. The field effect transistor is characterized in that the risk of short circuit between the gate electrode and the gate electrode is reduced. a semiconductor material comprising a source region, each source region including a plurality of orthogonally disposed extended areas accommodating contacts of a source electrode and a plurality of narrower areas interconnecting the extended areas; a semiconductor material; a tate electrode layer insulated over the semiconductor material; a source electrode metallization layer insulated over the tate electrode layer and forming a contact to the source extension area, the layer comprising said source electrode with a plurality of orthogonally placed unmetallized windows in said field effect transistor, wherein the probability of shorting between the source electrode layer and the date electrode layer and the interlayer capacitance are both reduced. With,
Field effect transistor as described above, characterized in that the orthogonal arrangement of the extended sub-regions and windows facilitates the use of a step-repeat method of transistor assembly.