JPS5880971A - Horizontal deflecting circuit - Google Patents

Abstract

PURPOSE:To improve the deflection frequency of the horizontal deflecting circuit of a television receiver, television camera, etc., and to stabilize the operation, by using a VCMM control voltage limiting circuit as a horizontal oscillation pulse width control type deflecting circuit. CONSTITUTION:A horizontal driving transistor (TR) 51 is driven, by the output of a variable pulse width output circuit 3 to obtain a rise period of a collector pulse of said TR51 coincident with timing set by a timing circuit under the control of a horizontal deflecting circuit. In this circuit, a level limiting circuit 12 is connected to between the output side of a phase difference detecting circuit 9 and the input side of the variable pulse width output circuit 3 to limit the output level of the phase difference detecting circuit 9 within a specified range, thereby limiting the width of pulse outputted from the variable pulse width output circuit 3. Consequently, deflecting operation in a transient period like a power supplying period is stabilized to obtain improved reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal deflection circuit for television receivers, television cameras, and the like.

FIG. 1 is a circuit diagram showing the configuration of a conventional horizontal deflection circuit, in which 1 is an A20 circuit and 2 is a horizontal deflection circuit 11.
Voltage controlled oscillator as a circuit, 4: horizontal drive circuit, 41ri: current limiting resistor, 42: tripe transformer, 43: drive transistor collector current accelerating capacitor, 51Fi: horizontal output transistor, 5: f
l, damper diode.

53#i, resonance capacitor, 54, horizontal deflection yoke,
55 indicates a flyback transformer.

FIG. 2 is a time chart of the voltage waveforms at each point A-E shown in FIG. 1 and the collector current waveform F of the horizontal output transistor 51.

The operation of the horizontal open circuit will be explained with reference to FIGS. 1 and 2. The FC circuit IFi in FIG. 1 compares the phase ratio # (frequency) of the horizontal synchronizing signal A and the flyback pulse C generated from the flyback transformer 55 (C in FIG. 2), and calculates the horizontal synchronizing signal A (FIG. If the oscillator 20-shot loss output B (Fig. 2 B) has a phase lead (high frequency) with respect to A), then
The control voltage of the voltage-controlled keepsake 2 is lowered, and the phase delay (M1
1 wave number is low), by increasing the control voltage, the time relationship between the horizontal synchronizing signal A and the flyback pulse C in FIG. The output B (OB in FIG. 2) of the voltage-controlled tokenizer 2 is controlled such that The scissor oscillation 820 output B drives the drive circuit 4, and the output of the cough drive path 4 drives the output transistor 51 via the transformer 42.

At this time, in order to perform the switching operation of the drive transistor and the output transistor 51KFi (not shown) of the drive circuit 4, the overexcitation rate is 1fi-g.
It is. As a result, as shown in FIG. 2, the storage times are Tsd (drive transistor) and T, respectively. (output transistor). The length of the storage time varies greatly depending on the fluctuations of the elements (transistors) K, temperature, or excitation conditions of the respective transistors. That is, the horizontal boundary rotation w1 is
Storage time of transistor with the above fluctuation Tsd * T
The width of each pulse is determined as shown in FIG. 2 on the premise that wo occurs.

The rise of the drive pulse in the second diagram must start from the time when the frying pulse C (collector pulse of the output transistor 51.1) becomes zero.
It must rise within the period until the collector current F of the output transistor 51 starts flowing as shown in FIG. Here, the time from the zero point of the flyback pulse C to the rising point 1 of the drive pulse D is Tmd + the time from the rising point of the drive pulse D to the point when the collector current F of the output transistor 51 starts flowing is Tml. In addition, the minimum value and maximum value of Batz Φ, fluctuation of the above accumulation time Tld e 'rso are respectively expressed as Tsd(min
) r Tid(max).

If Tso (mim) + Two (maw), then the minimum value Tmd (win) of the above time Tmd + Tm1 #
Tmi (min) u- can be expressed as in the following equation.

Tmd (mln) TP+Tad (min) Tr
Tso(max) =tl)8 Tm1(min)-2+Tr+Tao(min)'r
p Tsd (max) - i21 where TP is the oscillation pulse width IT, blanking period, T.

The Fi scanning period is shown. Here, Tmd (min) and Tm
Since it is desirable that 1 (rnin) be approximately equal,
If the oscillation pulse width TP is determined by setting Tmd(min)'''Tmi(min), it will be as follows.

Tp-”+Tr+2(Tso(win)+Tso(mi
x) Tad (min) Tsd (max))...
...(3) For example, when the storage time Tsd is (5 to 10) μsec and the storage time Tmo is (4 to 8) μsec, the horizontal frequency is 15.75 KHz (
This is the time of one running cycle. ), the oscillation pulse width TP
When calculated from equation (3), it becomes 23.4μ1lee, and (1)・(21 formula, Tmd(ml o )” Trni (min) is 8.4(μ5ec), and the oscillation pulse width TP is ±10%.
Even if the degree of deviation varies, the horizontal deflection operation is sufficiently normal. Assuming that the variation in missed pulse width TP is zero, with the worst combination of accumulation times "ad l 'r," shown above, Tmd
The horizontal deflection frequency fH (mix) at which −T+nl becomes 0 is, assuming the scanning llA rate τ is the same as when it is 15.75 KHz, fi+, f21, (Equation 33), and by substituting the upper value, the horizontal When the frequency reaches 45 KHz, the above margin disappears even if it is assumed that the fluctuation of the oscillation pulse +tlfil Tp is zero.In other words, at the same frequency at the horizontal edge above this, an element (transistor) is used to reduce the variation in the accumulation time Tad + T'ao. Alternatively, the accumulation time T+sd+Ti+.

It is necessary to control the oscillation pulse width TP so as to absorb the variation in the oscillation pulse width TP.

From this point of view, the oscillation pulse 1lli! The inventors of the present invention have separately proposed a horizontal deflection circuit using control of Tp and have applied for a patent.
An outline will be explained using figures. Figure 3 shows the excavation pulse width TP
2 is a road diagram (b) showing the configuration of a horizontal deflection circuit proposed by the Ministry of the Invention, etc. using a control method, and the same numbers as in FIG. 1 indicate the same functional blocks and elements; FIG. Further, FIG. 4 is a time chart of signals of various parts in the circuit of FIG. 3. In Fig. 3, M)'C1, C1, voltage controller 2
．． The drive circuit 4 and the subsequent output circuits operate in the same manner as the general horizontal deflection circuit described above. others,
3 is a voltage-controlled monostable multi-vibrator v-/ (
VCMM), 61d waveform shaping circuit, 7 is a reference pulse generation circuit, 8 is a waveform shaping/inverter circuit, 9 is
Phase detector, 10#'i, charge pump, 11Fi,
The operation will be explained with reference to Figs. 3 and 4, which show the low-pass filter. The drive pulse F (FIG. 4 F) from the drive circuit 4 is made into the output G (FIG. 4 G) through the waveform shaping/inverter 8, and the flyback pulse C
(FIG. 4C) is made into its output D (FIG. 4D) via the waveform shape path 6, and when the output falls, the reference pulse generating circuit 7 generates a pulse with a pulse width Tref. (Pulse E can also be obtained by delaying the output by a Tref period). Here, the falling edge of the pulse E between Tref M has a period Tr corresponding to the Tmd margin mentioned above.
Define e f. That is, phase detection is performed so that the falling edge of the pulse during the Tref period always coincides with the falling edge of the output G of the inverter 8. Charge pump 10. If the low-pass filter 11 controls the tt pressure flllJ II type monostatic multivibrator (vCMM) (the trigger of the VCMM3 is the voltage-controlled sericulture generator 2
(performed at the rise of output B (i4 Figure B)), accumulation time T
Even if sd*Tso varies or fluctuates, it is always Tmd "' Tref and Trni-T.

(, -Tmd)K is fixed and stable horizontal deflection operation can be performed.

Excavation pulse width TPO when the above control is performed
The control width is as follows◇T.

TP(wim)-Two(win) +Tr+ 4-
Tsd(max)I TP(max)-Tso(maw)+Tr+7-Tid
(mln) However, if the deflection is performed at a higher horizontal frequency without improving the paranki and fluctuation width of accumulation time %d*Tag, this control will reduce the accumulation time Tsd = T.
a.

Considering the worst condition of , the control width of TP is as follows.

, TP(mim) ” O TP(wax) -TH-Tsd(min) and normal operation is no longer possible.Furthermore, the characteristics of the control voltage versus pulse 1 area of the VCMM3 as a single unit in Fig. 3 are as shown in Fig. 5. As shown in , if the control voltage is given arbitrarily, the necessary control width (T
The excavation pulse width TP can be selected from a sufficiently wide range (P(win) to TP(wax)). In other words, at power-on, during the transition period of the control loop shown in Figure 3, the necessary TPQ pulse width cannot be obtained (Tmd<0, that is, the margin becomes less than zero), or the necessary NaT
If it is much wider than the P pulse width and CTrnt<0, that is, the margin becomes less than zero (1), normal operation cannot be performed.

The purpose of the present invention is to eliminate the drawbacks of the prior art described above, to realize a horizontal direction with a high frequency using components such as semiconductors that are currently commonly used, and to stabilize deflection operation during the transition period of power-on. The object of the present invention is to provide a horizontal deflection circuit that can

The main point of the present invention is that when operating at a high horizontal deflection frequency, under the worst conditions, the horizontal oscillation pulse width T'P (mln)
-0, or Tp(mix) = (THTs
d(min) ), so in this case Tmi(min
) + Tmd(mi'n) soT.

TP(rnin) r TP(max) are limited by approximately τ and IJ (within a range in which each takes a sufficiently positive value), and the transition period is taken into account, so that no control voltage is generated. Also, the VCMM 3 is limited so that only a control voltage that allows normal deflection operation is applied.

A specific example of the present invention will be described using the drawings.

Describe the operation using Kuo's constant as described in the explanation of the prior art. The storage time Tsd of the Doviput 2 transistor is (5 to 10) μm C
The accumulation time T'go of 9 output transistors is (4 to 8)μ
When the width C varies, the horizontal frequency f H (max)1 at which the minimum pulse width TP (mi.) - 0 is obtained is given by the following equation.

In addition, the maximum pulse width Tp (max) ” THTsd (
The horizontal frequency fH (max) 2 (min) is given by the following formula.

fH(max)1 * fH(max)2, whichever is lower, becomes the highest horizontal deflection frequency fH(wax) when Tmi is satisfied. maw) −fH(wax)1 and fH(
max) -65.3KHz. However, fH(ma
w) Since the stroke pulse duration TP is 0, the pulse width TP needs to be several μsec in order to perform normal operation.9For example, if the minimum pulse width Tp (m1m) is 2μ@ee, the practical maximum frequency is FHC-x)l #i is given by the following equation.

By substituting the above values, Fii(maX)l”49
2) The actual maximum frequency in the above-mentioned horizontal pulse width control is 49 KHz if each value takes the above values.

Furthermore, in order to ensure normal operation at the same horizontal frequency, the control voltage of VCMM3 is limited as follows.The horizontal pulse width control described above is as follows:
Control was performed so that Tmd z Tmiz '' was always maintained.Here, Tmd and 'rrni r:I should take a positive value under any conditions, Tmd *
Tm1T.

It's abbreviated to τ, so you don't have to make a big choice. Here, considering various variations, the minimum value of Tmd + Tmi that allows normal horizontal deflection operation is determined as Tmd (min) + T.
Suppose that m1(n+In) is Tmd('m1n
) + Tml (win) are both 1 jllsec, the maximum horizontal deflection frequency II FH (max) 2
Fi is given by the following formula.

Assuming that τ is the same as in a normal television receiver,
FH (wax) 2 #i66.1 KHz, Tm
By limiting the sales value of i, the deflectable iIk wave number becomes approximately 1.3S times. No matter what value the output voltage of the low-pass filter 11 in FIG.
) The control voltage of VCMM3 is limited so that it appears as follows. In other words, the characteristics of the output voltage of the low-pass filter 11 and the control voltage of the VCMM 3 may be limited by upper and lower limits as shown in FIG. A control voltage limiting circuit for obtaining this characteristic is shown in FIG.

In FIG. 7, 12 is a control voltage limiting circuit.

13 is a resistor, 14Fi is a diode, 15Ifi is a control voltage low limit power supply, 16 is a control voltage low limit power supply,
It is. Here, it is assumed that the output impedance of the low-pass filter 11 is sufficiently larger than the impedance of the power supplies 15 and 160 in FIG.

FIG. 8 is a circuit diagram of an 11-m water filter according to the present invention.

Comparing this figure with FIG. 3, we can see that the low-pass filter 11 and V
The only difference is that a control voltage limiting circuit 12, the details of which are shown in FIG. 7, is connected to the CMM 3, but the rest is the same. Since the explanation of the circuit operation of FIG. 8 is already clear from the foregoing, it will not be described further. In addition, VC
At the same time, the above-mentioned side @ of the control voltage of MM3 has the effect of stabilizing the deflection operation during a transition period such as when the power is turned on.

According to the present invention, by using the VCMM voltage limiting circuit in the horizontal pulse control phosphor type deflection circuit, the maximum horizontal frequency at which normal deflection can be performed can be increased by approximately 1.4 times. Moreover, it is possible to simultaneously stabilize the deflection production during a transition period such as when the power is turned on, and improve the reliability of the horizontal deflection circuit.In addition, the cost increase due to implementing the present invention is very small.

[Brief explanation of drawings]

Figure 1 is a (b) schematic diagram showing a conventional horizontal deflection circuit, Figure 2 is a time chart showing the waveforms of various signals in the circuit of Figure 1, and Figure 3 is another proposal by the inventors. A circuit diagram showing the horizontal deflection circuit, Fig. 4 is a time chart showing the waveforms of the signals in each part of the circuit K>ff in Fig. 3, and Fig. 5 is the voltage-controlled mono staple in Fig. 3! Fig. 6 is a characteristic diagram of the multivibrator (VCMM) 3, Fig. 6 is a control voltage limiting characteristic diagram of the VCMM 30 adopted in the present invention, Fig. 7 is a line diagram showing the VCMM control voltage limiting circuit used in the present invention, *awJ is the main 1 is a circuit diagram showing one embodiment of the invention. Symbols: 1 is a MuFC circuit, 2 is a voltage controlled oscillator, 3 is a voltage controlled mono-staple multivibrator, 4Fi horizontal drive circuit, 41tj current limiting resistor, 42tfi drive transformer, 43Fi drive transistor collector current accelerating capacitor, 51#'i Output transistor, 52t
j damper diode, 53 is a common capacitor, 54#i
Horizontal deflection yoke, 55 is a flyback transformer, 6 is a waveform shaping circuit, 7Fi base pulse generation circuit, 8F1 waveform shaping reed circuit, 9 is a phase detector, 10Fi charge pump, 11110 - bus filter, 12 is a control Voltage limiting circuit, 13 is a resistor, 14 is a diode, 15 is a power supply for control voltage low/heavy 11 Kuma, 16Fi control voltage high limit power supply. Agent: Patent attorney Namiki Fuo (Figure 4, Figure 5, Figure 6) low eight 74 ruta wide '7'jE) t-

Claims (1)

[Claims] l) A scan rounding horizontal deflection circuit comprising a horizontal output ms path, a drive transistor, and a horizontal output transistor which is driven by the output of the drive transistor; po: a timing circuit for setting a signal generator delayed by approximately one horizontal scanning period from the edge of the flyback pulse generated at the F letter;
a phase difference detection circuit that detects the zero phase difference between the rising edge of the collector pulse of the horizontal drive transistor and the zero phase difference between the timing set by the tie ZB path; and a variable pulse width output circuit whose output pulse width is controlled by the output of the phase difference detection oil path, and by driving the horizontal drive transistor with the output of the variable pulse width output circuit. In the horizontal deflection circuit that controls the rise timing of the collector pulse of the horizontal drive transistor to match the timing set by the timing circuit, the output side of the four phase difference detection circuits and the pulse width variable output circuit When the output level from the 1 phase difference detection circuit exceeds a certain range, a level limiting circuit is connected between the input signal and the output signal to limit it within a certain range and supply it to the variable pulse width output circuit. Variable Pulse Width Output Circuit A horizontal deflection circuit characterized by limiting the pulse width of multiple output pulses to improve deflection frequency and stabilize operation.