JPS5879435A - Power source supply system for electronic equipment - Google Patents

Power source supply system for electronic equipment

Info

Publication number
JPS5879435A
JPS5879435A JP56177873A JP17787381A JPS5879435A JP S5879435 A JPS5879435 A JP S5879435A JP 56177873 A JP56177873 A JP 56177873A JP 17787381 A JP17787381 A JP 17787381A JP S5879435 A JPS5879435 A JP S5879435A
Authority
JP
Japan
Prior art keywords
circuit
alarm
power
voltage
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56177873A
Other languages
Japanese (ja)
Inventor
近井 智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Telecom Networks Ltd
Original Assignee
Fujitsu Telecom Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Telecom Networks Ltd filed Critical Fujitsu Telecom Networks Ltd
Priority to JP56177873A priority Critical patent/JPS5879435A/en
Publication of JPS5879435A publication Critical patent/JPS5879435A/en
Pending legal-status Critical Current

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  • Direct Current Feeding And Distribution (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (11発明の技術分野 本発明は供給電圧の低下を監視するアラーム回路を備え
た電子機器用電源供給方式の改良に関す。
DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to an improvement in a power supply system for electronic equipment equipped with an alarm circuit for monitoring a drop in supply voltage.

(2)技術の背景 トランジスター、■C等各種電子部品、あるいはこれ等
に加えてリレー、モーター等の機械的部品を含んで構成
される各種の電子機器の供給電源としては、各種の規定
電圧を発生させる個々の2次撞線を備える電源トランス
、整流回路、平滑回路、および正規の機能を行わせるた
めに各種規定電圧間の付与順序、換言すれば付与時間の
制御、又動作中の不時の過電流等による規定電圧の低下
を監視するアラーム回路等から構成される。
(2) Background of the technology Various specified voltages are used as power supplies for various electronic devices that include various electronic components such as transistors and ■C, or mechanical components such as relays and motors in addition to these. A power transformer, a rectifier circuit, a smoothing circuit with individual secondary wires to be generated, a rectifier circuit, a smoothing circuit, and control of the application order, in other words, the application time between various specified voltages in order to perform the normal function, as well as the control of the application time, and the control of the application time during operation. It consists of an alarm circuit that monitors a drop in the specified voltage due to overcurrent, etc.

例えばトランジスター、IC等の半導体部品への供給電
圧として5V、あるいは!2Vが準備され、リレー、モ
ータ等の機械的部品への供給電圧として24Vが準備さ
れる電源供給方式においては、電源投入に際して先ず5
v1あるいは12Vが所定回路に供給され、短時間遅れ
てu■が供給されるよう設計される。これは機械的部品
の動作に先立ってその制御回路が予め準備されているこ
とが必要であるからである。同時に電源断に際しては機
械的部品への供給電圧24Vが断になって後5■、ある
い4;! 12 Vの供給電圧が若干遅れて断となる。
For example, 5V as a supply voltage to semiconductor components such as transistors and ICs, or! In a power supply system where 2V is prepared and 24V is prepared as the supply voltage to mechanical parts such as relays and motors, first 5V is prepared when the power is turned on.
It is designed so that v1 or 12V is supplied to a predetermined circuit, and after a short delay, u■ is supplied. This is because the control circuit must be prepared in advance of the operation of the mechanical component. At the same time, when the power is cut off, the 24V supply voltage to the mechanical parts is cut off and then 5■ or 4;! The 12 V supply voltage is disconnected with a slight delay.

第1図は横軸に時間tをとって、上記各種供給電圧の時
間的推移を示すもので、Tnは電源投入時点をTfは電
源断の時点を示す。
In FIG. 1, time t is plotted on the horizontal axis to show the time course of the various supply voltages mentioned above, where Tn indicates the time when the power is turned on and Tf indicates the time when the power is turned off.

u■の電源投入時Tnからの遅れ時間t1、および5■
、あるいは12Vの電源断時Tfからの遅れ時間t2は
共に夫々の電源供給回路の機能の−・つとして形成され
ている。
Delay time t1 from Tn at power-on of u■, and 5■
, or the delay time t2 from the 12V power-off time Tf are both formed as one of the functions of the respective power supply circuits.

夫々の供給電圧に対するアラーム回路は、個々に設ける
不経済性を避けるため共通回路として構成される:り、
そのためには第1図に示ずtl、t2の時間帯において
この共通のアラーム回路の゛機能を停止しておくことが
必要である。なぜならば、この電子機器の正常な動作時
間は、該機器に各種規定電圧の与えられている期間1時
間であるからである。
The alarm circuits for each supply voltage are configured as a common circuit to avoid the uneconomical cost of installing them individually:
For this purpose, it is necessary to stop the function of this common alarm circuit during time periods t1 and t2 (not shown in FIG. 1). This is because the normal operating time of this electronic device is one hour during which various specified voltages are applied to the device.

(3)従来技術と問題点 従来このためには電源トランスに特別の2次暗線を設け
、TTL(トランジスタ、トランジスタロジック)等の
複雑な組合せからなる独立した回路が使用されていたた
め、生産原価をたかめ、更に部品点数の多い点からも回
路の信頼度低下の因をなしていた。
(3) Prior art and problems Conventionally, for this purpose, a special secondary dark line was provided in the power transformer, and an independent circuit consisting of a complex combination of TTL (transistor, transistor logic) etc. was used, which reduced production costs. In addition to being expensive, the large number of parts also contributed to a decrease in the reliability of the circuit.

(4)発明の目的 本発明はこれ等の欠点を除去した新規なこの種電源供給
方式を提供することをその目的とする。
(4) Purpose of the Invention It is an object of the present invention to provide a novel power supply system of this type that eliminates these drawbacks.

(5)発明の構成 本発明のこの目的は電源トランスの主直流電源供給欅綿
の一つより直接導出される直流電圧が少なくとも一つの
主供給直流電圧と共にアラーム検出回路の設けられた時
定数をもつスイッチング回路を制御する構成となすこと
によって達成される。
(5) Structure of the Invention This object of the present invention is that the DC voltage directly derived from one of the main DC power supply lines of the power transformer has a time constant of an alarm detection circuit together with at least one main DC voltage supply. This is achieved by configuring a configuration that controls a switching circuit with

換言すれば従来のように電源トランスに特別な2次暗線
を設けて独立したアラーム禁止回路を設ける代りに、ア
ラーム検出回路に既述の禁止機能を持たせた構成を提供
するものである。
In other words, instead of providing an independent alarm inhibiting circuit by providing a special secondary dark line in the power transformer as in the prior art, a configuration is provided in which the alarm detection circuit has the above-mentioned inhibiting function.

アラーム検出回路には主供給直流電圧の一つが規定電圧
より規定以上に低下した際アラーム回路を閉結させるス
イッチング素子、例えばサイリスターが設けられる。こ
れに時定数回路を付加して、電源投入時より若干時間線
アラーム回路の閉結を阻止機能をもたせることによって
、第1図に示すt1時間過渡的に生ずる可能性のあるア
ラーム回路の誤動作を防止する。
The alarm detection circuit is provided with a switching element, such as a thyristor, which closes the alarm circuit when one of the main supply DC voltages falls below a specified voltage by more than a specified value. By adding a time constant circuit to this and providing a function to prevent the time line alarm circuit from closing slightly from the time the power is turned on, malfunctions of the alarm circuit that may occur transiently at time t1 shown in Figure 1 can be prevented. To prevent.

(6)発明の実施例 第2図は本発明の1実施例を示す要部回路図で、電源ト
ランス1の1次暗線2に商用電源が供給され、2次暗線
3.3’ 、3”は夫々整流回路、平滑回路、および遅
延回路等を含む回路網4.4°、4”を経て、夫々5■
、12V、24Vの主直流電圧を供給する。この際の回
路網4.4°申に含まれる遅延機能は第1図のt2時間
、回路網4”中に含まれる遅延機能は同図のt1時間に
該当するものである。
(6) Embodiment of the Invention FIG. 2 is a circuit diagram of a main part showing an embodiment of the present invention, in which commercial power is supplied to the primary dark line 2 of the power transformer 1, and the secondary dark lines 3.3', 3'' pass through 4.4° and 4" circuit networks including rectifier circuits, smoothing circuits, delay circuits, etc., respectively, and
, 12V, 24V main DC voltage. In this case, the delay function included in the circuit network 4.4° corresponds to time t2 in FIG. 1, and the delay function included in the circuit network 4'' corresponds to time t1 in the same figure.

一方2次(巻線3″より直接引き出され整流された直流
電圧は抵抗R1を経てシーケンス回路等の制御用電源C
Pとして供給され、又更に抵抗R2を経てトランジスタ
Qのコレクターに供給され、又そのベースにはツェナー
ダイオードDI D2等を介して図示のように供給直流
電圧の24V、5■が付与されている。
On the other hand, the secondary (DC voltage drawn directly from winding 3'' and rectified) passes through resistor R1 to control power supply C for sequence circuits, etc.
It is further supplied to the collector of the transistor Q via a resistor R2, and the supply DC voltage of 24V, 5.5V is applied to its base via a Zener diode DID2, etc., as shown.

又トランジスタQのコレクター電圧は抵抗R3、コンデ
ンサC1からなる時定数回路、およびツェナーダイオー
ドD3、平滑回路を経てアラーム回路ALに挿入された
サイリスク−Thに付与されている。鎖線に囲まれた部
分がアラーム検出回路とアラーム禁止回路を構成してい
る。
Further, the collector voltage of the transistor Q is applied to the thyrisk-Th inserted in the alarm circuit AL via a time constant circuit consisting of a resistor R3 and a capacitor C1, a Zener diode D3, and a smoothing circuit. The portion surrounded by chain lines constitutes an alarm detection circuit and an alarm prohibition circuit.

先ず正常状態(第1図のT期間)についての機能を説明
する。
First, the functions in the normal state (period T in FIG. 1) will be explained.

この状態においては24vも5vも正常電圧にあり、ト
ランジスターQのベース電位も正常電位でオン状態にあ
り、コレクター(B点)電位(よ低くツェナーダイオー
ドD3はオフ状態で、従ってサイリスタThもオフ状態
でアラーム回路ALは断たれている。
In this state, both 24v and 5v are at normal voltages, the base potential of transistor Q is also normal and on, and the collector (point B) potential is lower (lower), and Zener diode D3 is off, so thyristor Th is also off. The alarm circuit AL is cut off.

24V、あるいは5■の供給直流電圧が何らかの原因(
例えば過負荷)で規定値以下に降下すれ(f1トランジ
スタQのベース電位が下がってオフ状態となり、コレク
ター電位が上昇してツェナーダイオードD3をオン状態
に転換し、サイリスク−Thのゲート電圧が供給されて
これをオンに転換し、アラーム回路ALをと閉結する。
If the supply DC voltage of 24V or 5■ is caused by some reason (
For example, if the base potential of f1 transistor Q falls below the specified value due to overload (for example, overload), the base potential of f1 transistor Q falls and turns off, and the collector potential rises and turns Zener diode D3 on, supplying the gate voltage of Thyrisk-Th. turns it on and closes the alarm circuit AL.

次に第1図に示す電源投入よりの期間t1においてはア
ラーム回路ALが断の状態に保持される機能につき説明
する。
Next, a function for keeping the alarm circuit AL in an OFF state during a period t1 from power-on shown in FIG. 1 will be explained.

電源投入と同時にトランジスタQのコレクタ電位が上り
、24V供給監圧の未だ付与されないためにアラーム回
路ALのサイリスターThがオンになるのを防止するた
め、抵抗R3とコンデンサーC1よりなる時定数回路が
コレクタ・ノミツタ−間に接続されている。第1図下段
に示すようにトランジスタQのコレクタ電圧は24Vが
ベース電極に付与されるまでのt1期間増大し、付与さ
れるやトランジスタQのオンになると共に零電位に降下
して定常状態となる。以降供給直流電圧の低下によりア
ラーム回路ALが閉結状態に転換すること既述の通りで
ある。
The collector potential of the transistor Q rises at the same time as the power is turned on, and in order to prevent the thyristor Th of the alarm circuit AL from turning on because the 24V supply supervision pressure is not yet applied, a time constant circuit consisting of a resistor R3 and a capacitor C1 is connected to the collector.・Connected between chisels. As shown in the lower part of Figure 1, the collector voltage of the transistor Q increases for a period of t1 until 24V is applied to the base electrode, and once it is applied, the transistor Q turns on and drops to zero potential, reaching a steady state. . As described above, the alarm circuit AL is then switched to the closed state due to a decrease in the supplied DC voltage.

電源断となるや、5■、あるいは12Vの供給電圧がt
2期間残存していても、トランジスタQのコレクタ電位
が零電位であるためアラーム回路ALが閉結状態にはな
り得ない。
When the power is cut off, the supply voltage of 5 or 12 V is
Even if two periods remain, the alarm circuit AL cannot be closed because the collector potential of the transistor Q is zero potential.

(7)発明の詳細 な説明のように本発明においては、従来のようにアラー
ム禁止機能をもたせるために電源トランスに独立した2
次撞線を設ける必要なく、当然必要とするアラーム検出
機能に時定数をもつスイッチング回路を付加することで
禁止機能を合せ持たせることを可能とし、構成自体を簡
易化し、従って部品点数の増大からくる信頼度の低下も
避けられる等幾多の効果をもつものである。
(7) As described in the detailed description of the invention, in the present invention, two independent
By adding a switching circuit with a time constant to the naturally necessary alarm detection function, it is possible to provide a prohibition function without the need to provide a secondary conductor, simplifying the configuration itself and reducing the number of parts. This has many effects, such as avoiding a decline in reliability.

元より本発明は図示実施例で限定されるものでなく、「
特許請求の範囲」内で適宜変形実施できる。
Originally, the present invention is not limited to the illustrated embodiments;
Appropriate modifications may be made within the scope of the claims.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はアラーム禁止機能を説明するための特性図を、
第2図は本発明による電源供給方式の1実施例を示す要
部回路図である。 図において1は電源トランス、Qはトランジスタ、Di
、D2.D3はツェナーダイオード、]゛hはサイリス
ター、R1,R2,R3は抵抗、Cはコンデンサー、A
Lはアラーム回路を示す。
Figure 1 shows a characteristic diagram to explain the alarm prohibition function.
FIG. 2 is a main circuit diagram showing one embodiment of the power supply system according to the present invention. In the figure, 1 is a power transformer, Q is a transistor, and Di
, D2. D3 is a Zener diode, h is a thyristor, R1, R2, R3 are resistors, C is a capacitor, A
L indicates an alarm circuit.

Claims (1)

【特許請求の範囲】[Claims] 電源トランスの主直流電源供給捲線の一つより直接導出
される直流電圧が、少なくとも一つの主直流供給電圧と
共にアラーム検出回路に設けられた時定1をもつスイッ
チング回路を制御することを特徴とする供給電圧の低下
を監視するアラーム回路を備えた電子機器用電源供給方
式。
characterized in that the direct current voltage derived directly from one of the main direct current supply windings of the power transformer controls a switching circuit with a time limit 1 provided in the alarm detection circuit together with at least one main direct current supply voltage. A power supply system for electronic equipment equipped with an alarm circuit to monitor a drop in supply voltage.
JP56177873A 1981-11-06 1981-11-06 Power source supply system for electronic equipment Pending JPS5879435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56177873A JPS5879435A (en) 1981-11-06 1981-11-06 Power source supply system for electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56177873A JPS5879435A (en) 1981-11-06 1981-11-06 Power source supply system for electronic equipment

Publications (1)

Publication Number Publication Date
JPS5879435A true JPS5879435A (en) 1983-05-13

Family

ID=16038547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56177873A Pending JPS5879435A (en) 1981-11-06 1981-11-06 Power source supply system for electronic equipment

Country Status (1)

Country Link
JP (1) JPS5879435A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117625A (en) * 1987-10-30 1989-05-10 Nec Corp Power source monitoring circuit
JPH0358716U (en) * 1989-10-14 1991-06-07

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310042A (en) * 1976-07-15 1978-01-30 Komatsu Mfg Co Ltd Protection signal genenation circuit for control device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310042A (en) * 1976-07-15 1978-01-30 Komatsu Mfg Co Ltd Protection signal genenation circuit for control device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117625A (en) * 1987-10-30 1989-05-10 Nec Corp Power source monitoring circuit
JPH0358716U (en) * 1989-10-14 1991-06-07

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