JPS5879360A - Modulation circuit - Google Patents

Abstract

PURPOSE:To perform the data transmission with high speed and reliability by applying phase-modulation on data with two J-K flip-flops for transmission. CONSTITUTION:A modulation circuit 4 consists of J-K flip-flops (FFs) 41, 42. A transmission data signal is inputted to a CLR terminal of the 1st FF41. EAch terminal of J, K goes to a high level. The CLR terminal of the 2nd FF42 is grounded and each terminal of J, K is connected in common to the inversion Q' terminal of the 1st FF41. In the circuit like this, a data signal from an input terminal 3 is phase-modulated with each FF triggered at the leading of a clock signal from a clock terminal 40, corresponding to the high and low level of data. A modulation signal is transmitted via drive circuit 5. Thus, the high speed data transmitted via a drive circuit 5. Thus, the high speed data transmission with high reliability can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION α) Technical Field of the Invention The present invention relates to a modulation circuit for a transmission device that transmits data through a transmission line.

(2) Conventional technology Conventionally 9 For example, 1.0 (H) of data to be transmitted.

L) K Oscillation signal of a predetermined frequency or its stop (zero)
Transmission was performed by matching signals.

However, if one oscillation signal is used, 1 bit MB of data requires at least several cycles, and the length increases by 7t, making it unsuitable for high-speed transmission.

0) Purpose of the invention The purpose of this invention is to look at 9 or more points k11 and obtain a signal.

It is an object of the present invention to provide a round modulation circuit that achieves high speed and high reliability by performing phase modulation for transmission.

(4) Embodiment of the Invention FIG. 1 is an explanatory diagram of the configuration of a data transmission device according to the invention.

In the figure, 1 is a transmitting circuit, 2 is a receiving circuit, and T is a transmission line LK transmitting circuit 1. This is a transformer that connects the receiving circuit 2. The feeder 41 link 1 is supplied with 1, 0 (
H, L) transmission data signals are input, and 1 of this data is input.
A circuit that outputs one cycle of pulses corresponding to bits.
4. Modulation circuit that changes the phase of the output pulse signal only when LK changes. If you look at it differently, the ζO variable modulation circuit 4 Kara signal is a long and short paddle signal and 1-9,
The drive circuit 5 is configured to output a signal with a low peak value and a signal with a high peak value in accordance with the length. E9. The receiving circuit 2 includes a signal detection circuit 6. which detects the presence or absence of a received data signal. and the detection of this signal detection circuit 6, based on the ratio signal]
The demodulation circuit 7 demodulates received data and outputs the original data signal to an output terminal 8.

The data signal transmission format is the same as shown in FIG.

The transmitted data is KH (high) as shown in the first half of Figure 2 (0).
As shown in the first half of Figure 2 (←), when the signal is at the level, the transmission signal form is a signal with the same waveform as the previous pulse signal by adding one cycle of pulses in correspondence with lpi)K. , when the transmitted data is at the KL(a-) level as shown in the second part of Fig. 2 (0), the transmission signal form changes the phase of the previous pulse signal as shown in the second part of Fig. 2). The signal is inverted 180 degrees to produce nine waveform signals.

When transmitting, the data shown in Figure 2) is modulated into the pulse signal shown in Figure 2 ←).

When receiving, the 0 pulse signal is demodulated into the data of the 2nd rlA (branch) in order to demodulate the 0 pulse signal into the data of the 2nd rlA (branch). There are t*, H, and L level signals, and the transmission signal of data such as Ryoji 2 Figure 00 is In the second rlA), K becomes K as shown in (). Note that the phase of H may be reversed.

No. 31I is a configuration explanatory diagram showing an embodiment of the shipping route. tf magic key link 4 will be explained.

The modulation circuit 4 is supplied with the transmission data signal from the input terminal 3 to the clear terminal CLRK, and the J terminal is set to H (high) level, and the output data signal from the input terminal 3 is set to the H (high) level.
Ship and
The output of the L terminal is simultaneously supplied to the J terminal, the clear terminal is grounded and always at zero level, and the output signal is taken from the Ql terminal. yo) It is composed of 7 lipfs! Tsubu circuit 41, 4
Each clock terminal CKK is supplied with a clock signal of a predetermined period from the clock terminal 4G, and is triggered by the rising edge of the clock signal.

The operation of the modulation circuit 4 will be explained with reference to FIG.

Each 7-lip 70-tub circuit 41, 42K is supplied with a lock signal as shown in Figure 4 (sub), and receives H, L, H, L, L, H data signals as shown in Figure 4 (b). is supplied to the first J- to the clear terminal of the flip-flip circuit 41, making it 9. In addition, J-nifuri, pufuro.

In the pull circuit, when the clear terminal is at H level, the Q terminal is always high, and when the Q terminal is at H level, the clear terminal is at L level, and both the tJtK terminals are at H level, the Q and Q terminal outputs are set at the rising edge of the lock signal. , each inverted, and K.

When it is L, the state of '4h is maintained. (See table below)
184 When the link shown in Figure 0) is entered, the first J
- When data H is supplied to the clear terminal of the -Ky lip 70 tube circuit 41, its Q1 terminal output becomes H. The next time the four squares ■ are entered, it is also H'. When the clock is ■, the data is L.

When this is supplied to the clear terminal, the Qt terminal output is inverted and becomes L-. Even at the time of 0 clock (2), the data is rounded from L and inverted, and the Ql terminal output becomes H. When the input signal is set to ■, the data becomes Ho9, and the Q1 terminal output becomes H. In the same way, the output as shown in Fig. 4 f→ is the first 7 lips 70.
Ql terminal of the tube circuit 41) can be obtained.

This Ql terminal output is simultaneously supplied to the terminal J of the second 7-lip 70-tub circuit 42. When it comes to Kutsuku■,
The clear terminal is L and J, and the clear terminal is H, so t Q! The terminal output is inverted and becomes H. When it is four times ■, the terminals J and J are H, so t Q! The terminal output is inverted and becomes L. When the clock is ■, J.

Since the K terminal is still H, the Φ terminal output is inverted and becomes H.0
When the clock is ■, the terminal is J, and the terminal is L, so Q! The terminal output maintains its original state and is at H level.

When the error is 0, the J terminal is still H, and the Q! The terminal output is inverted and becomes L. Similarly, an output as shown in FIG. 4(c) is obtained from the Q2 terminal of the 7g2 7-lip 70-p circuit 42.

This 1lN4E (c) signal is the H,
It is delayed by one clock in response to the L signal, and for the H level, it becomes a signal with the same waveform as the previous signal, and for the L level, it becomes a signal that is 180 degrees inverted from the previous signal. The output data is one-phase modulated and transmitted via the primary stage drive circuit 5.

Note that the output terminals of the 7-rip, 70-tub circuits 41 and 42 must be connected to J-! Terminals other than those listed above can also be used depending on the requirements.

Next, the drive circuit 5 will be explained.

Referring again to FIG. 3, the drive circuit 5 is 9-phase modulated as shown in (4ffi) and the dead output signal is a mixture of long pulse width signals and short pulse width signals, resulting in round short pulses. A long/short pulse detection circuit 51 that looks like a signal and detects its length. and a first driver 52 driven by the long/short pulse detection signal of the long/short pulse detection circuit 51. The driver 53 of #I2 is made up of more than one driver. The first driver 52 is
The second driver 53 receives the transmission data from the modulation circuit 4 and outputs a signal with a low peak value E1 only when the transmission data is a long signal according to the long pulse detection signal of the long and short pulse detection circuit 51. In response to the short pulse detection signal from the detection circuit 51, a signal with a high peak value E2 is output.

Since the width of the long pulse signal is twice the width of the short pulse signal, the peak value E2 may be twice as large as El, and the peak values are different as shown in FIG. 50). A signal such that the integral value e(Dc a +)+ for one arbitrary period becomes zero is transmitted via the transformer T to the transmission line AK.

Therefore, the integral value from zero point a to zero point cl is zero), and the integral value from zero point to zero point d is also zero,
The integral value of any one period is always zero.

In this way, the transmission line AK has a CR distributed constant tube and is rounded. If a long signal and a short signal are transmitted at the same peak value, energy will accumulate on the long signal side and the zero point will be dragged and become unstable, resulting in correct transmission. However, if you always set the integral value of any one cycle to zero, no energy accumulation will occur, zero point fluctuation will not occur, and the received waveform will not be violent as shown in Figure 5 ←). This results in fewer correct signals.

FIG. 6 is a configuration explanatory diagram showing one embodiment of the receiving circuit 2. As shown in FIG.

In the figure, a data signal transmitted through a transmission line t is passed through a transformer T to a signal detection circuit 6. The signal is supplied to the demodulation shaft path 7. The signal detection circuit 6 has an H signal as shown in FIG. 7(A).
, H, H, L, H, L, L, H data signal presence/absence and carrier detection rounding level comparator 61. A rectifier circuit 62 rectifies the output of the level comparator 61 to a predetermined level, and a delay circuit 63 delays the output of the rectifier circuit 62 by 1 bit or 2 bits as shown in Figure 2 to generate a dead output. Furthermore, a carrier signal can be taken out from the output terminal 60. The demodulation circuit 7 includes a waveform shaping circuit 71. such as a hysteresis comparator that shapes the waveform of a data signal as shown in FIG. 7(0). An edge detection circuit 72 such as a differentiator circuit that detects edges of the waveform shaping circuit 71 and generates edge pulses. A program counter 73 that has a delay function and functions as a single-stable multivibrator that generates a pulse signal of a predetermined width with a predetermined time delay each time the edge detection circuit 72 is triggered. The output of the program counter 73 is supplied to the DI terminal.
Lip 7ay pump circuit 74. The output of the D-type first 7-rig frog circuit 74 is connected to the D2 terminal and the clear terminal C.
It is also configured with a D-type second 7-lip 7a tag circuit 75 which is supplied to LR2. Note that the delay circuit 63 is also used.

Edge detection circuit 72. The program counter 73 is delayed by one bit and the first . Second 7-rig circuit 74.
75 is designed to operate with a 2-bit delay.

Note that the delay circuit 63 may be considered as a separate component from the signal detection circuit 6.

The operation of the receiving circuit 2 will be explained with reference to FIG.

The data shown in FIG. 7 0) is supplied to the edge detection circuit 72 via the waveform shaping circuit 71, and
The operation is started with a delay of one bit by a carrier detection signal as shown in the figure), and the minimum interval as shown in FIG. 7 generates an edge pulse of half a bit of output data. This edge pulse is loaded into the program 2 controller 73, and the 1st edge pulse is loaded into the program 2 controller 73. Second flip-flop circuits 74, 75
The clock terminal CKK is supplied to perform the operation.

The output of the program counter 73 is output from the edge detection circuit 72.
As shown in Fig. 7C, the rising edge signal of the edge pulse is delayed by the time t1 that it can rise before the secondary edge pulse arrives, and the time width is 1 g, which is reset by the falling edge of the primary edge pulse. Generates a pulse signal. Therefore, a pulse signal is generated after a predetermined time t:L delay with the edge pulse ■, and the next edge pulse ■ is generated within t2 hours.
It is reset at the falling edge of edge pulse 0, and the next pulse width signal is generated again at the rising edge of edge pulse 0,
A similar pulse signal is obtained from the Qo terminal. The pulse width signal caused by the edge pulse (2) has a wide interval up to the 9th edge pulse (2), and automatically falls. Similarly, a QO terminal output such as the 7th -(→ is supplied to the D1 terminal of the first flip-flop circuit 74.

The first flip-flop circuit 74 starts operating with a delay of 2 bits, and due to the edge pulse ■) e Qo terminal output is H, so its Ql terminal output is H. Even with the edge pulse ■, the QO terminal output is H, so its Ql terminal The output is H, edge pulse C and the QO terminal output is L.

The Ql terminal output is high, and the Qo terminal output is H at edge pulse ■, so t.The Ql terminal output is H, and Q at edge pulse C.
Since the O terminal output is H, the Q1 terminal output is H, and so on.
Thereafter, in the same manner, an output as shown in FIG. 7(E) is obtained from the Q1 terminal of the first flip-flop circuit 74.

It is supplied to the D2 terminal and clear terminal of the second flip-flop circuit 65.

The second flip-flop circuit 75 also starts operating with a 2-bit delay, and at edge pulses ■ and ■, the Q1 terminal output is high.
Therefore, its Q2 output is also H. When the edge pulse is ■, the Qt terminal output is not L, and the Q2 terminal output is cleared and the Q2 terminal output is high, and when the edge pulse is 0, the Q1 terminal becomes low.

The output HE rises, but since it is tffL, the clear works and the Q2 terminal output goes up.Since the edge pulse is 0 and the output of the beam terminal goes H, the Q2 terminal output does not go up. The output can be obtained from the Q2 terminal, and the output can be obtained from the output terminal 70.

This is shown in Figure 7 (excluding the first two bits of 4, H, L
, H, L, L, and so on, resulting in a correctly demodulated signal.

Note that a band pass filter or a PLL (7-axis lock loop) may be used in place of the rectifier circuit 62 of the signal detection circuit 6 to extract only the received signal of the required frequency and obtain the carrier detection signal. good. Alternatively, the level converter 1 of the signal detection circuit 5 may be omitted, and the outputs of the demodulation circuit 70 and the waveform circuit 71 may be used in common.

(5) Summary of the Invention As described above, this invention uses a flip-flop circuit for two J-, and the pulse signal before the output signal is set to 9, which corresponds to the low level of the transmission data. This is a modulation circuit designed to output a signal with the same waveform as or a signal whose phase is reversed by 180 degrees.

(6) Effects of the Invention Accordingly, with an extremely simple configuration using two flip-flop circuits, it is possible to phase-adjust transmission data, resulting in low cost, high speed, and high reliability.

[Brief explanation of drawings]

#I1 is a configuration explanatory diagram showing one embodiment of the transmission device according to this f14, FIG. 2 is a waveform diagram for explaining the operation of the drive circuit, and FIG. 6 is a waveform diagram for explaining the operation of the drive circuit. FIG. 7 is a waveform diagram for explaining the operation of the receiving circuit. 1... Transmission circuit, 2... Receiving circuit, 4... Modulation circuit. 5... Drive circuit, 6... Signal detection circuit, 7... Demodulation circuit. 41.42...Flip-flop circuit at J-, 51.
... Long and short pulse detection circuit, 52.53 ... Driver, 63 ... Delay circuit, 71 ... Waveform shaping circuit, 72
...Edge detection circuit. 73...Program counter, '14.7rs...
・Flip-flop circuit patent applicant Chino Seisakusho Co., Ltd.

Claims (1)

[Claims] 1. Transmission data is supplied to the clear terminal, and the J terminal is set to high level, and the flip 7 four-tub circuit goes to the J- of the good path 1, and the 7 lip-flop circuit outputs to the 1st OJ- at the same time to the KJ terminal. The second J-Ky9 tube 7a supplied to
The high level 19 of the transmission data corresponds to the low level and is the same as the pulse signal before the output signal.
The waveform signal converter is a modulation circuit that outputs a 180-degree inverted signal after phase modulation.