JPS5864848A - Data transmitter - Google Patents

Abstract

PURPOSE:To speed up a titled data transmitter and to make it highly reliable, by phase-modulating transmission data into long and short pulses, transmitting signals corresponding to the pulses with different peaks, and detecting and demodulating the signals at the reception side. CONSTITUTION:Transmission data of H, L is inputted from a terminal 3 at a transmission circuit 1, a modulating circuit 4 outputs pulses of one period corresponding to 1-bit of this data and changes the phase of a pulse signal outputted only at the change to L. This phase-modulated signal becomes a long and short pulse signal on the other hand, and this signal is applied to a driving circuit 5. The circuit 5 converts the signal into a signal with a low and high peak value corresponding to the length of pulses and outputs the signal from a transformer T. A reception circuit 2 detects the presence/absence of a reception data signal inputted from the transformer T at a signal detecting circuit 6, this detecting signal demodulates the reception data into an original data at a demodulation circuit 7 and outputs the data signal from a terminal 8. Since one pulse is enough for one bit, the redundancy is less and high-speed transmission can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a data transmission device that transmits and receives data through a transmission line.

(2) Prior Art Conventional 1 For example, data is transmitted by associating 1.0 (H, L) of the data to be transmitted with an oscillation signal of a predetermined frequency or its stop (zero) signal.

However, when a single oscillation signal is used, at least several cycles are required for each bit of data, and redundancy increases accordingly, making it unsuitable for high-speed transmission.

(3) Purpose of the Invention In view of the above points, it is an object of the present invention to provide a data transmission device which transmits signals by phase modulating the signals and achieves high speed and high reliability.

(4) Embodiment of the Invention FIG. 1 is an explanatory diagram of the configuration of a data transmission device according to the invention.

In the figure, 1 is a transmitting circuit, 2 is a receiving circuit, and T is a transformer connecting the transmission line t, the transmitting circuit t, and the receiving circuit 2. The transmitting circuit 1 receives 1, 0 (H
, L) is input, and outputs one period of pulse corresponding to one bit of this data.
A modulation circuit 41 changes the phase of the output pulse signal when K changes, and this modulation circuit 40. A good signal that has been phase modulated becomes a long and short pulse signal, so the peak value is changed according to the length. The driving circuit 5 is configured to have a plurality of driving circuits 5 that output low signals and high signals. 9. The receiving circuit 2 includes a signal detection circuit 6 for detecting the presence or absence of a received data signal. The demodulation circuit 7 demodulates the received data using the detection signal of the signal detection circuit 6 and outputs the original data signal through the output terminal 8. The transmission data is KH (high) as shown in the first half of Figure 2 (B).
As shown in the first half of Figure 2 (b), when the signal is at the same level, the transmission signal form is divided into 1 cycle pulses corresponding to 4C, and is made into a signal with the same waveform as the previous pulse signal. When the transmitted data is at the KL (low) level as shown in the second half of Figure 2 (A), the transmission signal form is as shown in Figure 2 (←)
As shown in the second half of the figure, the phase of the previous pulse signal is 18
It is inverted by 0 degrees and becomes a nine waveform signal.

When transmitting, the data in Figure 2 (0) should be sent to Figure 2 (B).
When receiving the pulse signal, the pulse signal shown in Fig. 2 @) is demodulated into the data shown in Fig. 2 0).

Further, a data transmission signal as shown in ts2 (c) in which H and L level signals are mixed is as shown in FIG. 2). Note that K may be used to invert the phase when the signal is H.

FIG. 3 is a configuration explanatory diagram showing one embodiment of the transmitting circuit. First, the modulation circuit 4 will be explained.

The modulation circuit 4 has a clear terminal CLRK supplied with the transmission data signal from the input terminal 3, and a first flip-flop circuit 41.J- whose terminal is set at H (high) level. and Q1 of this first J-Ky lip flop circuit 41
The output of the terminal J is simultaneously supplied to the terminal J, and the clear terminal is always at zero level by grounding, and the output signal from the terminal Q is taken out. , each flip-flop circuit 41, 4
Each clock terminal CKK is supplied with a clock signal of a predetermined period from the clock terminal 40, and is triggered by the rising edge of the lock signal.

#I4 Explain the operation of the modulation circuit 4 with reference to the diagram 〇Each 7
The lip-flop circuits 41 and 42K are supplied with a lock signal as shown in FIG. 4 (0), and H, L, H, L, L, H data signals as shown in FIG. Suppose that the signal is supplied to the clear terminal of the flip-flop circuit 41. Note that in the J- flip-flop circuit, when the clear terminal is at H level, the Q terminal is always on, the Q terminal is at H, the clear terminal is at L, and J.

When the K terminal is both KH, Q at the rising edge of the clock signal)
, Q terminal outputs are each inverted, and when both are KL, the original state is maintained. (Refer to the following table) When the clock shown in Figure 4 (0) is input, the first J- is a flip-flop, the clear terminal of the pull circuit 41 is supplied with data H, and the Ql terminal output is H. becomes. The same goes for the 9th time when the next "tsuku■" is entered.When the clock is ■, the data is L.

This is supplied to the clear terminal, and the Q1 terminal output is inverted and becomes L. Also at the time of clock ■, since the data is L, it is inverted and the Ql terminal output becomes H. When the clock is ■, the data is H, so the Ql terminal output becomes H. Similarly, an output as shown in FIG. 4 is obtained from the Ql terminal of the first flip-flop circuit 41.

This Ql terminal output is simultaneously supplied to the J terminal of the second flip-flop circuit 42. When the clock is ■, the clear terminal is L and the J and 2 terminals are H, so the +Q2 terminal output is inverted and becomes H. In the case of BLACK or RI, the J and Q2 terminals are at H level, so the output from the tQ2 terminal is inverted and becomes L level. When the clock is ■.

Since the terminal J is still at H, the output from the Q2 terminal is inverted and becomes H. When the clock is ■, the terminal J is still at L, so the output from the Q2 terminal maintains its original state and becomes H. When the clock is ■, the J terminal is still H.

The Q2 terminal output is inverted and becomes L. Similarly, the fourth
An output as shown in ) is obtained from the Q2 terminal of the second flip-flop circuit 42.

The signal shown in Fig. 4 (←) is delayed by one clock in response to the H and L signals shown in Fig. 4 (b), and has the same waveform as the previous signal with respect to the H level. On the other hand, a signal obtained by inverting the previous signal by 180 degrees is used.For the output terminals of the flip-flop circuits 41 and 42 for J-, residual terminals other than those described above can be used as necessary.

Next, the drive circuit 5 will be explained.

Referring again to FIG. 3, the drive circuit 5 performs two-phase modulation as shown in FIG. A long/short pulse detection circuit 51 that looks like a signal and detects its length. and a first driver 52 driven by the long/short pulse detection signal of the long/short pulse detection circuit 51. second driver 5
3. It is structured. The first driver 52 receives the transmission data from the modulation circuit 4 and the long/short pulse detection circuit 5
In response to the long pulse detection signal #1, a signal with a low peak value Er is output only when the transmitted data is a long signal, and in response to the dry signal #I2, a signal with a high peak value E2 is output.

The width of the long pulse signal is twice the width of the short pulse signal, which is 1, so the peak value E+ should be twice the number 8, and the 5th
The wave height values were different as shown in Figure (a). A signal whose integral value (DC component) for any one cycle is zero is transmitted via the transformer T to the transmission line tK.

Rit6. The integral value from zero point a to zero point C is zero, and the integral value from zero point A to zero point d is also zero,
The integral value of any one period is always zero.

In this way, the transmission 1ijtK has a CR distribution constant, so if a long signal and a smoke signal are transmitted at the same peak value, energy will accumulate on the long signal side, the zero point will be dragged, and the transmission will be unstable. However, if you always set the integral value of any one cycle to zero, no energy accumulation will occur, zero point fluctuation will not occur, and the received waveform will not be violent as shown in Figure 5 ←). This results in fewer correct signals.

FIG. 6 is a configuration explanatory diagram showing one embodiment of the receiving circuit 2. As shown in FIG.

In the figure, the data signal that has transmitted the transmission IIt is
6. Signal detection circuit via transformer T. The signal is supplied to the demodulation circuit 7. The signal detection circuit 6 includes H, as shown in FIG.
A rounding level comparator 61 that detects the presence or absence of H, H, L, H, L, L, H data signals and carriers. This level comparator generates a 2-bit delayed output as shown in Figure 2 (→), and a carrier signal can be extracted from the output terminal 60. A waveform shaping circuit 71 such as a hysteresis comparator that shapes the waveform of a data signal such as 71. An edge detection circuit 72 such as a differentiating circuit that detects the edge of the waveform shaping circuit 71 and generates an edge pulse. A glogram counter 73 that has the function of a monostable multivibrator with a delay that generates a pulse signal of a predetermined width with a predetermined time delay every time the trigger is applied.Program counter 73
A D-type first 7 lip-flop circuit 74. whose output is supplied to the D1 terminal. and a D-type second 7-lip 70-tub circuit 75 to which the output of the D-type first 7-lip 70-tub circuit 74 is supplied to the D2 terminal and the clear terminal CLR2. Note that due to the delay circuit 63.

Edge detection circuit 72. The program counter 73 is delayed by one pit and the first . Second 7-lip 70-g circuit 74
, 75 are aligned with K so that they operate with a delay of 2 bits. Note that the delay circuit 63 may be considered as a separate component from the signal detection circuit 6.

The operation of the receiving circuit 2 will be explained with reference to FIG.

The data shown in FIG. 7 0) is supplied to the edge detection circuit 72 via the waveform shaping circuit 71, and
The carrier detection signal shown in Figure (B) starts operation with a 1-bit delay, and generates an edge pulse whose minimum interval is half a bit of the output data as shown in Figure 7 (C). The first gram counter 73 is loaded, and the first . a second 7-lip 70-tub circuit 74;
It is supplied to the clock terminal CK of 75 to cause the operation to take place.

The output of the program counter 73 is output from the edge detection circuit 72.
(The time t1 that the rising edge pulse of → can rise before the arrival of the first edge pulse is delayed by t1, and the falling edge of the 9th order edge pulse J) is reset from K. Generates a time span signal. Therefore, a pulse signal is generated after a predetermined time t1 delay in the erazino (Rus), and is reset at the falling edge of the next edge pulse 0 within the time tz, and the next pulse signal is generated again at the rising edge of this erazino (Rus). A similar pulse-width signal is generated from the QO terminal.The pulse width signal from the Eraginokurus has a wide interval to the primary Eraginokurus, and it automatically falls. In the same manner, the QO terminal output as shown in FIG.

In the first flip-flop circuit 74, even with a 2-bit delay time, the QO terminal output is H &, so its Q1 terminal output is H. Since the Qo terminal output is L with an edge pulse ■, the Q1 terminal output is high, and the Qo terminal output is high with an edge pulse ■. Because it is H+
Q” terminal output is H, edge pulse ■QO terminal output is H
Therefore, an output such as the Q1m output (in the same way as shown in FIG. 7) is obtained from the Ql terminal of the first flip-flop circuit 74.

It is supplied to the D2 terminal and clear terminal of the second flip-flop circuit 65.

The second flip-flop circuit 75 also starts operating with a 2-bit delay, and at edge pulses ■ and ■, the Q1 terminal output is high.
Therefore, the Q2 terminal output is also H.

At edge pulse ■, the Q1 terminal output is not L, it is cleared and the Q2 terminal output is increased, and at edge pulse ■, the Ql terminal output is I (C rises, but since it was still L, the clear is activated and the Q2 terminal output is increased. In Edge Pulse ■, the Ql terminal output is H table, so the Q2 terminal output is H.

Thereafter, in the same manner, an output as shown in FIG.

This excludes the first two pits of ω in Figure 7, H, L,
The signal is correctly demodulated as H, L, L, etc.

Note that the rectifier circuit 620 of the signal detection circuit 6 is replaced by a K/< pass filter or a PLL (phase-locked loop), and the reception signal paste 61 of the required frequency is omitted.
The outputs of the demodulation circuit 70 and the waveform shaping circuit 71 may be used in common.

@) Summary of the Invention As stated above, the present invention consists of a modulation circuit that phase modulates transmission data, and a waveform that corresponds to the long and short pulse signal, which becomes a long and short pulse signal if you look at the phase modulated signal differently. This data transmission device includes a transmitter circuit including a drive circuit that transmits data with different high values, a signal detection circuit that detects the presence or absence of received data, and a receiver circuit that includes a demodulation circuit.

(6) Effects of the invention Therefore, since the transmission data is transmitted as long and short pulse signals, 1 bit per #) 1 pulse (cycle)
, there is less redundancy, and also.

If you change the way you look at a good signal that is phase modulated, it becomes a long and short pulse signal.Since the wave height values are different and are transmitted according to the long and short pulse signals, there is little distortion in the received waveform, and it is fast and highly reliable. It can be used as a transmission device.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of a transmission device according to the present invention, and FIG. 2 is an explanatory diagram of a transmission signal format. FIG. 3 is a configuration explanatory diagram showing one embodiment of a transmitting circuit. Fig. 4 is a waveform diagram for explaining the operation of the modulation circuit, Fig. 5 is a waveform diagram for explaining the operation of the driving circuit, Fig. 6 is a configuration explanatory diagram showing one embodiment of the receiving circuit, and Fig. 7 is the operation of the receiving circuit. It is a waveform diagram for explanation. 1... Transmission circuit, j... Receiving circuit, 4... Modulation circuit. 5... Drive circuit, 6... Signal detection circuit, 7... Demodulation circuit 41, 42... J-Flip flop circuit, 51... Long/short pulse detection circuit, 52.53...
63... Delay circuit, 71... Waveform shaping circuit, 72... Edge detection circuit, 73... Program counter, 74, 75... Flip-flop circuit Patent applicant Chino Seisakusho Co., Ltd.

Claims (1)

[Claims] 1. In a data transmission device that connects to a transmission line and sends and receives signals, a modulation circuit that phase modulates transmitted data and a signal that is phase modulated and becomes a long and short pulse signal when viewed from a different perspective. and a transmitter circuit including a drive circuit that transmits signals with different peak values. 9. A data transmission device comprising: a signal detection circuit for detecting the presence or absence of received data; and a receiving circuit including a demodulation circuit for demodulating the received data using a detection signal of the signal detection circuit.