JPS587925A - Gate signal display circuit for thyristor - Google Patents

Gate signal display circuit for thyristor

Info

Publication number
JPS587925A
JPS587925A JP10662881A JP10662881A JPS587925A JP S587925 A JPS587925 A JP S587925A JP 10662881 A JP10662881 A JP 10662881A JP 10662881 A JP10662881 A JP 10662881A JP S587925 A JPS587925 A JP S587925A
Authority
JP
Japan
Prior art keywords
gate pulse
thyristor
gate
display circuit
gate signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10662881A
Other languages
Japanese (ja)
Inventor
Fumio Mizohata
文雄 溝畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10662881A priority Critical patent/JPS587925A/en
Publication of JPS587925A publication Critical patent/JPS587925A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region

Landscapes

  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To visually confirm gate pulses directly applied to each thyristor by the naked eyes of an operator to check them by connecting light emitting diodes to the secondary windings of pulse transformers corresponding to respective thyristors which are connected in series or in parallel. CONSTITUTION:A gate pulse signal generated by a gate pulse generating circuit 1 is supplied to the primary winding of each gate pulse transformer 6 and inputted to each thyristor 3 through the secondary winding, turning on each thyristor. A light emitting diode 5 connected to the secondary winding of each gate pulse transformer 6 lights up at the input of the gate pulse signal, so that the existence of a gate pulse signal corresponding to each thyristor can be checked by the naked eyes of an operator.

Description

【発明の詳細な説明】 本発明は、サイリスクに供給さ扛るゲート信号の有無全
目視可能とするサイリスタのゲート信号表示回路に関す
るものである0 従来、この種の回路として第1図に示すものがあった。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate signal display circuit for a thyristor that allows the presence or absence of a gate signal supplied to a thyristor to be visually checked.A conventional circuit of this type is shown in FIG. was there.

図において、(1)はゲートパルス発生回路、(2)は
直列接続された各サイリスタ(8)にそ扛ぞn対応して
設けら扛、谷サイリスタ(8)と上記ゲートパルス発生
回路(1)との間に介在して上記ゲートパルス発生回路
(1)から各サイリスタ(8)に供給さ扛るゲートパル
ス信号全絶縁するゲートパルストランスである。しかし
て、(4)は上記ゲートパルス発生回路(1)の出力端
に接続され、ゲートパルス発生回路(1)から出力が送
出された時に点灯する発光ダイオード金儲えて谷サイリ
スタ(8)に点弧信号が与えら扛ていること全目視可能
とするゲートパルス表示回路である。
In the figure, (1) is a gate pulse generation circuit, (2) is a gate pulse generation circuit (1) provided corresponding to each thyristor (8) connected in series, and a valley thyristor (8) and the gate pulse generation circuit (1). ) is a gate pulse transformer that completely insulates the gate pulse signals supplied from the gate pulse generating circuit (1) to each thyristor (8). (4) is connected to the output terminal of the gate pulse generation circuit (1), and lights up when the output is sent out from the gate pulse generation circuit (1). This is a gate pulse display circuit that allows you to visually see whether the arc signal is being applied or not.

上記第1図構成において、ゲートパルス発生回路(1)
によって発生さtたゲートパルス信号は、各ゲートパル
ストランス(2)の1次巻線に供給す扛絶縁された2次
巻線を弁してサイリスク(8)にそ扛ぞれ入力ざ扛、サ
イリスタ(8)全点弧式せている。しかして、この時ゲ
ートパルス表示回路(4)は、ゲートパルス発生回路(
1)より発生さ扛たゲートパルス信号によって点灯し、
サイリスク(8)に点弧信号が与えら扛ていること全目
視確認ができるようになつている。
In the configuration shown in FIG. 1 above, the gate pulse generation circuit (1)
The gate pulse signal generated by the gate pulse transformer (2) is inputted to the silicon risk (8) by valving the insulated secondary winding that supplies the primary winding of each gate pulse transformer (2). Thyristor (8) is fully ignited. At this time, the gate pulse display circuit (4) is connected to the gate pulse generation circuit (
1) Lights up by a gate pulse signal generated from
It is now possible to fully visually confirm that the ignition signal is not being given to the Cylisk (8).

しかるに、従来のゲートパルス表示回路は以上のように
構成されているので、ゲートパルス発生回路(1)の出
力全目視可能とするものでおって、実際に各サイリスク
(8)に供給されるゲートパルス信号全目視可能とする
ものではなり、シたがって、サイリスク(3)がゲート
パルス発生回路(1)に多数接続されている場合は、各
サイリスク(8)にそれぞれゲートパルス信号が印力1
石れているか否かを確実に目視確認することができなか
った0 本発明は、上記のような従来のものの欠点全除去するた
めに彦ざ扛たもので、各ゲートパルストランスの2次巻
線に、即ち、各サイリスタのゲートに並列に、発光ダイ
オードを接続することにより各サイリスタへのゲート信
号の有無全確実に目視確認することができるサイリスク
のゲートパルス表示回路全提供すること全目的としてい
る。
However, since the conventional gate pulse display circuit is configured as described above, it is possible to visually see the entire output of the gate pulse generation circuit (1), and the gate pulse display circuit actually supplied to each of the gate pulses (8) can be viewed visually. It is not possible to visually see all of the pulse signals. Therefore, if a large number of thyrisks (3) are connected to the gate pulse generation circuit (1), the gate pulse signal will be applied to each thyrisk (8) at an output of 1.
It was not possible to reliably visually confirm whether or not the stones were broken.0 The present invention was developed in order to eliminate all the drawbacks of the conventional ones as described above, and the secondary winding of each gate pulse transformer For the entire purpose of providing Thyrisk's gate pulse display circuit, the presence or absence of the gate signal to each thyristor can be visually confirmed with complete certainty by connecting a light emitting diode to the line, i.e. in parallel to the gate of each thyristor. There is.

以下、本発明の一実施例全第1図と同一部分は同−符号
金附して示す第2図に基いて説明する。
Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2, in which all the same parts as in FIG. 1 are denoted by the same reference numerals.

第2図において、谷サイリスタ(1)にそ扛ぞt対応し
て設けら2″しる本発明のゲートパルストランス(6)
の2次巻線(ICは、谷サイリスクのゲートに並列状態
となる発光ダイオード(5)が設けらflており、ゲー
トパルス発生回路(1)から各ゲートパルストランス(
0)を介してそれぞれ各サイリスク(1)にゲートパル
ス信号が発せら7する時に、そのゲートパルス信号の有
無を谷発光ダイオード(5)vr−よって目視確認がで
きるようになっている。
In FIG. 2, the gate pulse transformer (6) of the present invention is provided 2" corresponding to the valley thyristor (1).
The secondary winding (IC) is provided with a light emitting diode (5) that is in parallel with the gate of the valley sirisk, and each gate pulse transformer (
When a gate pulse signal is emitted to each sirisk (1) via the gate 0), the presence or absence of the gate pulse signal can be visually confirmed by the valley light emitting diode (5) vr-.

即ち、第2図構成において、ゲートパルス発生回路(1
)によって発生さ扛だゲートパルス信号は、各ゲートパ
ルストランス(2)の1次巻線に供給ざ扛絶縁式扛fC
2次巻線?介して谷サイリスタ(8)にそれぞれ入力4
tt、こルによって各サイリスタ(1)を点弧させるが
、この時、ゲートパルストランス(6)の2次巻線に接
続てれた発光ダイオード(5)は、ゲートパルス信号が
印力11さ扛ると魚釣し、目視により1%−+)−4!
J −xz(t−)KN”5 L fc ’J = )
 ′: iv 、x @ g   、の有無を確認でき
るようになっている。
That is, in the configuration of FIG. 2, the gate pulse generation circuit (1
) is supplied to the primary winding of each gate pulse transformer (2) by an insulated transformer fC.
Secondary winding? Input 4 to the valley thyristor (8) through
At this time, the light emitting diode (5) connected to the secondary winding of the gate pulse transformer (6) receives the gate pulse signal from the input power 11. When it is caught, it is 1%-+)-4 by visual inspection!
J -xz(t-)KN"5 L fc 'J = )
′: The presence or absence of iv and x @ g can be confirmed.

以上のように本発明によれは、谷サイリスクに対応する
パルストランスの2次巻線に兄元夕゛イオ一ド(t−設
けたことにより、直接各すイリスメに与えらγLるゲー
トパルスを確実に目視確認することができるという効果
を奏する。
As described above, according to the present invention, by providing the secondary winding of the pulse transformer corresponding to the valley current, the gate pulse γL is directly applied to each iris. This has the effect of allowing reliable visual confirmation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のサイリスタのゲート信号表示回路を示す
回路図、第2図は本発明の一実施例によるサイリスタの
ゲート信号表示回路を示す回路図である。 (1〕・・φゲートパルス発生回路 (、−4) 、 (6)−・・ゲートパルストランス(
8)・争・サイリスク (5)争・@う6光ダイオード なお図中、同一符号は同一、又は相当部分を示す。 代理人 葛 野 信 − 5− 第 1 図 第2図 手イ1ダC補正書(自発) 昭和 571七 〇11241.1 2、発明の81′Th、 サイリスタのゲート信号表示し1路 31由Iにを4−るh 名 弥((iol )   :、菱電機株式会社代表り
片+I+仁八部 へ、代理人 5補正の対象 明細書の発明の詳細な説明の欄。 6補正の内容 明細書第4頁第5行、第13行及び第17行の各1−各
サイリスタ(1)」という記載をそれぞれ「各サイリス
タ(3)」と補正する。 榎上 2−
FIG. 1 is a circuit diagram showing a conventional thyristor gate signal display circuit, and FIG. 2 is a circuit diagram showing a thyristor gate signal display circuit according to an embodiment of the present invention. (1)...φ gate pulse generation circuit (,-4), (6)-...gate pulse transformer (
8)・Conflict・Sirisk (5)Conflict・@U6 Photodiode In the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - 5- 1 Figure 2 Hand A 1 Da C Amendment (Spontaneous) Showa 5717 011241.1 2. Invention 81'Th, Thyristor gate signal display 1 way 31 way I Niwo 4-ruh Name Ya ((iol):, Ryodenki Co., Ltd. representative + I + Jin 8 part, Column for detailed explanation of the invention in the specification subject to amendment 5 by agent. 6 Description of contents of amendment The description "each 1 - each thyristor (1)" in the 5th, 13th, and 17th lines of page 4 is corrected to "each thyristor (3)." Enoue 2-

Claims (1)

【特許請求の範囲】[Claims] 直列または並列接続さnる各サイリスタにそ扛ぞn対応
して設けら扛て、ゲートパルス発生回路からのゲート信
号全上記各サイリスタにそれぞれ供給するゲートパルス
トランスを備えたゲートパルス供給回路における上記ゲ
ート信号の有無を表示するようにしたサイリスクのゲー
ト信号表示回路において、上記各ゲートパルストランス
の2次SM側に、各サイリスタのゲートと並列状態で発
光ダイオード全接続したこと全特徴とするサイリスタの
ゲート信号表示回路。
The above-mentioned gate pulse supply circuit includes a gate pulse transformer which is provided correspondingly to each thyristor connected in series or parallel and supplies a gate signal from the gate pulse generation circuit to each of the above-mentioned thyristors. The thyristor's gate signal display circuit, which displays the presence or absence of a gate signal, is characterized in that all light emitting diodes are connected to the secondary SM side of each gate pulse transformer in parallel with the gate of each thyristor. Gate signal display circuit.
JP10662881A 1981-07-07 1981-07-07 Gate signal display circuit for thyristor Pending JPS587925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10662881A JPS587925A (en) 1981-07-07 1981-07-07 Gate signal display circuit for thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10662881A JPS587925A (en) 1981-07-07 1981-07-07 Gate signal display circuit for thyristor

Publications (1)

Publication Number Publication Date
JPS587925A true JPS587925A (en) 1983-01-17

Family

ID=14438370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10662881A Pending JPS587925A (en) 1981-07-07 1981-07-07 Gate signal display circuit for thyristor

Country Status (1)

Country Link
JP (1) JPS587925A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007336618A (en) * 2006-06-12 2007-12-27 Pre-Tech Co Ltd High-power circuit for high frequency
US9541137B2 (en) 2012-09-24 2017-01-10 Ntn Corporation Cooling structure for bearing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007336618A (en) * 2006-06-12 2007-12-27 Pre-Tech Co Ltd High-power circuit for high frequency
US9541137B2 (en) 2012-09-24 2017-01-10 Ntn Corporation Cooling structure for bearing device
US10280980B2 (en) 2012-09-24 2019-05-07 Ntn Corporation Cooling structure for bearing device

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