JPS587885A - Manufacture of semiconductor photodetector - Google Patents

Manufacture of semiconductor photodetector

Info

Publication number
JPS587885A
JPS587885A JP56105834A JP10583481A JPS587885A JP S587885 A JPS587885 A JP S587885A JP 56105834 A JP56105834 A JP 56105834A JP 10583481 A JP10583481 A JP 10583481A JP S587885 A JPS587885 A JP S587885A
Authority
JP
Japan
Prior art keywords
layer
type
guard ring
compound semiconductor
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56105834A
Other languages
Japanese (ja)
Inventor
Kazuto Yasuda
和人 安田
Haruo Kawada
春雄 川田
Yasuo Baba
馬場 靖男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56105834A priority Critical patent/JPS587885A/en
Publication of JPS587885A publication Critical patent/JPS587885A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H01L31/1075Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To improve the withstand voltage of a guard ring by using Be as a p type impurity when a photodetector and the p-n junction of the guard ring are formed, and deeply injecting Be ions by an ion injection method. CONSTITUTION:An n<-> type light absorptive layer 2 made of four-element compound semiconductor, an n<-> type guard ring forming layer 3 made of compound semiconductor and an n type multiplication layer 4 made of compound semiconductor are sequentially formed on a semiconductor substrate 1. Subsequently, the layer 4 is etched in mesa shape, beryllium is then injected, thereby forming a p-n junction in the layers 4 and 3.

Description

【発明の詳細な説明】 本発明は、ガード・リングを有する半導体受光装置を製
造する方法の改jLK関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modified method for manufacturing a semiconductor light receiving device having a guard ring.

従来、この種の半導体受光装置として第1図に見られる
ものが知られている。
Conventionally, the one shown in FIG. 1 has been known as this type of semiconductor light receiving device.

図に於いて、1は%+型I%P基板、2はC型1mにm
JIzP光吸収層、3は外−型1sPガード・リング形
成層、4は%WI%P倍増層、5はp型不純物領域、A
は受光部、Gはガード・リング部をそれぞれ示している
。伺、主な層の不純物濃度を例示すると、 光吸収層2 : 8 X (O” (cm−畠〕ガード
・リング形成層3 : 8X 10” l:c+m−’
)増倍層4 :’ 2 X 10” (e+m−’)で
ある。
In the figure, 1 is a %+ type I%P substrate, 2 is a C type 1 m
JIzP light absorption layer, 3 is an outer-type 1sP guard ring forming layer, 4 is a %WI%P doubling layer, 5 is a p-type impurity region, A
1 indicates a light receiving section, and G indicates a guard ring section. To give an example of the impurity concentration of the main layers, light absorption layer 2: 8X (O" (cm-Hatake) Guard ring forming layer 3: 8X 10"l:c+m-'
) Multiplier layer 4: ' 2 X 10''(e+m-').

ところで、図示の装置を製造するには、基板1に連続液
相エピタキシャル成長法を適用して光吸収層2、ガード
・リング形成層3、増倍層4を成長させ、次いで、増倍
層4をメサ・エツチングして図示の如き形状となし、次
いで、例えばカドオウム(cd)を気相拡散してpm不
純物領域5を形成するようKしている。即ち、Cdの拡
散に依シ増倍層4に増倍作用をするp−n 8合を形成
するとともにガード・リング形成層3に於いてはキャリ
ヤ密度を減少させガード・リング部Gの耐圧を向上させ
るようにしている。
By the way, in order to manufacture the illustrated device, a continuous liquid phase epitaxial growth method is applied to a substrate 1 to grow a light absorption layer 2, a guard ring forming layer 3, and a multiplication layer 4, and then the multiplication layer 4 is grown. Mesa etching is performed to form the shape as shown in the figure, and then, for example, cadmium (CD) is vapor phase diffused to form a PM impurity region 5. That is, depending on the diffusion of Cd, a pn 8 coupling is formed which has a multiplication effect on the multiplication layer 4, and at the same time, the carrier density is reduced in the guard ring forming layer 3, and the withstand voltage of the guard ring portion G is increased. I'm trying to improve it.

しかしながら、この従来技術では、ガード・リング部G
K於けるキャリヤ密度を8 X 10” 〔ox−”)
以下にすることは困難であシ、ガード・リング部Gの耐
圧向上に限界がおった。
However, in this prior art, the guard ring portion G
The carrier density at K is 8 x 10” [ox-”]
It was difficult to do the following, and there was a limit to the improvement in pressure resistance of the guard ring portion G.

本発明は、増倍層にp−n接合を形成するとともにガー
ド・リング部に於けるキャリヤ密度を低下させる為のp
TIl不純物の種類を適切に選択し、且つ、それをイオ
ン注入法を適用して打ち込むことに依シガー)°・リン
グ部の耐圧を大幅に向上させようとするものであυ、以
下これを詳細に説明する。
The present invention provides a p-n junction in the multiplication layer and a p-n junction for reducing the carrier density in the guard ring part.
The aim is to significantly improve the withstand voltage of the ring part by appropriately selecting the type of TIl impurity and implanting it using the ion implantation method.This will be explained in detail below. Explain.

本発明に依って得られる装置の構造は第1図に示したも
のと同じであるが、増倍層4にp−n接合を形成し、′
tた、ガード・リンク部Gにp−n接合を形成する為の
p型不純物としてベリリウム(B#)を使用する。
The structure of the device obtained according to the invention is the same as that shown in FIG. 1, except that a pn junction is formed in the multiplication layer 4, and
Additionally, beryllium (B#) is used as a p-type impurity to form a p-n junction in the guard link portion G.

即ち、第1図について説明した工程を経て図示の形状と
なし、次いで、B#+を加速エネルギ140(fgF)
、ドーズ量I X 10” (es−”:lとして注入
し、次いで、窒素雰囲気中にて温度750 (℃)で時
間20ω〕の熱処理を行なう。これに依シ、第1図に見
られるよりなp+型層が形成される。
That is, the shape shown in the figure is formed through the process explained in connection with FIG.
, at a dose of I.times. A p+ type layer is formed.

このp型層の存在で、p−n接合近傍のキャリヤ密度は
B#の補償効果に依って第28図(ロ)、(6) K見
られるような分布となるもの′cある。
Due to the presence of this p-type layer, the carrier density near the p-n junction has a distribution as shown in FIGS. 28(b) and (6) K due to the compensation effect of B#.

第2図(ロ)は受光部Aに於ける分布を表わす線図、第
2図(6)はガード・リング部Gに於ける分布を表わす
線図をそれぞれ示している。
FIG. 2(B) shows a diagram showing the distribution in the light receiving part A, and FIG. 2(6) shows a diagram showing the distribution in the guard ring part G.

いずれの図に於いても、実線はB−注入後のホール密度
、1点鎖線は同じ(Ih+注入後の電子密度、破線はB
−“注入前の電子密度をそれぞれ示すものである。
In both figures, the solid line is the hole density after B- injection, the dashed line is the same (electron density after Ih+ injection, and the broken line is B
−“Indicates the electron density before injection.

このように、B−イオンを注入してガード・リング形成
層3にp+型層を形成することに依シ、その下側の1型
層に於けるキャリヤ密度は減少し、ガード・リング部G
としての耐圧は大になる。
In this way, by implanting B- ions to form a p+ type layer in the guard ring forming layer 3, the carrier density in the type 1 layer below it decreases, and the guard ring portion G
As a result, the pressure resistance increases.

第6図はB#+を注入して形成したr型層のキャリヤ密
度と表面からの距離との関係を表わす線図でおる。
FIG. 6 is a diagram showing the relationship between carrier density and distance from the surface of an r-type layer formed by implanting B#+.

このデータを得た条件は次の通シである。The conditions for obtaining this data are as follows.

イオン注入対象:n−型1mP基板R=4X10”(a
m−り注入イオン:B#+ ドーズ量: I X 10” Ce講4〕アニール時間
:20〔分〕 雰囲気二Nl 活性化率: 60 (−) アニール温度750 (C)にテ%z : s、ox 
10” [:am−”)アニール温度700 (C) 
Kて%# : S’、2 X 10” (am−”)ア
ニール温度650 CC)にて外JF : 9.6X 
10” 〔ex−”〕同、%Iは表面濃度、Xjは接合
深さ である。
Ion implantation target: n-type 1mP substrate R = 4X10" (a
Re-implanted ion: B#+ Dose: I x 10" Ce course 4] Annealing time: 20 [minutes] Atmosphere 2Nl Activation rate: 60 (-) Annealing temperature 750 (C) %z: s , ox
10” [:am-”) Annealing temperature 700 (C)
K%#: S', 2 x 10"(am-") annealing temperature 650 CC) outside JF: 9.6X
10"[ex-"] Same, %I is the surface concentration and Xj is the junction depth.

以上の説明で判るように、本発明に依れば、半導体受光
装置に於けゐ受光部及びガード・リング部のp−n接合
を形成するに際し、pHi不純物としてB−を使用し、
イオン注入法にて深く打ち込むことに依シ、従来技術で
形成したガード・リング形成層に於けるキャリヤ密度を
更に減少させることができるから、ガード・リング部の
耐圧を向上することができる。
As can be seen from the above description, according to the present invention, B- is used as a pHi impurity when forming a p-n junction in a light receiving part and a guard ring part in a semiconductor light receiving device.
By deeply implanting ions using the ion implantation method, the carrier density in the guard ring forming layer formed by the conventional technique can be further reduced, so that the withstand voltage of the guard ring portion can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体受光装置の要部説明図、第2図はキャリ
ヤ分布を表わす線図、第3図はIn基板のp+型層に於
けるキャリヤ分布を表りす線図である。 図に於いて、1は基板、2は光吸収珊、3はガード・リ
ング形成層、4は増倍層である。 特許出願人 富士通株式会社
FIG. 1 is an explanatory diagram of the main part of a semiconductor light receiving device, FIG. 2 is a diagram showing carrier distribution, and FIG. 3 is a diagram showing carrier distribution in the p+ type layer of an In substrate. In the figure, 1 is a substrate, 2 is a light absorbing coral, 3 is a guard ring forming layer, and 4 is a multiplication layer. Patent applicant Fujitsu Limited

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に四元化合物半導体からなるn−型光吸収
層及び化合−半導体からなる外−型ガード・リング形成
層及び化合物半導体からなる謡型増倍層を順次形成し、
次いで、前記%型増倍層をメサ状にエツチングしてから
ベリリウムを導入して前記5ill増倍層及び前記%−
型ガード・リング形成層内K p−s接合を形成する工
程を含んでなることを特徴とする半導体受光装置の製造
方法。
sequentially forming on a semiconductor substrate an n-type light absorption layer made of a quaternary compound semiconductor, an outer-type guard ring forming layer made of a compound semiconductor, and a song-type multiplication layer made of a compound semiconductor;
Next, the %-type multiplication layer is etched into a mesa shape, and beryllium is introduced to form the 5ill multiplication layer and the %-type multiplication layer.
1. A method of manufacturing a semiconductor light receiving device, comprising the step of forming a K ps junction in a mold guard ring forming layer.
JP56105834A 1981-07-06 1981-07-06 Manufacture of semiconductor photodetector Pending JPS587885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56105834A JPS587885A (en) 1981-07-06 1981-07-06 Manufacture of semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56105834A JPS587885A (en) 1981-07-06 1981-07-06 Manufacture of semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPS587885A true JPS587885A (en) 1983-01-17

Family

ID=14418064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56105834A Pending JPS587885A (en) 1981-07-06 1981-07-06 Manufacture of semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPS587885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810511U (en) * 1981-07-13 1983-01-24 シルバ−工業株式会社 Wick for combustion appliances

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810511U (en) * 1981-07-13 1983-01-24 シルバ−工業株式会社 Wick for combustion appliances
JPS5913448Y2 (en) * 1981-07-13 1984-04-21 シルバ−工業株式会社 Wick for combustion appliances

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