JPS587884A - Flip-chip type semiconductor device - Google Patents

Flip-chip type semiconductor device

Info

Publication number
JPS587884A
JPS587884A JP10602081A JP10602081A JPS587884A JP S587884 A JPS587884 A JP S587884A JP 10602081 A JP10602081 A JP 10602081A JP 10602081 A JP10602081 A JP 10602081A JP S587884 A JPS587884 A JP S587884A
Authority
JP
Japan
Prior art keywords
electrode
package
chip type
semiconductor device
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10602081A
Other languages
Japanese (ja)
Inventor
Michihiro Kobiki
小引　通博
Manabu Watase
渡瀬　学
Takeshi Suzuki
武 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10602081A priority Critical patent/JPS587884A/en
Publication of JPS587884A publication Critical patent/JPS587884A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve the reliability of a semiconductor device by reducing the adhering area of an electrode adhered to a conductor piece on an insulating member of a package. CONSTITUTION:A semiconductor element dies 9 formed on one main surface side is formed with electrodes 6, 7 confronted with the surface of a package at the main surface side on a package 13 having an insulating member on the surface formed with a main body of metal. The electrodes are bonded to be electrically connected to conductor pieces 15a, 17a respectively formed on the metal or the insulating members 14, 16 on the surface of the package. The adhering areas of the electrodes 15a, 17a bonded to the pieces can be reduced.

Description

【発明の詳細な説明】 この発明はフリップチップ形半導体素子ダイスをパッケ
ージに接着して構成する半導体装置のパッケージの構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a package for a semiconductor device constructed by bonding a flip-chip type semiconductor element die to the package.

以下ヒ化ガリクムを用いた横形ショットキパリアゲート
形電界効果トランジスタ（ＧａＡｓ　ＦＥＴと略称する
。）を例にとって説明する。A description will be given below of an example of a lateral Schottky parry gate field effect transistor (abbreviated as GaAs FET) using gallium arsenide.

第１図および第２図は７リツブチツプ形ＧａＡｓＦＥＴ
ダイスの一般的な構成を示し第１図はその平面図、第２
図は第１図におけるＩｆ−Ｉｆ線での断面図である。図
において、＋１１は半絶縁性Ｇ１Ａｓ基板、（２）はこ
の基板（！）上に選択的に形成された能動層、（３）お
よび（４）はそれぞれこの能動層（２）上にこれとオー
ム接触するように形成されたソース電極およびドレイン
電極、（−）はソース電極（３）とドレイン電極（４）
との間の能動層（２）上にこれとショットキー接触を有
するように形成されたゲート電極で、そのボンダイング
パッド部（５ａ）は前記基板（１）上にある。Figures 1 and 2 are 7-ribbon-chip GaAsFETs.
The general structure of the die is shown; Fig. 1 is a plan view thereof, Fig. 2 is a plan view of the die;
The figure is a sectional view taken along the If-If line in FIG. 1. In the figure, +11 is a semi-insulating G1As substrate, (2) is an active layer selectively formed on this substrate (!), and (3) and (4) are respectively on this active layer (2). Source and drain electrodes formed in ohmic contact, (-) indicates source electrode (3) and drain electrode (4)
A gate electrode is formed on the active layer (2) between and having a Schottky contact therewith, and its bonding pad portion (5a) is on said substrate (1).

ｔｅｌ　、　＋７１および（８）はそれぞれソース電極
（３）の上、ドレイン電極（４）の上およびゲート電極
（６）のポンディングパッド（ＳＳ＋）上に電解メッキ
によって選択的に形成された厚メツキ電極である。この
ようにしてフリップチップ形Ｇ１Ａｓ　ＦＥＴダイス（
３）は構成される。tel, +71, and (8) are thick platings selectively formed by electrolytic plating on the source electrode (3), the drain electrode (4), and the gate electrode (6) bonding pad (SS+), respectively. It is an electrode. In this way, flip chip type G1As FET die (
3) is configured.

そして、とのブリップチップ形ＧａＡｓ　ＦＥＴダイス
（９）は第３図および第４図に示すようにパッケージに
塔載される。第３図はその平面図、第４図は第３図にお
ける■−■線での断面図である。Then, the blip-chip type GaAs FET die (9) is mounted in a package as shown in FIGS. 3 and 4. FIG. 3 is a plan view thereof, and FIG. 4 is a sectional view taken along the line ■--■ in FIG.

第３図および第４図において、前記第１図および第２図
に示したソース厚メツキ電極（６）、ドレイン厚メツキ
電極（７）およびゲート厚メツキ電極（８）を備えたフ
リップチップ形Ｇ１Ａｓ　ＦＥＴダイス（９）の各厚メ
ツキ電極（６１、（７１および（８）上にそれぞれリボ
ン状の付加電極（２）、　Ｑｔ）および（ｌ乃を圧着し
た後、ソース厚メツキ電極（６）上の付加電極（Ｉ０）
はパッケージ＋ＩＪの本体へ、ドレイン厚メツキ電極（
７）上の付加電極（１１）はパッケージ０１のドレイン
側セラミック基板（Ｉ４上のストリップライン０５１へ
、そして、ゲート厚メツキ電極（８）上の付加電極（１
′４はパッケージ−〇ゲート側セラミック基板霞上のス
トリップライン０ηへそれぞれ半田付部を用いて半田付
は−される。In FIGS. 3 and 4, a flip-chip type G1As equipped with the source thick plating electrode (6), the drain thick plating electrode (7), and the gate thick plating electrode (8) shown in FIGS. 1 and 2 is shown. After crimping the ribbon-shaped additional electrodes (2), Qt) and (1) on the thick plated electrodes (61, (71 and (8)) of the FET die (9), place them on the source thick plated electrode (6). Additional electrode (I0)
connect the package + IJ body to the drain thick plated electrode (
7) The additional electrode (11) on the drain side of the package 01 is connected to the strip line 051 on the drain side ceramic substrate (I4), and the additional electrode (11) on the gate thickness plated electrode (8)
'4 is soldered to the strip line 0η on the ceramic substrate on the gate side of the package using the respective soldering parts.

以上のように構成されるクリップチップ形（フエイスダ
クン形）　ＧａＡｓ　ＦＥＴの動作機構については周知
であるからあらためて述べないが、通常のアップサイド
アップ（ｕｐ　５ｉｄｅ　ｕｐ）形（フェイスアップ形
）　ＧａＡｓ　ＦＥＴでは細いリード線をボンディング
しているのに対して、フリップチップ形ＧａＡｓＦＥＴ
ではインダクタンス成分の少ないリボン状付加電極を用
いているため、増幅器に使用された場合には、インダク
タンス成分の減少が増幅利得の向上に直結することから
高利得化に有効な構造である。The operation mechanism of the clip-chip type (face-up type) GaAs FET configured as above is well known, so I will not discuss it again. While the lead wires are bonded, flip-chip GaAsFET
Since this uses a ribbon-shaped additional electrode with a small inductance component, when used in an amplifier, the reduction in the inductance component is directly linked to an improvement in the amplification gain, making it an effective structure for increasing the gain.

しかしながら、このように構成されるクリップチップ形
ＧａＡｓ　ＦＥＴに温度変化を与えた場合、パッケージ
−〇本体（通常、材料として線膨張係数　　　・１．６
５Ｘ１０′ｄｅｇ−”をもつ銅が用いられる。）とドレ
インおよびゲート側のセラミック基板Ｏｎおよび幀。However, when a temperature change is applied to a clip-chip GaAs FET configured in this way, the package body (typically, the material has a linear expansion coefficient of 1.6
5 x 10'deg-" is used) and the ceramic substrates On and On on the drain and gate sides.

によるストレスが７リツプチツプ形ＧａＡｓ　ＦＥＴダ
イス（９）に加わる。例えば、第４図中に一点鎖線矢印
で示したように、ドレインおよびゲート側のセラミック
基板０４およびａ四の伸縮に比して、パッケージ崗の本
体はその２．５倍も伸縮し、高温時にはパッケージ０！
ＩＯ本体は７リツプチツプ形ＧａＡｓ　ＦＥＴダイス（
９）を持ち上げるように働き、低温時には、パッケージ
０１０本体はフリップチップ形ＧａＡｓＦＥＴダイス（
９）を引っばり下げるように働く。このように、温度変
化によるパッケージ０３）の伸縮が７リツプチツプ形Ｇ
ＲＡＩＬ　ＦＥＴダイス（９）にストレスを加えるため
、信頼性に対する懸念があった。stress is applied to the 7-lipped GaAs FET die (9). For example, as shown by the dashed-dotted line arrow in Figure 4, compared to the expansion and contraction of the ceramic substrates 04 and A4 on the drain and gate sides, the main body of the package expands and contracts 2.5 times as much, and at high temperatures. Package 0!
The IO body is a 7-lip chip GaAs FET die (
9), and when the temperature is low, the package 010 body lifts the flip-chip type GaAsFET die (
9) Works to pull down. In this way, the expansion and contraction of package 03) due to temperature changes
There were concerns about reliability because it added stress to the RAIL FET die (9).

この発明は以上のような点に鑑みてなされたもので、７
リングチップ形半導体装置において、パッケージの絶縁
板部分上に形成されその上に半導体素子ダイスの電極を
ろう付けすべきストリップツイン導体の面積を小さくし
て当該電極のパッケージへの接着面積を小さくすること
によって、ノ（ツケージの各部位における伸縮の差異に
もとづくＦＥＴダイスに対するストレスを緩和し信頼性
にすぐれたクリップチップ形半導体装置を提供すること
を目的としている。This invention was made in view of the above points.
In a ring chip type semiconductor device, to reduce the area of a strip twin conductor formed on an insulating plate portion of a package and onto which an electrode of a semiconductor element die is to be brazed, thereby reducing the bonding area of the electrode to the package. It is an object of the present invention to provide a clip-chip type semiconductor device with excellent reliability by alleviating stress on an FET die due to differences in expansion and contraction in various parts of a cage.

第５図および第６図はこの発明の一実施例になる７リツ
グチツプ形ＧａＡｓ　ＦＥＴの構成を示し、第５図はそ
の平面図、第６図は第５図における■−■線での断面図
である。なお、第５図および第６図において第１図〜第
４図と同一符号は同一もしくは相当部分を示す。5 and 6 show the structure of a 7-chip GaAs FET which is an embodiment of the present invention, FIG. 5 is a plan view thereof, and FIG. 6 is a sectional view taken along the line ■-■ in FIG. 5. It is. Note that in FIGS. 5 and 6, the same reference numerals as in FIGS. 1 to 4 indicate the same or corresponding parts.

第５図および芦６図において、前記第１図および第２図
に示したソース厚メツキ電極（６）、ドレイン厚メツキ
電極（７）およびゲート厚メツキ電極（８）を備えた７
リツプチツプ形ＧａＡｓ　ＦＥＴダイス（９）の各厚メ
ツキ電極＋６１　（７）および（８）上にそれぞれリボ
ン状の付加電極１ｏ）　（１１）およびα匂を圧着した
後、まずソース厚メツキ電極（６）上の付加電極（１＠
はパッケージ（Ｉ：１０本体へ半田付けされる。同時に
パッケージｔＪ３のドレイン側セラミック基板Ｈ上で従
来よりも面積を縮少したストリップライン５およびゲー
ト側セラミック基板α呻上で従来よりも面積を縮少した
ａｖ 極（川およびゲート側付加電極Ｏ匂を半田材端により半
田付けすることによ多構成される。In Fig. 5 and Fig. 6, a 7.5mm electrode 7 comprising the source thick plating electrode (6), the drain thick plating electrode (7) and the gate thick plating electrode (8) shown in Figs. 1 and 2 above is shown.
After pressing the ribbon-shaped additional electrodes 1o) (11) and α on each of the thick plated electrodes +61 (7) and (8) of the lip-chip type GaAs FET die (9), first the source thick plated electrode (6) Upper additional electrode (1@
is soldered to the main body of the package (I:10).At the same time, the strip line 5 is soldered to the drain side ceramic substrate H of package tJ3, which has a smaller area than before, and the gate side ceramic substrate α has a smaller area than before. It is constructed by soldering a small AV pole and an additional electrode on the gate side with the end of the solder material.

この実施例では、ドレインおよびゲート付加電ッグージ
α場の伸縮を付加電極（１１）および０２で吸収し得る
構造となシ、ダイスに加わるストレスを低減でき信頼性
にすぐれたクリップチップ形トランジスタ装置を得るこ
とが出来る。In this example, the structure is such that the expansion and contraction of the drain and gate added electric charge α field can be absorbed by the additional electrodes (11) and 02, and a clip chip type transistor device with excellent reliability that can reduce the stress applied to the die is created. You can get it.

なお前記実施例ではブリップチップ形ＧａＡｓ　ＦＥＴ
について述べたが、本発明はこれに限定されるものでは
なく、フリップチップ形横型トランジスタをはじめ全て
の７リツプチツプ形半導体装置に適用し得る。また、本
発明による付加電極とスリップラインとの接着方法に関
しても、半田付けに限定されるものではなく、例えば熱
圧着法でもよい。In the above embodiment, a blip-chip type GaAs FET is used.
However, the present invention is not limited thereto, and can be applied to all 7-lip chip type semiconductor devices including flip chip type lateral transistors. Further, the method of adhering the additional electrode and the slip line according to the present invention is not limited to soldering, but may also be, for example, thermocompression bonding.

以上、詳述したように、この発明になるプリップチップ
形半導体装置では半導体素子ダイスの各電極のうちパッ
ケージの絶縁部材部上の導体片に接着される電極の接着
面積を小さくシたので、パッケージの金蝿都に接着され
る電極との間で、温度変化にもとづくパッケージの不均
一伸縮のために受けるストレスを吸収することができ、
信頼性を高くすることができる。As detailed above, in the prep-chip semiconductor device according to the present invention, the bonding area of the electrode bonded to the conductor piece on the insulating member of the package is reduced among the electrodes of the semiconductor element die. It is possible to absorb the stress caused by uneven expansion and contraction of the package due to temperature changes between the electrode and the electrode bonded to the metal fly.
Reliability can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はフリップチップ形ＦＥＴダイスの一般的な構成
を示す平面図、第２図は第１図の■−■線での断面図、
第３図は７リツプチツプ形ＦＥＴを従来のパッケージに
装着した状態を示す平面図、第４図は第３図のＩＶ−Ｉ
Ｖ線での断面図、第５図はこの発明の一実施例を示す平
面図、第６図は第５図の■−■線での断面図である。 図において、ｔｅｌ　＋　Ｉ’ｔ）、　（ｓｌは電極、
（９）は７リツグチツプ形ＧａＡｓ　ＦＥＴダイス（半
導体素子ダイス）、００１　、　（川、　Ｑ＠は附加電
極、端はパッケージ本体（金属部）　、　（１、Ｈはセ
フミック基板（絶縁部材部）、（１５ａ）　ｔ　（１７
ｍ）はストリップライン（導体片）　、（Ｉｋ）は半田
材である。 なお、図中同一符号は同一または相肖部分を示す。 代理人葛野信−（外１名） 第１図 第２図 第５図 ９ 第６図 手続補正書（自発） 特許庁長官殿 １、事件の表示　　　　特願昭５６−１０６０１ａｏ号
２、発明の名称　　　　クリップチップ形半導体装置３
、補正をする者 （１） ５、　補正の対象 明細書の発明の詳細な説明の欄 ６、　補正の内容 明細書の第５頁第１３行、第６頁第１行、第７頁第９行
及び第８頁第５行に「信頼性」とあるのをいずれも「信
頼性」と訂正する。 以上 ４４９−Fig. 1 is a plan view showing the general configuration of a flip-chip FET die, Fig. 2 is a sectional view taken along the line ■-■ in Fig. 1,
Figure 3 is a plan view showing a 7-lip chip FET mounted in a conventional package, and Figure 4 is IV-I in Figure 3.
5 is a plan view showing an embodiment of the present invention, and FIG. 6 is a sectional view taken along the line ■--■ in FIG. 5. In the figure, tel + I't), (sl is the electrode,
(9) is a 7-chip type GaAs FET die (semiconductor element die), 001, (river, Q@ is an additional electrode, the end is the package body (metal part), (1, H is a cefmic substrate (insulating member part), ( 15a) t (17
m) is a strip line (conductor piece), and (Ik) is a solder material. Note that the same reference numerals in the figures indicate the same or similar parts. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 5 Figure 9 Figure 6 Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Indication of the case Patent application No. 10601AO No. 1988 2, Title of the invention Clip chip type semiconductor device 3
, Person making the amendment (1) 5. Column 6 for detailed explanation of the invention in the specification to be amended, page 5, line 13, page 6, line 1, page 7, line 9 of the description of the contents of the amendment. In both lines and page 8, line 5, the words ``reliability'' will be corrected to ``reliability.'' Above 449-

Claims (1)

【特許請求の範囲】 ｉｌｌ　　各電極が一方の主面側に形成された半導体素
子ダイスを、金員で主体部が構成され表面に絶縁部材部
を有するパッケージ上に、上記主面側を上記パッケージ
の上記表面に対向させて載置し、上記各電極を上記パッ
ケージの上記表面の金属部、または上記絶縁部材部上に
形成された導体片にそれぞれ電気的に接続するように接
着してなるものにおいて、上記導体片とこれに接着する
電極との接着面積を小さくしたことを特徴とする７リツ
プチツプ形半導体装置。 （＝）導体片と接着する電極の上記接着の部位を当該電
極の端部になるようにしたことを特徴とする特許請求の
範囲第１項記載の７リツプチツプ形半導体装置。 （８）導体片と接着する電極は当該電極から側方に延び
る附加電極を備え、上記接着の部位は上記附加電極の先
端部にあることを特徴とする特許請求の範囲第２項記載
の７リツプチツプ形半導体装置。[Scope of Claims] ill A semiconductor element die in which each electrode is formed on one main surface side is placed on a package whose main body is made of metal and has an insulating member on the surface, and the main surface side is placed on the package. The package is placed facing the surface of the package, and each of the electrodes is bonded to be electrically connected to a metal part of the surface of the package or a conductor piece formed on the insulating member part. 7. A 7-lipped chip type semiconductor device, characterized in that the bonding area between the conductor piece and the electrode bonded thereto is reduced. (=) 7-lip chip type semiconductor device according to claim 1, characterized in that the adhesive portion of the electrode to be adhered to the conductor piece is an end portion of the electrode. (8) The electrode to be bonded to the conductor piece is provided with an additional electrode extending laterally from the electrode, and the adhesive portion is located at the tip of the additional electrode. Lip chip type semiconductor device.
JP10602081A 1981-07-06 1981-07-06 Flip-chip type semiconductor device Pending JPS587884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10602081A JPS587884A (en) 1981-07-06 1981-07-06 Flip-chip type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10602081A JPS587884A (en) 1981-07-06 1981-07-06 Flip-chip type semiconductor device

Publications (1)

Publication Number Publication Date
JPS587884A true JPS587884A (en) 1983-01-17

Family

ID=14422964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10602081A Pending JPS587884A (en) 1981-07-06 1981-07-06 Flip-chip type semiconductor device

Country Status (1)

Country Link
JP (1) JPS587884A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61173016A (en) * 1985-01-25 1986-08-04 ドウマツク・オツフエネ・ハンデルスゲゼルシヤフト・ドクトル・テヒニツシエ・ルードヴイツヒ・カルーツア・ウント・コンパニー Combustion apparatus for fluid combustible medium and nozzle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61173016A (en) * 1985-01-25 1986-08-04 ドウマツク・オツフエネ・ハンデルスゲゼルシヤフト・ドクトル・テヒニツシエ・ルードヴイツヒ・カルーツア・ウント・コンパニー Combustion apparatus for fluid combustible medium and nozzle
JPH0463286B2 (en) * 1985-01-25 1992-10-09 Domatsuku Ohg Dokutoru Tehinitsushe Ruudoitsuhi Karuutsua Unto Co

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