JPS5878450A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of integration by effectively utilizing excessive region sections formed at both ends of an element region row and reducing the width of a region between said row and an adjacent element region row only by a section corresponding to the excessive regions. CONSTITUTION:Wiring regions 22 with wiring 21, such a power supply wiring, ground wiring, etc., which have the first directional length required, are arranged so that a plurality of the element region rows 4 have the first mutually equal directional length among necessary adjacent element regions 3 in at least plural regions 3 in element region rows 4 required in a plurality of the element region rows 4. According to such constitution, the width of the regions 20 among the adjacent element regions 4 can remarkably be made smaller than the case of no formation of the wiring regions 22 when the positions of the wiring regions 22 are properly selected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a configuration in which a plurality of element region rows each having a plurality of element regions arranged in a direction 1 are arranged in a direction 1El perpendicular to the first direction. This invention relates to improvements in semiconductor integrated circuit devices.

As such a semiconductor integrated circuit device, a first@#cf (a plurality of plotters 2 are arranged on a semiconductor substrate 1, and each plotter 2 has a plurality of element regions as shown in FIG. 5 is arranged in the direction of 1 (horizontal direction in the figure).
A plurality of face region rows 4 are arranged in the second direction perpendicular to the direction of the first direction.
It has a configuration in which the power supply wiring 5 and the ground wiring 6 of the element region row 4 are arranged in the direction of @a
The input/output ends 9 of the plurality of element regions 5 of the negative element region row 4 are connected to a wiring 10 extending in the second direction, and these wirings 10 are connected to the wiring 4110 through an insulating layer. The element region array 4 is connected to the arrangement 11A1 extending in the direction of fsl on a different surface via the contact nail 12, and the element region array 4 of -
The input/output terminal 9 of the - element region 5! c The input/output terminal of the - element area S of the connecting arrangement @11 and the other element area array 4! A wiring 11 connected to the wirings 10 and 11 is connected via a contact hole IS' extending in a second direction on a different surface through an insulating layer from the wirings 10 and 11, and is further connected to a plurality of blocks. The arrangement allows the input/output end 14 of No. 2 to extend in the direction of lEl! 115, and the wiring 15 is different from the arrangement 11% through the supply layer. 4914 has the same improvement as m15.
Tsuntatatoho J/1 with wiring tS that extends in the direction of l
9 has been proposed.

However, in the case of such a conventional semiconductor integrated circuit device.

The length in the direction 111 of the plurality of element regions S of the element region row 4 has a length j-N which is the number N times the number of fireflies of the reference length I, but the plurality of element region rows 4 are They are not formed to have equal lengths, and therefore have extra regions at both ends of the element region row 4, and because of ζΦ, it cannot be said that the degree of integration is sufficiently high.

Therefore, in this Ii@, the extra regions at both ends of the element region rows 40 mentioned above are used for increasing the operation, and the width of the region 2G between the adjacent element region rows 4 is reduced by ζΦ.

Therefore, the aim is to improve the degree of integration.

No. 511 shows an example of a semiconductor integrated circuit device according to the present invention, in which parts corresponding to those in II2 are given the same reference numerals, but in the configuration described above in II2, a plurality of element regions Column 4
At least the area S of *a in the required element area column 4 in
A power supply wiring I11 having a required length in the first direction so that the plurality of element region rows 4 have the same length in the first direction between required adjacent element regions 5 in the middle. It has a configuration in which a wiring region 22 having a wiring 21 such as a ground wiring is arranged.

The above is the basic idea of the semiconductor integrated circuit device according to the present invention. According to such a configuration, if the position of the arrangement area 22 is properly determined, the area 20 between the adjacent element areas 4 can be % can be made much smaller than in the case where the arrangement area 22 is not formed. By providing the arrangement region 2Q, the arrangement 1111III which connects the input/output end 9 of the element region row of the adjacent element region row 4 can be arranged in the width direction M-array in the region 20. This is because it can be made smaller than in the case where 20 is not provided.

Therefore, the present invention has a great feature that allows the degree of integration to be significantly improved compared to the conventional case.

[Brief explanation of the drawing]

No. 1 @ is an approximately 1-dimensional diagram showing a semiconductor integrated circuit device, No. 211 is an approximately 1-dimensional diagram showing its boot switch, and Figure 5 is an approximately 1-dimensional diagram showing an example of a semiconductor integrated circuit device according to the present invention. It is a temple. Applicant Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney 1) Masaharu Naka

Claims (1)

[Claims] In a semiconductor integrated circuit device having a configuration in which a plurality of element region rows each having a plurality of element regions arranged in a first direction are arranged in a second direction perpendicular to the first direction,
A first direction in which the plurality of element region rows are mutually inverse between required adjacent element regions in the plurality of element region rows. A semiconductor integrated III-value device that is formed by arranging a wiring region having a required length in a first direction so that the length is the same as that of the first direction.