JPS5878450A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5878450A
JPS5878450A JP17693581A JP17693581A JPS5878450A JP S5878450 A JPS5878450 A JP S5878450A JP 17693581 A JP17693581 A JP 17693581A JP 17693581 A JP17693581 A JP 17693581A JP S5878450 A JPS5878450 A JP S5878450A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
regions
element
region
wiring
rows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17693581A
Inventor
Katsuji Horiguchi
Mitsuyoshi Nagatani
Tsunetaka Sudo
Hiroshi Yoshimura
Original Assignee
Nippon Telegr & Teleph Corp <Ntt>
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

PURPOSE:To improve the degree of integration by effectively utilizing excessive region sections formed at both ends of an element region row and reducing the width of a region between said row and an adjacent element region row only by a section corresponding to the excessive regions. CONSTITUTION:Wiring regions 22 with wiring 21, such a power supply wiring, ground wiring, etc., which have the first directional length required, are arranged so that a plurality of the element region rows 4 have the first mutually equal directional length among necessary adjacent element regions 3 in at least plural regions 3 in element region rows 4 required in a plurality of the element region rows 4. According to such constitution, the width of the regions 20 among the adjacent element regions 4 can remarkably be made smaller than the case of no formation of the wiring regions 22 when the positions of the wiring regions 22 are properly selected.
JP17693581A 1981-11-04 1981-11-04 Semiconductor integrated circuit device Pending JPS5878450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17693581A JPS5878450A (en) 1981-11-04 1981-11-04 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17693581A JPS5878450A (en) 1981-11-04 1981-11-04 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5878450A true true JPS5878450A (en) 1983-05-12

Family

ID=16022308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17693581A Pending JPS5878450A (en) 1981-11-04 1981-11-04 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5878450A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178868A (en) * 1984-09-27 1986-04-22 Mitsui Toatsu Chem Inc Thermosetting resin molding material
JPS61110448A (en) * 1984-11-02 1986-05-28 Hitachi Ltd Wiring system of semiconductor integrated circuit
US4864381A (en) * 1986-06-23 1989-09-05 Harris Corporation Hierarchical variable die size gate array architecture
US4978633A (en) * 1989-08-22 1990-12-18 Harris Corporation Hierarchical variable die size gate array architecture
US5063430A (en) * 1989-04-27 1991-11-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having standard cells including internal wiring region
US5111271A (en) * 1989-06-26 1992-05-05 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system
US5124776A (en) * 1989-03-14 1992-06-23 Fujitsu Limited Bipolar integrated circuit having a unit block structure
WO1998040913A1 (en) * 1997-03-11 1998-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device with its layout designed by the cell base method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178868A (en) * 1984-09-27 1986-04-22 Mitsui Toatsu Chem Inc Thermosetting resin molding material
JPS61110448A (en) * 1984-11-02 1986-05-28 Hitachi Ltd Wiring system of semiconductor integrated circuit
US4864381A (en) * 1986-06-23 1989-09-05 Harris Corporation Hierarchical variable die size gate array architecture
US5124776A (en) * 1989-03-14 1992-06-23 Fujitsu Limited Bipolar integrated circuit having a unit block structure
US5063430A (en) * 1989-04-27 1991-11-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having standard cells including internal wiring region
US5111271A (en) * 1989-06-26 1992-05-05 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system
US4978633A (en) * 1989-08-22 1990-12-18 Harris Corporation Hierarchical variable die size gate array architecture
WO1998040913A1 (en) * 1997-03-11 1998-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device with its layout designed by the cell base method
US6335640B1 (en) 1997-03-11 2002-01-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device with its layout designed by the cell base method

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