JPS5878425A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high performance semiconductor device by accurately positioning a semiconductor region and a conductive layer through mutual self- alignment within the element forming region for said semiconductor region and by configurating them with small area on the substrate. CONSTITUTION:An insulating layer 48, which continuously extends over insulating regions 20, 21, an insulating layer 40 and conductive layers 43 and 44, provides windows 45 and 46 through which conductive layers 43 and 44 are exposed to the external side and a window 47 at the location opposing to a conductive layer 39, is provided and a window 49, which exposes the conductive layer 39 to external side, is formed at an insulating layer 40 under the window 47 of insulating layer 48. Thereafter, the titled semiconductor device can be obtained by forming conductive layers 50 and 51 which are connected to the conductive layers 43, 44 through the windows 45 and 46 of the insulating layer 48 and are extending over the insulating layer 48, and also forming an conductive layer 52 which is connected to the conductive layer 39 through the windows 47 and 49 of the insulating layers 48 and 40 and is extending over the insulating layer 48.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices such as bipolar transistors and MI8 field effect transistors. A semiconductor region having a predetermined conductivity is formed in the region from the main surface side, and a conductive layer as an electrode or wiring layer connected to the semiconductor region is extended on the main surface of the semiconductor substrate. As a semiconductor device, the semiconductor device is reliably positioned in the element formation region between the semiconductor region and the conductive layer in a mutually self-aligned manner;
By forming an insulating layer on the outer surface of the conductive layer described above, it is possible to easily obtain V-V. The purpose of the present invention is to propose a method for manufacturing a semiconductor device that is not only harmful to insects but also has excellent performance.

The method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. EIA~× indicates the first example of the method for manufacturing a semiconductor device according to the present invention, and 1s1W obtained in advance
Into a semiconductor wafer 11 made of silicon having a pH of *pHI as shown in FIG.
A semiconductor region 13 of N''ll is formed, and then a semiconductor region 13 of N''ll is formed on the main surface 12 of the semiconductor wafer 11 by, for example, an epitaxial growth method which is known per se, as shown in FIG.
A semiconductor layer 14 made of silicon is formed, and the semiconductor layer 14 is made of silicon.
PM semiconductor wafer 1 on which a solid semiconductor region 15 is formed
A semiconductor substrate 15 having a structure in which an N-type semiconductor layer 14 is formed on the main surface 12 of the semiconductor substrate 1 is obtained.

Next, the semiconductor wafer 11 of the semiconductor substrate 15 thus obtained
Oxidation-resistant etching masks 17 and 18 made of, for example, a silicon nitride film are formed by a method known per se in a region facing the semiconductor region 15 on the main @ 16 on the opposite side from the surface, as shown in Figure 1. , and then, by etching the semiconductor layer 14 using the oxidation-resistant etching masks 17 and 18 as masks, as shown in FIG. A groove 19 extending from the surface 16 side is formed, and in the region where the sieve 19 of the semiconductor layer 14 is formed in the 11th order,
The area surrounding the semiconductor region 13 when viewed from its main surface 16 (p
An impurity such as Pawn which provides H is introduced by ion implantation to form an impurity introduced region 22', and then a thermal oxidation treatment is performed on the semiconductor layer 14 and the impurity introduced region 22' using masks 17 and 18 as masks. By this, as shown in 1st@F, the masks 17 and 1 of the semiconductor layer 14' are
An insulating region 20 that can be polished more than the main surface 16 is formed in the area of iMeta 1 and 18 in the area other than under 8, and the insulating area 20 of the alternating conductor layer 14 is formed Mainly m14@ in the region and impurity introduction region 22'
In addition to forming an insulating region 21 (insulating regions 20 and 21 are made of silicon dioxide when the semiconductor layer 14 is made of silicon) that allows the semiconductor wafer 11 to grow longer, an impurity-introduced region 22/ , the semiconductor region 13 is IIjL11 when viewed from the main surface 1611Il with a depth reaching the semiconductor wafer 11 from the insulating region 21
! Munyo (extendable semiconductor region 22 of P star to 1/IIji
E. Thus, an element forming region 23 is formed by the semiconductor layer 14 of the semiconductor substrate 15 separated by the insulating region 21 and the conductor region 22. In this case, the element formation region 2
5, Ns is included in the semiconductor region 13 side.
N+ where I impurity diffuses and reaches insulating regions 20 and 21
A mold semiconductor region 26 is formed.

Next, as shown in FIG. 1G, the masks 17 and 18 are removed from the semiconductor layer 14 and hence the element formation region 25, and then, as shown in FIG. A window 24 that extends over the region 23 but exposes the entire -1 portion of the element forming region 25 sandwiching the insulating region 20 to the outside.
For example, an ion implantation mask 25 made of aluminum (i=limb) is formed by a method known per se.
For example, an impurity ion implantation process made from trout is carried out to give a temperature of 1,100 to 11,000 yen when the element forming region is made of silicon and the impurity ions are phosphorus ions.
50 DEG C.), and thus, as shown in FIG.

Next, as shown in FIG. 1J, after removing the mask 25, an impurity ion implantation process of boron, for example, is performed to give a P type from the side of the outer box 16, and then a heat treatment is performed. As shown in FIG.
A P-type semiconductor region 2B extending toward the semiconductor region 26 is formed. In this case, although P-type impurity ions are introduced into the semiconductor region 27 from the main surface 16 side, since the semiconductor region 27 is of N+ type, no PTj1 semiconductor region is formed in this semiconductor region 27.

Next, the semiconductor regions 27 and 28 are subjected to thermal oxidation J! (900 to 1 when the semiconductor regions 27 and 28 are made of silicon)
By drying at 100°C and oxidizing with #lL elementary atmosphere -1'1, the resultant (1Il) as shown in No. 11i1L is obtained.
A thin insulator made of an oxide of such material (silicon dioxide if the semiconductor regions 27 and 2 are made of silane) and connected to the insulating regions 20 and 21 is provided on the main surface 16 of the semiconductor regions 27 and 28. The films 29 and SO are formed, and then an oxidation-resistant layer S1 of, for example, silicon nitride, and of, for example, molybdenum, is continuously extended over the insulation regions 20 and 21 and the insulation films 29 and 30, as shown in FIG. A laminate 5 in which a high melting point metal layer 55 is laminated in a vague manner.
6 is formed by methods known per se.

Next, the oxidation-resistant layer 31 and the high point metal layer 5 thus formed
As shown in the 11th EIH, on the laminate 56 of No. 5, for example, a photoresist is used, which has windows 32 on the insulating region 21 side facing that of the semiconductor region 28 and in the region facing the semiconductor region 2811 adjacent to that of the insulating region 21. An etching master 35 is formed, and then this etching mask 5 is formed.
Etching process for the single-point metal layer 55 using S as a mask (if the high single-point metal layer 55 is made of molybdenum, etching using an etching moat in which a hydrogen peroxide-based tank and a tetramethylammonium-based solution can be used in combination)
ll), followed by etching treatment for the oxidation-resistant layer 31 (
When the oxidation-resistant layer 51 is made of silicon nitride, for example, OF
4-based etching treatment using gas plasma), followed by etching treatment for the insulating region 21 and the insulating film 50 (for example, etching treatment using a buffered hydrofluoric acid solution when the insulating region 21 and the insulating film 30 are made of silicon dioxide) As shown in FIG. 1, a lift-off mask 58 having a window 57 under the fl152 of the etching mask 55 formed by the high single point metal layer 55 and a window 34 that approximately coincides with 11157 formed by the oxidation-resistant layer 51 are formed. A window 57 laminated with a saponification-resistant master 55 having a
In addition, a window 36 is formed in the insulating film 50 to expose the semiconductor region 2B to the outside through the window 59 of the composite mask 60 and 11152 of the etching mask 33, and a composite mask is formed in the insulating region 21. body 60
#$37 is formed which faces the outside through the window 59 of the etching mask 33 and the window 32 of the etching mask 33.

Next, as shown in Figure #11 P, the etching master 33 is removed from the composite mask body 6o, followed by cleaning with toluene, acetone, etc., followed by cleaning with a buffered hydrofluoric acid solution, etc.

Next, as shown in FIG.
*5 of the composite mask body 6o of the insulating region 21 and the area facing the outside through the window 36 of the mask body 60 and the window 59 of the bond association mask body 60
A conductive layer 3 that extends continuously over the area facing the outside through 9
A conductive layer s9, which is the same as that of 8, is formed without damaging the etching mask 35 by a sputtering method, a vapor deposition method, a deposition method, a vapor deposition method, etc., which are known per se.

Next, the rear-off i-star 5 that constitutes the composite mask body 60
8 from the top of the oxidation-resistant master 55 using its solution II (for example, sulfuric acid-hydrogen perchloride island 11 in the case of sulphate 58 or molybdenum). , conductive layer 38 is removed, but conductive layer 59 remains.

Next, conductive layer 39 is thermally oxidized Jall (for example, 90
As shown in No. 1118, the outer surface of the conductive layer 59 is oxidized (oxidation treatment in normal pressure steam at a temperature of 0 to 1100° C.). Oxide of the material of the conductive layer 39 on the screen (silicon dioxide if the conductive layer 39 is made of polycrystalline silicon)
r! The insulating JII 40 is formed to have a larger thickness than the insulating films 29 and 50.

Next, as shown in No. 111T, the heated l& layer causes Pffi impurities contained in the conductive layer 39 to be introduced into the region below the conductive layer 39 of the semiconductor region 28.
+ Form a semiconductor region 41 ・Additionally, this semiconductor region 4
1 can also be formed using heat during the formation of the insulating layer 40.

Next, it’s time to give up! As shown in Figure U of WL1, an oxidation-resistant master 35 is formed by etching the mask s5 using, for example, OF4 gas plasma, and then etching the insulating films 29 and 30 using, for example, a mild hydrofluoric acid solution.
Then, the insulating films 29 and 30 are removed, and the semiconductor regions 27 and 28 and the insulating regions 20 and 21 are left outside so that s<tji. In this case, the insulating layer 40 on the outer surface of the conductive layer 59 is etched at the same time as the insulating films 29 and 30, but since its thickness is greater than the insulating films 29 and 50, the insulating layer 40 is can be left on the outer surface of the

Next, a conductive layer made of, for example, polycrystalline silicon containing an impurity of, for example, phosphorus, which provides Nl&, is formed on the semiconductor regions 27 and 28 and the insulating regions 20 and 2 by, for example, vapor phase growth.
1, and a continuous arc length is formed on the insulating layer 40, and then selective etching 4611 is performed on the conductive layer, and then the thermal conductive layer II (the conductive layer is made of polycrystalline silicon and is contained therein) is formed. When the impurity is phosphorus, 800-1000C
As shown in FIG. , a conductive layer 45 , which is applied on the semiconductor region 42 and extends around the semiconductor region 41 of the insulating regions 20 and 21 and the insulating layer 40 by the above-mentioned conductive layer. and forming a conductive layer 44 which is the same as the conductive layer 4s attached to the semiconductor region 27 and extending around the semiconductor region 27 of the insulating regions 20 and 21.Next, as shown in No. 111W, the insulating region 20 and 21,
145 that extends continuously over the insulating layer 40 and the conductive layers 43 and 44 and exposes the conductive layers 4B and 44 to the outside.
and 46 and a window 47 at a position facing the conductive layer 59 is formed by a method known per se, and a conductive layer S? A window 49 is formed that allows the outside to be viewed.

Next, as shown in FIG.
The insulating layer 4 is connected to the conductive layers 4s and 44 through the conductive layers 4s and 44, respectively.
conductive layers 50 and 51 extending over the insulating layer 8 and a conductive layer 52 extending over the insulating layer 48 and connected to the conductive layer 39 through the windows 47 and 49 of the insulating layers 48 and 40; It is formed by a known method, thus obtaining the desired semiconductor device.

The first embodiment of the method for manufacturing a semiconductor device according to the present invention has been clarified above, and the semiconductor device shown in FIG. Separated by an insulating region 21 formed from the side 1iil
In the element forming region 25 which has been designed, a region sandwiched between the semiconductor regions 26 and 28 in the element forming region 2S is a collector region, and the semiconductor regions 13 and 2-6 are a collector compensation/drawing region and a semiconductor region. 27 is a collector extraction region, the conductive layer 44 is a collector electrode, the conductive layer 51 is a collector wiring, the semiconductor region 2B is a base region, and the semiconductor region 4
1 is the base extraction region, the conductive layer S9 is the base electrode, the conductive layer 52 is the base wiring, the semiconductor region 42 is the Senken Tsuta region, the conductive layer 43 is the emitter electrode, the conductive layer 50
This constitutes an NPNW bipolar transistor with a constructional ivy wiring.

Therefore, the first embodiment of the present invention described above can be said to be an embodiment of the method for manufacturing an NPN type bipolar transistor, but the #! According to the first embodiment,
A step of forming an insulating region 21 in the semiconductor substrate 15 to separate the element formation region 23 from the semiconductor substrate 15 (FIG. 1G), and forming an oxidation-resistant layer 31 on the main surface 16 of the semiconductor substrate 15. A composite structure having a window 59 that allows at least the element forming area 25 to be exposed to the outside, which is made up of a mask 35 for oxidation resistance 1 and a lift-off i-sk 58 made of a high melting point metal layer 55 that can be extended on the oxidation-resistant mask s5. Step (jlllmlP) of forming the master body 60, and forming the composite mask body 60 on the composite mask body 60 and in the element formation region 2s.
A process 11 (jllllIQ) for forming the conductive layer 3B and 59 which can absorb impurities and be plated to provide conductivity in the area extending toward the window 59, and the composite mask body 6.
For lift Otsu that can make up 0! A step (1-R) of removing the conductive layer 5B that can be extended onto the composite mask body 60 by removing the mask 5B (F), and a step (1-R) of removing the conductive layer 5B that can be extended onto the composite mask body 60 by removing the mask 5B (F), and removing the conductive layer 5B on the area included in the window s4 of the oxidation-resistant mask 35 in the element forming area 25. An insulating layer 40 is formed on the outer 12 surfaces of the conductive layer 59 by an oxidation-sensitive layer for the conductive layer 39 that can be extended (FIG. 1), and an element forming area 5 is formed.
The process includes forming a semiconductor region 41 (FIG. 1T) formed by introducing impurities contained in the conductive layer 39 into a region under the conductive layer 39 of No. 23 (FIG. 1T). In this case, the semiconductor region 41 (as a base extraction region in this case) formed in the element formation region 25 and the conductive layer 39 (as a base electrode in this case) connected thereto are formed in the element forming region 25 (in this case, as a base electrode). and the semiconductor region 41 is divided into the insulating region 21 in a self-aligned manner.
The conductive layer 39 is positioned tightly within the bond area 23 and forms an insulating layer 40 on the outer surface of the conductive layer 39 to form an easily obtainable and intended semiconductor device on the semiconductor substrate 1.
It has a large ELL, which allows a semiconductor device to be easily constructed with a small area on the K15, and also allows a semiconductor device with excellent performance to be easily obtained.

In the case of the first embodiment of the present invention described above, it is for etching! By only using the mask 33, a semiconductor region 41 as a base extraction region, a window for connecting the conductive layer 59 as a base electrode, a window for connecting the conductive layer 59 as a base electrode, and a semiconductor region as an EITSUTA region can be formed. 42,
A window for connecting the conductive layer 4S as a construction ivy electrode to it, a conductive layer 45 as an emitter electrode, a space between the conductive layers 39 and 43 as a base electrode and a construction ivy electrode, and the like as a base, respectively. The insulating film 4D that separates the windows for connection to the semiconductor regions 41 and 42 as the lead-out region and the output region can be precisely positioned in a self-aligned manner, and can be obtained as a conductive film as the base electrode and the emitter electrode. An insulating layer 40 is formed on the surface of the conductive layer 39 as a pace electrode by thermal oxidation to form an interval between windows for connecting the conductive layers 59 and 43 to the semiconductor regions 41 and 42 as a base extraction region and an eight-star region, respectively. Furthermore, for this purpose, the semiconductor region 41 as a pace extraction region and the semiconductor region 42 as an emitter region can be brought close to each other by connecting them as shown in the figure. A bipolar transistor that can reduce the voltage can be fabricated on a semiconductor substrate &15 with a small area and with high precision.
It can be configured differently. Furthermore, since the area of the semiconductor region 28 as a pace region can be reduced for the reasons mentioned above, the PN junction capacitance of the collector base can be reduced. As mentioned above, it has a large 4IiIk, which makes it possible to sufficiently reduce the pace resistance and easily obtain a bipolar transistor that operates at high speed.

Also according to the first embodiment of the invention, conductive layers 38 and 5
9 and then removes the lift-off mask 58 made of the one-point metal layer 55 that forms the composite mask body 60, leaving only the conductive layer 39. Due to the presence of 5B, conductive layers 3B and 39 can be formed well at high temperatures,
Further, after forming the composite i-sphere body 60, the surface of the semiconductor substrate can be cleaned, and impurities can be introduced into the conductive layers 3B and 39 with precision by ion implantation. This is a problem that has a unique characteristic that allows S9 to have low resistivity and good adhesion to the insulating region 21.

Next, a second embodiment of the present invention will be described with reference to FIGS. g21MB
As shown in step 5, an oxidation-resistant etching mask 6s made of silicon nitride, for example, is formed, and then step 7! ff 65
By performing an etching heat treatment on the semiconductor substrate 1fi61 that can be stabilized, a groove 64 is formed in a region of the semiconductor substrate 61 other than under the mask 65, as shown in FIG. 2C, and then! Sufu 65
As shown in Figure 5tIE2, an insulating region 66 is formed in order to separate and define an element forming region 65 of the semiconductor substrate 61 using a thermal ironing process for the semiconductor substrate 61 using as a mask.

Next, as shown in FIG. 2F, after removing the mask 65, a thermal oxidation treatment J1 is applied to the element formation region 65, so that the surface of the element formation region 65 is covered with the oxide as shown in FIG. 2F. A thin insulating layer 67 is formed that is connected to the dense region 66 .

As shown in Fig. 2 (insulating region 66 and insulating layer 67)
An oxidation-resistant layer 68 made of silicon nitride, for example, and a refractory metal layer 105 made of molybdenum, which extend continuously therefrom, are laminated on these layers.

A laminate 104 is formed.

Next, on the laminate 106 of the oxidation-resistant layer 6's and the high melting point metal layer 105, an insulating region 66 adjacent to that of the element y/# region 65 is coated as shown in 211H. Element formation region 6 adjacent to the side of the base and the edge of the insulating region 66
For etching with windows 69 and 70 on opposite sides of S! Next, using this mask 71 as a mask, an etching process is performed for the high point metal layer 1 (15) and an etching process is performed for the oxidation-resistant layer 6.

As shown in FIG. 2I, one part of the mask 71 formed by the high melting point metal layer 105 is
14? And a lift-off mask 10 having windows 107 and 10@ under 7G? and 11 by the oxidation-resistant layer 68
Composite master body 1゛11 with 1115 and 114 according to @107 and 72 and 1G11 and 75, which is formed by laminating the oxidation-resistant layer stuff 4 with the lattice 72 and 7s substantially corresponding to 107 and 108. accomplished,
Further, the insulating layer 67 is covered with dust from the composite master body 111 and 1
14, the element forming area 6S is exposed to the outer surface of the 11HC.
#I76 and #I77 facing the outside through the x-shaped body 111DII11151CF114 are formed.Next, as shown in FIG. 2J, etching the jil-r screen 71
Combine! It is removed from above the star body 111, and if necessary, it is washed using toluene, acene, etc., and sulfur (buffered hydrofluoric acid solution).

Next, as shown in Figure 2K, a conductive layer 71 made of, for example, polycrystalline silicon, which contains PIl impurities and can be oxidized, is formed on the composite mask body 111.

Liao 9411 and 11 of element formation region 6S and insulation region 66
A conductive layer 7a that extends the IC over a region facing outside S through s.
The same conductive layer 7? and the upper region 4 facing the outside 11 through the windows 9s and 114 of the element forming region 6S and the insulating region 66.
The same conductive layer 80 as the conductive layers 78 and 79 is applied.

Next r: Lift-off master 10 that composes the II combined master body 111? By removing the conductive layer 70, the conductive layers 79 and 80 remain as shown in 211L.

Next, conductive layer 7! And, by the thermal acid source m for 0,
As shown in No. 211MK, on the outer surface including the conductive layer 79 and the sidewalls of .O, insulators 11811 and 82 made of an oxide of the base material of @O are formed.

Next, as shown in No. 211N, pH is formed by introducing Fil impurities contained in the conductive layers 79 and 80 into the region under the conductive layers 79 and 80 in the element forming region 6s by the heat treatment field. semiconductor regions s5 and $4 are formed.

The saponification-resistant master 74 is removed by etching the oxidation-resistant mask 74 as shown in Figure 2-0, and then an insulating layer 6 is formed on the insulating layer 67 as shown in Figure 2-P.
A conductive layer 85 extending over 1 and 82 is formed, . . . , thus obtaining the desired semiconductor device.

The second embodiment of the semiconductor device according to the present invention has been clarified above, and the semiconductor device shown in FIG. 2 IIC obtained by the second embodiment IIIA is as follows.

Semiconductor regions 85 and 84 are formed as a source region, a drain region, and an element formation region 65, respectively, in an element formation region 65 defined by an insulating region 66 formed in the semiconductor substrate 61 from the main side 62. The region between the semiconductor regions 85i and 84 is used as a channel region, the insulating layer 67 is used as a gate insulating film, and the conductive layers 79, 80 and 85 are used as a source electrode @FJ11 wiring layer, a drain electrode or wiring layer, and a dirt electrode or wiring layer, respectively. This constitutes a P-channel M1g field effect transistor.

Therefore, the above-mentioned example #2 of the present invention can be considered as an example of the method for manufacturing an r-channel MI8g field effect transistor, but this is the second example of the present invention. According to , it is detailed in the am beak, but this is omitted.
Since it has a size similar to the first embodiment of the present invention, a small area is formed on the semiconductor substrate I [61] so that the intended semiconductor device can be manufactured in the same manner as the first embodiment of the present invention. Therefore, it can be constituted as a harmful bird, and along with that, Ik
It has the unique characteristic of being able to obtain a semiconductor device with excellent performance from a pest base ζ.

In the case of the second embodiment of the present invention, which can be improved, the conductive layers 79 and 80 as the source region and the drain region as the half-d drain m-pole are Dust for connecting, conductive layer 7? and 0 as source electrode and drain electrode, insulating layer 67% as dirt insulating layer, conductive layer 7? as source electrode and drain electrode, oath 80. Each insulating layer 81
1 and 82, the conductive layer 85 as a dart-pole is precisely positioned in a self-aligned manner, and the conductive layer 7? Since it is difficult to make the minute intervals determined by J4 and 80 and 82, MI8 field effect transistors are configured on the semiconductor substrate 61 with a small product and a high detection f. It has great features such as being able to

Also, in the case of the second embodiment of the present invention described above.

Since the composite mask body 111 is used as in the case of the first embodiment, details [11! Although this is omitted here, it has the same excellent features as described regarding the composite mask body 60&c in the first embodiment.

Next, a fifth embodiment of the method for manufacturing a semiconductor device according to this book a@ will be described with reference to FIGS. The man omitted this, but as shown in No. 51g1-C, he took the same steps as described above in Fig. 1, 5-0, and as shown in No. 5lllO,
The main 1i1 of the semiconductor quench 11 at a pH that forms the semiconductor region 1s in the %N+ position is similar to that described above in No. 1110.
A semiconductor substrate 15 is obtained having a structure in which a semiconductor layer 14 of N11 is formed on 2, ::, s.

% on the semiconductor layer 14 of the resulting semiconductor substrate 15.
As shown in the first step DK, an insulating layer 120 made of, for example, saponified silicon is formed by, for example, thermal oxidation.

Next, on the insulating layer 12G, as shown in FIG.
In the same way as described above in D, oxidation-resistant elatin column task 17
and 18, and then the insulating layer 120 is etched using the saponification-resistant etching masks 17 and 18 as masks.
-ill I mll K In the same manner as in 4d above, grooves 19 are formed, and then grooves 1 to 4 of the semiconductor layer 14 are formed in the area where the grooves 1 to 4 are to be formed, as shown in FIG. Similarly, the impurity introduced region 2r is formed, and the impurity introduction region 2r is formed.
As shown, similarly to the 111F occasion, the insulating regions 20 and 21 were formed by the heat forging treatment, and the pH semiconductor region 22 was formed by 1 m, so that the insulating region 21 and the semiconductor region 22#c were separated by An element formation region 25 of the defined semiconductor layer 14M of the semiconductor substrate 15 is formed by i#.

Next, perform ion implantation treatment of impurities that give NIII, for example, impurity, then heat treatment, and thus the fifth cabinet H#
As shown in FIG.
NIl semiconductor region 2 connected to +■ semiconductor region 26
7#c.

Next, by performing ion implantation treatment with an impurity such as boron to provide a rim, and then performing heat treatment, the main 1i
A semiconductor region 28 of pHl that can be polished from the i16 side toward the semiconductor region 26 is formed.Next, as shown in FIG. The refractory metal layer 55 is formed by methods known per se.

Next, on the high single point metal layer 55 formed in this way, as shown in FIG.
As shown in Figure 1, an etching master 55 is formed in the same manner as in Figure 1N, and then this etching master s5 is formed.
The etching process for the high melting point metal layer 55 using as a master, the subsequent etching process for the oxidation-resistant layer 51, and the subsequent etching process for the insulating region 21 and the edge film i0 are described above with reference to FIG. By doing this, as shown in 5th IILK, a lift-off mask 58 having an IC layer S7 under 1I52 of the etching master s5 by the high melting point metal layer 5s, and a window 57 by the anti-aging star 1. An oxidation-resistant mask 55 with a curvature 54
A composite mask body 60 having a window S9 formed by laminating the window 57 and s4 is formed, and a composite master body 60tD*S9 and the edge 5 of the etching master 55 are formed on the insulating film 50.
Maro which exposes the semiconductor layer 28 to the outside 11 through 2! When #6 is 1lIIE, a composite mask body is formed in the #C insulation region 21,
A groove S7 facing the outside is formed through 1159 of 60 and the edge s2 of the etching master 5s.

Next, as shown in MIC 111, the etching mask 55 is removed from the composite mask body 60, followed by cleaning with toluene and acetone, followed by cleaning with a mild hydrofluoric acid solution, etc.

Next, a conductive layer 58 extending over the composite mask body 6G is shown in the 5th IIN6c.
and the window 56 of the insulating film 5° of the semiconductor region 28 and the window 5 of the composite mask body 60? The same conductive layer as the conductive layer 5 which can be continuously extended over the region facing the outside through the window 59 of the composite mask body 60 of the insulating region 21! 1
9.

Next, by applying the lift-off mask 5B constituting the composite mask body 60 over the oxidation-resistant master S5,
As shown in No. 5110, the conductive layer 5B is removed while the conductive layer 59 is left.

Next, the conductive layer s9 is subjected to thermal saponification treatment, as shown in FIG.
As shown in K<, as in the case of $11118, the conductive layer s9
An insulating layer 40 is formed with a thickness greater than that of the insulating layer 120 on one outer surface including the side of the insulating layer 120 .

Next, as shown in Figure Q#c of %II5 by heat treatment, the first WJ
Case of T and Oka! A P+ type semiconductor region 41 is formed in the region under the conductive layer 59 of the semiconductor region 2B by introducing pH impurities contained therein from the conductive layer S9.

Next, the oxidation-resistant mask 17 and S5 are etched, followed by the insulating layer 120#! By etching the oxidation-resistant masks 17 and 5 as shown in the 51ilR1
5% and the insulating layer 120 are removed, and the semiconductor regions 27 and 2 are removed.
B, JLQ 'Zetsu 1111 area 20 kU 211 outside 11K
Thus, if the configuration described above in FIG. 1 is described above, a similar configuration is obtained.

After passing through the same 1st stage as mentioned above in 111th V to X,
Obtain the desired semiconductor device.

The fifth embodiment of the method for manufacturing a semiconductor device using the present li@ has been clarified above, and the semiconductor device obtained by the fifth embodiment is similar to the NPN@pipo This constitutes a nine-digit transistor.

Therefore, the embodiment 5 of the present invention described above can be said to be an embodiment of the method for manufacturing an NPN type bipolar transistor, but according to the fifth embodiment of this invention, the percentage shown in FIG. Similar to the case of the first embodiment of the present invention, which will be described in detail below, there is a royal authority (FIG. 5G) to form an insulating region 21 in a semiconductor substrate 15 to separate and define an element formation region 25 from its main body 1ii1611. , an oxidation-resistant mask 55 formed of an oxidation-resistant layer 51 extending only over the element formation region 25 on the main surface 16 of the semiconductor substrate 15;

The oxidation-resistant mask 55 and the main body 11i of the semiconductor substrate 15
A window 5 that allows at least the element formation region 25 to be exposed to the outside, comprising a lift-off mask 58 made of a high-melting point metal layer 55 that extends over a region where the oxidation-resistant layer 55 on the oxidation-resistant layer 55 does not extend.
Step 1ll of forming the composite mask body 60 having 9 (fifth
1! IM) and.

A predetermined guide w1a that can extend over the composite mask body 60 and the region facing the window 59 of the composite mask body 60 in the element formation region 25
! a step of forming conductive layers S8 and 59 which can be saponified and which can give a negative effect (FIG. 5N);
Step 1 of removing the long conductive layer 5B on the composite mask body 60 by removing the lift-off master S8 constituting 0
m (5-0) and the conductive layer 5 that can be extended on the region facing @54 of the oxidation-resistant mask s5 in the element formation region 2s? IC
Conductive layer 5! Outside *mK insulation layer 4
0 forming factory (stripes 511P) and element forming area 25
Conductive layer 5! A step (first sIIQ) of forming a semiconductor region 41 formed by introducing impurities contained in the conductive layer s9 into the lower region, so as to obtain a target semiconductor device (in this case, a bipolar transistor). The detailed explanation will be omitted, but the first I
In the case of I, it has the same excellent characteristics as those mentioned above.

To describe the fourth embodiment of this vh@ with the next 4 figures M~P, the parts corresponding to those in Figure 112 will be given the same reference numerals, and detailed explanations will be omitted. In the second embodiment of the present invention described above in the second section, the enemy resistant master 4 constituting the composite master body 111 is made of semiconductor material as in the case of the fifth embodiment of the present invention. An insulating layer 150 (corresponding to the insulating layer 15G in FIG. S) is formed on the substrate 61, and an oxidation-resistant mask 6S similar to that described above in FIG. 2B is formed on the bonding layer 150. , and the master 6s is obtained as shown in FIG. 2.

Therefore, further details of the J1ml1ml beak will be omitted, but according to the fourth embodiment of the present invention, MI8) Rungis I, which is similar to that described above in J1211, is replaced with the fourth embodiment of the present invention, which is described above in Ss. By a method similar to the case of Example 5,
This can be obtained using the same excellent If# mold as described above in FIG.

The above description merely shows a few examples of the present invention, and various modifications and changes may be made without departing from the spirit of the present invention.

Table Brief Description of the Drawings °□゛ Figure 1 M-X shows the first embodiment of the method for manufacturing a semiconductor device according to the present invention. Linear cross-sectional views in sequential steps showing a second embodiment of m-washing of a semiconductor device according to the present invention, FIG.
4A to 4C are cross-sectional views showing sequential steps showing a fifth embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. Sequential work 8! This is a cross-sectional view of the route.

・Applicant Nippon Telegraph and Telephone Public Corporation #1 Figure 1 1111 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1:lJ:1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 1 ( 1 Rattan 2 Figure 2 Figure 3 Figure 3 Figure 3 Figure 3 Cause 3 Figure 4 Figure 4 Figure 4 H Figure 114 Procedural Amendment Document February 26, 1980 1, Incident Display of 1986 轡・Permission No. 1749!!4 No. 2・Issue-
Name of manufacturing method for medium conductor device 3, Relationship with the case of the person making the amendment 4, agent is type N+,” he corrected.

(2) Please replace the phrase ``Hydrogen peroxide-based etching treatment'' with ``oxidation treatment using a hydrogen peroxide-based solution'' from the second line from the bottom of page 9 to the first line of page 10. , followed by an etching process using a tetramethylammonium-based etching solution.''

(3) On page 11, lines 2-5, "toluene" should be corrected to "triclene."

(4) 11th line 14-16 [formed by vapor phase growth method]. '' should be corrected to ``formed by vapor phase growth method, etc.''.

(5) Page 14, line 1 rN! The name ilJ is “N”
``+ type'' is corrected.

°(6) Please correct "41" in line 4 of page 14 of tIIi to "42".

()) Please correct the phrase ``semiconductor regions 13 and 26...--semiconductor region 27'' to ``semiconductor regions 15, 26, and 27'' on page 15, lines 13-14.

(8) On page 25, line 1o, "toluene" should be corrected to "triclene."

(9) 1II28W1 line rJ11wJDJ Toa6
') Correct Ifs diagram DJ. 6. Therefore, line 2114 "In Figure 3 G" is tgsW in the first order! "Aa," he corrected.

1. However, the FM oxidizing layer 51 J in rows 50jj and 3 is corrected to read ``abrasion-resistant etching mask 18''.

Axis: "Insulating film 30" on page sO, lines 5 and 13, respectively.
The respective descriptions have been corrected to read "insulating film 12o."

Rin: In the 1st and 2nd lines of the 51st member, ``Toluene'' should be corrected to ``Tokuren''.

a4 Page 31, line 6 [Insulation l1ls OJ is corrected to read "insulating film 12o."

as Please correct the text ``Oxidation-resistant layer 5o'' on page 35, line 10.

In the 33rd member 1'2 line, "oxidation-resistant layer 35" should be corrected to "oxidation-resistant master 35."

an, line 543116 rllE4 Figure A-PJ
Correct door 6 to rj14gang A-OJ.

Page 55, line 1, "of the present invention" [3rd page]
This is corrected as "of the present invention shown in the figure."

Correction: On page 35, lines 2 to t1, the phrase "insulating layer 160 in the case of 3 tM" is corrected to "insulating layer 120 in the case of FIG. 3."

an an, 11111-G (M2jlli),
1111H~J (5th Ji), Figure 1 NP (g4 system), and Figure 1 Q~8 (5th jlii) are circularly pressed as shown in the attached sheet. (17th series), and 59th series
N-P(141B:s)') Attachment (7) Correct h.

that's all Figure 1 3rd rllJ Figure 3

Claims (1)

[Claims] 1. A step of forming an insulating region in the #P conductor substrate to separate and define an element formation region from the main picture side thereof; Forming a composite mask body comprising an oxidation-resistant mask and a 97-off master made of a high single-point metal layer extending on the oxidation-resistant layer, and having a window that allows at least the element formation area to be exposed to the outside. and a step of forming a conductive layer containing an impurity that provides a predetermined conductivity type and capable of being hardened, extending over the composite mask body and the region of the element formation region facing the window of the composite mask body; The above 7 to-offs can be used to form a composite mask body! a step of removing the conductive layer on the composite i-framework by removing the star, and an oxidation-sensitive layer for the conductive layer extending over the region facing the oxidation-resistant mask in the element formation region. A factory for forming an insulating layer on the outside of the conductive layer, and a semiconductor region formed by introducing impurities contained in the m* conductive layer into the region under the conductive layer in the element formation region. 411. A method for manufacturing a semiconductor device, which includes a step of forming a semiconductor device. 2 The element type 1lLI from its main Iiii@ in the semiconductor substrate
forming an insulating region to separate the I region;
- On the main surface of the semiconductor substrate, the oxidation-resistant master is formed by an oxidation-resistant layer that extends only on the element formation region, and the anti-cough master is formed on the oxidation-resistant layer and the main surface of the semiconductor substrate. For lift-off using a high single point metal layer that can be extended over areas where the oxidative layer does not extend! a step of forming a composite mask body having at least a window that extends the element formation region outward, and forming a composite mask body on the composite mask body and on a region of the element formation region facing - of the composite master body; a step of forming a conductive layer that contains impurities and can be oxidized to give a predetermined conductivity type that can be extended, and a conductive layer that can be extended on the composite mask body by removing the upper one-point mask that constitutes the composite mask body; forming an insulating layer on the outer surface of the conductive layer by oxidizing the conductive layer extending over the region facing the window of the oxidation-resistant mask in the element formation region; A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor region in a region below the conductive layer in the element formation region by introducing impurities contained therein from the conductive layer.