JPS5875379A - Compensating circuit for up-down pincushion distortion - Google Patents
Compensating circuit for up-down pincushion distortionInfo
- Publication number
- JPS5875379A JPS5875379A JP17339881A JP17339881A JPS5875379A JP S5875379 A JPS5875379 A JP S5875379A JP 17339881 A JP17339881 A JP 17339881A JP 17339881 A JP17339881 A JP 17339881A JP S5875379 A JPS5875379 A JP S5875379A
- Authority
- JP
- Japan
- Prior art keywords
- vertical
- signal
- circuit
- waveform
- blanking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
- H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
- H04N3/233—Distortion correction, e.g. for pincushion distortion correction, S-correction using active elements
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
Description
【発明の詳細な説明】
上下ビンクッション歪を補正するものとして平衡変調器
や可飽和リアクターを用いた補正回路がある。DETAILED DESCRIPTION OF THE INVENTION There is a correction circuit using a balanced modulator or a saturable reactor to correct vertical bin cushion distortion.
第1図は平衡変調器を用いた補正回路の一例で。Figure 1 shows an example of a correction circuit using a balanced modulator.
同期分離回路(1)で分離された1直同期パルスPvが
のこぎり波発生回路(2)K供給されc[垂直のむぎり
波信号Sv (第2図A)が形成され、一方同期分離さ
れた水平同期パルスpHが積分回路等で構成されたパラ
ボラ波発生回路(3)に供給されて水平パラボラ波信号
8H(第2図B)が形成される。One series synchronous pulse Pv separated by the synchronous separation circuit (1) is supplied to the sawtooth wave generation circuit (2) K to form a vertical sawtooth wave signal Sv (Fig. 2 A), while the synchronous separation The horizontal synchronizing pulse pH is supplied to a parabolic wave generation circuit (3) composed of an integrating circuit, etc., to form a horizontal parabolic wave signal 8H (FIG. 2B).
垂直のζぎり波信号syと水平パラボラ波信号8Hとは
平衡変調器(4)に供給されて、水平パラボラ波信号8
Hが垂直のこぎり波信号syで平衡変調された上下ビン
クツシ嘗ン歪の補正信号80R(同図C)が形成され、
これが金成器(5)で1厘のこぎり波信号8vK重畳さ
れる。The vertical ζ-wave signal sy and the horizontal parabolic wave signal 8H are supplied to a balanced modulator (4) to generate the horizontal parabolic wave signal 8.
A correction signal 80R (C in the same figure) of vertical and vertical distortion is formed in which H is balanced-modulated with a vertical sawtooth signal sy.
This is superimposed with a sawtooth wave signal of 8vK by a metal generator (5).
この合成信号8AD (同図D)は比較回路(6)で画
面サイズ等の補正信号S8と比−較されたのち、その比
較信号8D (同図n)が喬厘出力回路四に駆動信号と
して供給さ・れる。This composite signal 8AD (D in the same figure) is compared with a correction signal S8 for screen size, etc. in a comparator circuit (6), and then the comparison signal 8D (n in the same figure) is sent to the QiaoLan output circuit 4 as a drive signal. supplied/received.
―直出力回路01はコンブリメント5EPP接続された
一対のトランジスタQl、 Q2と駆動信号SDが供給
される入力トランジスタQ3とで構成され。- The direct output circuit 01 is composed of a pair of transistors Ql and Q2 connected in a combination 5EPP and an input transistor Q3 to which a drive signal SD is supplied.
そしてこの垂直出力回路−には垂直偏向コイルLDYが
接続されて、このコイルLDYに補正信号8CHの重畳
された垂直偏向電流が流れる。A vertical deflection coil LDY is connected to this vertical output circuit, and a vertical deflection current superimposed with a correction signal 8CH flows through this coil LDY.
なお、コンデンサCは8字補正用のコンデンサであり、
Rは1厘偏向電流を検出するための抵抗であって、その
両端に得られる検出電圧が画面サイズ等の補正信号8B
として利用される。In addition, capacitor C is a capacitor for character 8 correction,
R is a resistor for detecting the deflection current, and the detection voltage obtained at both ends is used as a correction signal 8B for screen size, etc.
used as.
さて、この補正回路では第2図に示すよ5に、珠直帰線
期間TIでも平衡変調動作が行なわれているので、この
期間TRK41第2図Cに示すような補正信号80Rが
得られる。そのため、垂直出力回路QIK供給される駆
動信号8Df)#I線パルスPRも変調されて第2図E
ft示すようにその波形が歪んでし1.なお、この第2
図の水平周期と垂直帰線期間TRとの関係は実際の期間
の関係とは対応していない、実際には第3図のよ5にな
る。Now, in this correction circuit, as shown in FIG. 2, the balanced modulation operation is performed even during the vertical retrace period TI, so that a correction signal 80R as shown in FIG. 2C is obtained during this period TRK41. Therefore, the drive signal 8Df) #I line pulse PR supplied to the vertical output circuit QIK is also modulated and
The waveform is distorted as shown in ft.1. Note that this second
The relationship between the horizontal period and the vertical retrace period TR in the figure does not correspond to the relationship between the actual periods; in reality, it is 5 as shown in FIG.
この図は、に直帰線期間TRを12H(Hは1水平周期
)Kl、た場合の例であって、本来の帰線パルスp5は
1点鎖線で示すような歪のない波形であるが、実際には
垂直帰線期間Tg:に存在する補正信号SCRKよって
1図のように水平パラボラ波信号8Hの重畳された波形
となって得られる。This figure shows an example in which the rectangle period TR is 12H (H is one horizontal period) Kl, and the original retrace pulse p5 has a waveform without distortion as shown by the dashed line. , in fact, a waveform on which the horizontal parabolic wave signal 8H is superimposed is obtained as shown in FIG. 1 by the correction signal SCRK present in the vertical retrace period Tg:.
1厘出力回路輪はこの歪んだ倦縮パルスPRV有する駆
動信号8Dによって駆動されるから次のような不都合が
生ずる。Since the output circuit wheel is driven by the drive signal 8D having the distorted compressed pulse PRV, the following problem occurs.
すなわち、nフィールド目に得られた駆動信号SDのう
ち帰線パルスPRの波形が図のような場合で、トランジ
スタQsのVBIがIia図の直11iRmであるとき
には、点1がトランジスタQsのオン、オフの切換点と
なる。これに対し、(n+1)フィールド目の駆動信号
はnフィールド目の駆動信号に対しo、inだけずれる
ので、帰線パルスPRK重畳される水平パラボラ波信号
8H4,0,5Hだけずれることになる。従−って、
(Il+1)フィールド目の帰線I(ルスPHの直l
ll5上でのエンベ−ロープ(部分的)は第3図破線で
示すように、 0.5Hだけずれる。その結果、(n+
1)フィールドでのトランジスタQsの切換点は1点よ
り0.5Hだけ時間的に先行した点すとなる。That is, when the waveform of the retrace pulse PR of the drive signal SD obtained in the n-th field is as shown in the figure, and when the VBI of the transistor Qs is 11iRm in the diagram Iia, point 1 is the ON state of the transistor Qs. This is the off switching point. On the other hand, since the drive signal of the (n+1)th field is shifted by o, in from the drive signal of the nth field, it is shifted by the horizontal parabolic wave signal 8H4, 0, 5H superimposed with the retrace pulse PRK. Therefore,
(Il+1) field retrace I (direction of Luss PH
The envelope (partial) on ll5 is shifted by 0.5H, as shown by the broken line in FIG. As a result, (n+
1) The switching point of the transistor Qs in the field is a point temporally preceding the first point by 0.5H.
このように、フィールドによってトランジスタQsの切
換タイインタかずれるため、Iii[出力信号によって
一直偏向コイルLDYに流れる垂直偏向電流の位相が片
寄り、その結果インターレースが不完全なものとなる。As described above, since the switching tie-inter of the transistor Qs is shifted by the field, the phase of the vertical deflection current flowing through the linear deflection coil LDY is shifted by the output signal Iii[, resulting in incomplete interlacing.
つまり、nフィールドでのラスターの中間K (El+
1) フィールドのラスターが位置せず、どちら側かに
片寄ってしまうため、正しくインターレースしなくなっ
てしまう、この問題は第1図に示す平衡変調器(4)t
−用いた補正回路に限らず、可飽和リアクターを使用し
た通常周知の補正回路でも発生する。That is, the middle K (El+
1) The raster of the field is not positioned and is shifted to either side, resulting in incorrect interlacing.This problem is solved by the balanced modulator (4)t shown in Figure 1.
- This phenomenon occurs not only in the correction circuit used, but also in a commonly known correction circuit using a saturable reactor.
このインターレースの不完全さは、家庭用などに供され
る1通常のテレビジョン受像機では殆んど問題にならな
いが、特に放送局内の!スターモニター用として使用さ
れるような高級なテレビジョン受像機では、インターレ
ースが正確に行なわれる必要があるため、これを補正す
る必要がある。This imperfection of interlacing is hardly a problem in normal television receivers used for home use, but it is especially true in broadcasting stations! In high-end television receivers such as those used for star monitors, interlacing must be performed accurately, so it is necessary to correct this.
そこで、この発明では正しくインターレースするように
工夫したものである。そのため、この発明は上下ビンク
ッション歪を補正するための補正信号を垂直走査期間の
み1直出品回路(IK供給するようにしたものである。Therefore, the present invention is devised to interlace correctly. Therefore, in the present invention, a correction signal for correcting the upper and lower bottle cushion distortion is supplied to one direct output circuit (IK) only during the vertical scanning period.
続いて、この発明の一例を上述の補正回路に適用した場
合につき第4図以下を参照して説明する。Next, a case in which an example of the present invention is applied to the above-mentioned correction circuit will be described with reference to FIG. 4 and subsequent figures.
第4図に示す例は、平衡変調器(4)に供給される垂直
のこぎり波信号Svのうち、[i[m線部間TRK得ら
れる垂直のこぎり波信号をブランキングするようkした
場合で1図のようにブランキング回路−が設けられ、こ
れには垂直周期のブランキングパルスFB (IIS図
B)・が供給される。In the example shown in FIG. 4, when the vertical sawtooth signal Sv supplied to the balanced modulator (4) is blanked, the vertical sawtooth signal obtained by [i[m As shown in the figure, a blanking circuit is provided, to which a vertically periodic blanking pulse FB (IIS diagram B) is supplied.
従って、このブランキングをかけることによって垂直の
こぎり波信号Sv′は第5図CのようKなるから、垂直
帰線期間THの禎平衡変調出力は零になる。そのため、
平衡変調器(4)からは垂直帰線期間TRのみ信号が欠
如した第5図りに示すような補正信号80Rか出力され
、その結果、比較回路(6)より出力される駆動信号S
D′は第5図Fの如くなって帰線パルスPRには水平パ
ラボラ波信号sHが全く存在しなくなる。Therefore, by applying this blanking, the vertical sawtooth signal Sv' becomes K as shown in FIG. 5C, so that the balanced modulation output during the vertical retrace period TH becomes zero. Therefore,
The balanced modulator (4) outputs a correction signal 80R as shown in Figure 5, in which no signal is present during the vertical retrace period TR, and as a result, the drive signal S output from the comparator circuit (6)
D' becomes as shown in FIG. 5F, and there is no horizontal parabolic wave signal sH in the retrace pulse PR.
このことから、トランジスタQ3のオン、オフタインン
グはnフィールドも、(fl+1)フィールドも。From this, the on/off timing of transistor Q3 is the same for both the n field and the (fl+1) field.
ともに同一時点となり、11直偏向電流従って、垂直偏
向のタイインタが一致し、ラスターは正しくインターレ
ースすることになる・
なお、6厘のむぎり波信号Svをブランキングするので
はなく、Ii直帰線期間TRk得られる水平パラボラ波
信号sHをブランキングしても、!11厘帰線期間TR
のみ信号が欠如した補正信号ScRが得られる。Both are at the same point in time, 11 direct deflection currents Therefore, the vertical deflection tie-inters match, and the raster is correctly interlaced.In addition, instead of blanking the 6-line shear wave signal Sv, Ii direct deflection Even if you blank the horizontal parabolic wave signal sH obtained during the period TRk,! 11th return period TR
A corrected signal ScR is obtained in which only the signal is missing.
また、第4図の例では[1IiLのこぎり波信号8vを
加算器(5)K供給するようにしであるが、この−厘の
こぎり波信号Svに代えてブランキング後の垂直のこぎ
り波信号Sv′を加算器(5)K供給するよ5KL。In the example of FIG. 4, the [1IiL sawtooth signal 8v is supplied to the adder (5) K, but the vertical sawtooth signal Sv' after blanking is used instead of the -1IiL sawtooth signal Sv. Adder (5)K supplies 5KL.
てもよい。It's okay.
第6図は可飽和リアクターにより上下ピンクツシラン歪
を補正するようKした補正回路にこの発明を適用した場
合であって、可飽和リアクター(至)の1次コイル(3
01) Kは水平同期パルスPHか供給されるが、この
例ではブランキング回路cIIJv介して水平同期パル
スpHが供給されるようになされている。また、その2
次コイル(36b)は可変インメクタンス素子Glv介
して垂直偏向コイルLDY K接続されると共に、2次
コイル(30b)と可変インダクタンス素子0υに対し
、並列にコンデンサーが接続されて並列共振回路(至)
が構成され、可変インダクタンス素子Cl1)を調整し
て垂直偏向電流に重畳される。上下ビンクッション歪の
・補正信号たる水平パラボラ波信号sHの位相が制御さ
れる。Fig. 6 shows a case where the present invention is applied to a correction circuit designed to correct upper and lower pink distortion distortion using a saturable reactor.
01) K is supplied with the horizontal synchronizing pulse PH, and in this example, the horizontal synchronizing pulse pH is supplied via the blanking circuit cIIJv. Also, part 2
The secondary coil (36b) is connected to the vertical deflection coil LDYK via the variable inductance element Glv, and a capacitor is connected in parallel to the secondary coil (30b) and the variable inductance element 0υ to form a parallel resonant circuit (toward).
is configured, and is superimposed on the vertical deflection current by adjusting the variable inductance element Cl1). The phase of the horizontal parabolic wave signal sH, which is a correction signal for vertical bin cushion distortion, is controlled.
補正回路をとのよ5に@成することKよりても、水平同
期パルス−の供給を、ブランキングパルスPBKよって
制御できるから、垂直帰線期間TRのみ信号が欠如した
補正信号によって上下ビンクツシ四ン歪を補正できる。Since the supply of the horizontal synchronizing pulse can be controlled by the blanking pulse PBK, the correction circuit can be controlled by the blanking pulse PBK. It is possible to correct the distortion.
以上説明したようにこの発明によれば、Ii厘帰線期間
TRは補正信号が存在しないので、帰線パルスPRの波
形が水平パラボラ波信号8Hによ・って1されない。そ
のため、フィールドによって1直偏向のタイインタが変
動しないから、ラスターを正しくインターレースさせる
ことができる。従って、この発明は特に、局内のマスタ
ーモニター用のテレビジ曹ン受像機に適用して極めて好
適である。As described above, according to the present invention, there is no correction signal during the Ii retrace period TR, so the waveform of the retrace pulse PR is not set to 1 by the horizontal parabolic wave signal 8H. Therefore, since the tie-inter of the single direct deflection does not vary depending on the field, the raster can be correctly interlaced. Therefore, the present invention is particularly suitable for application to a television receiver for a master monitor in a station.
第1図は上下ビンタッシ冒ン歪補正回路の従来例を示す
系統図、第2図及び第3図はその動作説明に供する波形
図、第4図はこの発明に係る上下ビンクッシ冒ン歪補正
回路の一例を示す系統図。
第6図はその動作説I!AK供する波形図、第6図はこ
の発明の他の例の要部を示す接続図である。
(2)は―直のこぎり波信号8VF)形成回路、(3)
は水平パラボラ波信号sHの形成回路%(4)は平衡変
調器′、aのは1直出力回路、 LDYは1直偏向コイ
ル。
SCRe SCRは補正信号である。
第2図FIG. 1 is a system diagram showing a conventional example of an upper and lower binarcus distortion correction circuit, FIGS. 2 and 3 are waveform diagrams for explaining its operation, and FIG. 4 is an upper and lower binarcus distortion correction circuit according to the present invention. A system diagram showing an example. Figure 6 shows the theory of operation I! FIG. 6 is a connection diagram showing the main parts of another example of the present invention. (2) - sawtooth wave signal 8VF) formation circuit, (3)
is a horizontal parabolic wave signal sH forming circuit % (4) is a balanced modulator', a is a single direct output circuit, and LDY is a single direct deflection coil. SCRe SCR is a correction signal. Figure 2
Claims (1)
走査期間のみ供給し、Illll縁期間は供給しないよ
うにした上下ビンクツシ田ン歪補正回路。A top and bottom bin distortion correction circuit supplies a correction signal for correcting top and bottom bin cushion distortion only during one direct scanning period, and does not supply it during Illllll edge periods.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17339881A JPS5875379A (en) | 1981-10-29 | 1981-10-29 | Compensating circuit for up-down pincushion distortion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17339881A JPS5875379A (en) | 1981-10-29 | 1981-10-29 | Compensating circuit for up-down pincushion distortion |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5875379A true JPS5875379A (en) | 1983-05-07 |
Family
ID=15959667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17339881A Pending JPS5875379A (en) | 1981-10-29 | 1981-10-29 | Compensating circuit for up-down pincushion distortion |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5875379A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61293072A (en) * | 1985-06-20 | 1986-12-23 | Mitsubishi Electric Corp | Correcting circuit for upper and lower pincushion distortion |
WO2002076087A1 (en) * | 2001-03-15 | 2002-09-26 | Matsushita Electric Industrial Co., Ltd. | Vertical deflection apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS553871A (en) * | 1978-06-27 | 1980-01-11 | Toho Rayon Co Ltd | Adsorbent for removal of poisonous gas containing sulfur |
-
1981
- 1981-10-29 JP JP17339881A patent/JPS5875379A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS553871A (en) * | 1978-06-27 | 1980-01-11 | Toho Rayon Co Ltd | Adsorbent for removal of poisonous gas containing sulfur |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61293072A (en) * | 1985-06-20 | 1986-12-23 | Mitsubishi Electric Corp | Correcting circuit for upper and lower pincushion distortion |
JPH0521470B2 (en) * | 1985-06-20 | 1993-03-24 | Mitsubishi Electric Corp | |
WO2002076087A1 (en) * | 2001-03-15 | 2002-09-26 | Matsushita Electric Industrial Co., Ltd. | Vertical deflection apparatus |
US6831427B2 (en) | 2001-03-15 | 2004-12-14 | Matsushita Electric Industrial Co., Ltd. | Vertical deflection apparatus |
US7166972B2 (en) | 2001-03-15 | 2007-01-23 | Matsushita Electric Industrial Co., Ltd. | Vertical deflection apparatus |
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