JPS5875322A - Phase and frequency comparator - Google Patents

Abstract

PURPOSE:To obtain an ideal 3-state output through a simple constitution of circuit, by using the 1st and 2nd bistable networks which are set by the output signals given from a frequency detecting means. CONSTITUTION:For a frequency comparator containing a frequency detecting mean and a frequency discriminating means, an inverting action is repeated with an inverting period corresponding to the distributing period in case the effective pulse that can invert the output state of the 1st and 2nd bistable networks 16 or 22 is applied alternately to input terminals A and B. As a result, the output level is kept at an L level for AND gates 12 and 13 respectively. At the same time, the frequency of the pulse signal applied to an input terminal of one side is set higher than that of the pulse signal applied to the other terminal to produce ineffective pulses. Even in such case, the output states of the networks 16 and 22 are not inverted, and the frequency comparing signals are obtained through output terminals E and F of the 3rd bistable network 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase and frequency comparator, and its first purpose is to provide a phase and frequency comparator that can compare the phase difference and frequency difference between two systems of pulse signals with a simple configuration. The object of the present invention is to obtain a frequency comparator, and further to obtain a phase and frequency comparator capable of independently taking out a phase comparison output and a frequency comparison output between the pulse signals.

A second object of the present invention is to respond to cases where the frequency of one of the two systems of pulse signals is higher or lower than the other, and furthermore, when the frequency difference between the two systems of pulse signals is zero. The object of the present invention is to obtain a frequency comparator whose output can be taken out.

A third object of the present invention is that when the frequency of one of the two pulse signals is higher than the other, a first DC level output is obtained, and when the frequency is lower, a second DC level output is obtained,
Furthermore, when the frequency difference between the two systems of pulse signals is zero, a phase error output corresponding to the phase difference between the pulse signals is obtained, realizing the configuration of a phase and frequency comparator with three nutate outputs. There is a particular thing.

In recent years, the use of phase comparators or frequency comparators has been increasing due to the rapid spread of locked loops (hereinafter referred to as PLLs).

A typical phase and frequency comparator that can simultaneously compare the phase difference and frequency difference between two systems of pulse signals is disclosed in U.S. Pat. No. 3,610,954.
The circuit shown at the brightest side is shown in FIG. 1, and its logical configuration is shown in FIG.

The circuit shown in FIG.
, No. 773, U.S. Pat. No. 3,206,438, U.S. Pat. No. 3,328,688.

U.S. Patent No. 3,370,252, Japanese Patent Publication No. 47-12923, and G111's paper 0
(Use IC5inYour Phase-Lock
ed Loop, +-IKI electronic Deg
ign, pri1.11, 1968.

Compared to the phase comparator shown on pages 76 to 79, output terminal X depends on whether the signal frequency applied to input terminal M or B is higher or lower than the signal frequency applied to the other input terminal. Yes.

Since one output of Y is completely fixed at the H level (a rectangular wave with an average level corresponding to the phase difference between the input signals appears at the other output terminal), for example, as shown in Figure 2. A charge pump circuit using complementary MOS transistors can be used to convert X and ! When the outputs appearing at the terminals are combined, the output terminal 2 in Fig. 2 is completely fixed at either L# or H depending on whether the frequency of the pulse signal being compared is higher or lower than the other. When a PLL is configured, there is an advantage that the cap charge range can be widened as much as possible to follow the voltage controlled oscillator (VCO).

Furthermore, since the circuit shown in Figure 1 is configured to perform edge trigger operation using the sequential operation of nine match gates, it has the characteristic that the input signal is not limited to a square wave with a duty of 60%. It also has

However, the phase and frequency comparator shown in FIG. 1 also has some drawbacks.

First, the phase comparison output and the frequency comparison output cannot be taken out independently.

For example, when configuring a PLL that includes a dynamic element such as a motor connected to an alternator in its loop (the motor, the alternator, and the drive circuit for the motor are (It can be regarded as a motor with a high degree of accuracy.) The inertia of the motor's rotor is particularly likely to cause out-of-sync phenomena such as overshoot and undershoot immediately after power is turned on, and particularly for motors that require highly precise control. A bidirectional servo drive circuit is used that drives the brake to decelerate the motor when an overshoot occurs, and accelerates the motor when an undershoot occurs. The output that appears at the output terminals X and Y of the circuit is either a rectangular wave or a fixed output of the H level, so the control signal for the bidirectional servo circuit (it is a switching signal for deceleration operation and acceleration operation, and is not used at times other than overshoot or undershoot). (Cyclic fluctuations cause problems.) However, when converting the system into an LSI, an increase in the number of smoothing capacitors will result in an increase in the number of IC terminals. This results in extremely unfavorable results such as deterioration of system reliability due to an increase in the number of parts.

In addition, the circuit shown in Figure 1 has a frequency discrimination function.
’ However, for example, The Be1l system
Technical Journal, March, 1
962.C, J I By, described on pages 559 to 602
Compared to the phase comparator that uses one set-reset flip-flop as shown in Figure 3 in Mr. Two-person NAND
It can be easily configured by a gate or a cross-coupling connection of two two-person NOR gates. ), and also has the disadvantage that the number of gates increases if an output is required that corresponds only to the phase difference between input signals.

The second drawback (this is an important problem that affects the accuracy and stability of the PLL) is that when the charge pump shown in Figure 2 is connected to the circuit shown in Figure 1, the signal frequency at input terminal B is When the signal frequency of the input terminal B is lower than the signal frequency of the terminal B, the output of the output terminal 2 is fixed at the L# level. A rectangular wave output with an average level lv (corresponding to the DC level when the signal is smoothed) is Z
furthermore, when the signal frequency of input terminal B becomes higher than the signal frequency of input terminal M, output terminal 2
The output of is fixed at -H# level μ. In other words, it is often thought that it is possible to obtain a 3-state output (there are some documents that actually explain this), but in reality, at least as long as it is used in an oven μm amplifier, the output from output terminal 2 is -・L. The problem is that only bias state outputs of .

That is, if the signal frequency fB of the input terminal B at point α on the frequency fB axis in FIG. 3 is lower than the signal frequency fB of the input terminal M, the level of the Y terminal in FIG.
- Since the drain side output of the P-channel enhancement type MO8) transistor 1 and the channel enhancement type MO8) transistor 2 constituting the input inverter in Fig. 2 are fixed at the L level, the steering gate circuit is The R channel enhancement type MO8) transistor s which constitutes the OF F state 1tc is fixed.

On the other hand, the X terminal, that is, the P-channel enhancement type MO8 transistor 4 constituting the steering gate circuit.
A rectangular wave signal is applied to the gate of , which depends on the phase relationship between the signal applied to the M terminal and the signal applied to the B terminal,
When the level of the X terminal becomes -L, the P-channel enhancement type MO8) transistor 4 is turned on, and the N-channel enhancement type MO8) transistor that constitutes the output gate circuit is turned on, that is, the level of the output terminal 2 is turned on. is set to ・L・, but the level of the X terminal is ・
H. and the P channel enhancement type MO
8) Even when the transistor 4 is in the OFF state, the drain of the N-channel enhancement type MO8) transistor 3 is fixed at high impedance, so that the drain of the transistor 3 remains in the gate region of the N-channel enhancement type MO8) transistor until then. Since the charge is not discharged and the N-channel enhancement type MO 8) range nuller 6 continues to be in the ON state, the level of the output terminal 2 is held at -L#.

When the signal frequency applied to input terminal B gradually increases and the output state of the circuit in Figure 1 is reversed at 11 points on the fm axis in Figure 3 (the phase and frequency comparator in Figure 1 The output state is the rising point of the signal applied to the other input terminal between the rising edge of the signal applied to the input terminal on the opposite side of the channel whose output was previously fixed at the H# level and the next rising edge. in two or more places~
It will be reversed when ), the level of the X terminal is fixed at -H, and this time the level of the X terminal is cyclically set to 1,
It begins to fluctuate from H to L.

When the level of the X terminal becomes L, the P-channel enhancement type MO8) transistor 1 turns on, the N-channel enhancement type MO8) transistor 3 turns on, and the N-channel enhancement type MO8) transistor transistor turns on. The charge accumulated in the gate region is discharged, and the P-channel enhancement type MOS transistor 6 constituting the output inverter is turned on to lower the level of the output terminal 2 to .L.
・Transition from ・H・.

Even if the signal level of the X terminal changes cyclically from -L to -H#, as long as the level of the X terminal is fixed at -H-, the level of the second terminal will continue to be fixed at -H. As already stated.

In other words, if fm is gradually increased starting from point α in Figure 3 and changed to point β, the average level ξ of the signals from the X terminal and the i terminal will be as shown by X and y in Figure 4 a. However, when fB reaches near 1, the composite output obtained by the charge bonding circuit in Figure 2 suddenly shifts from ・L# to ・H#, and from point α to β in Figure 3. It is not possible to extract an output that depends on the phase difference between the input signals during the path to the point.

Now, in Figure 3 or Figure 4, if fB once rose to point β gradually becomes lower, then fm
When becomes lower than f (more precisely, when there are two or more rising points of the signal of the terminal B in the interval from the rise of the signal of the terminal B to the next rising)
At f2, the output states of the X terminal and the X terminal are reversed,
As shown in Figure 4, the average level of the output signal from the X terminal exhibits sawtooth wave characteristics as shown by X, and the average level of the output signal from the Ru.

Therefore, at point f2 in FIG. 3, output terminal 2 in FIG.
The 0 level rapidly shifts from -H- to -L-, and even on the return trip from point β to point α, it is not possible to extract an output that depends on the phase difference between the input signals.

In other words, when the phase and frequency comparator of FIG. 1 and the charge pump circuit of FIG. 2 are connected, as long as the circuit is used in an open loop, it is impossible to extract an output that depends on the phase difference between input signals.

When a simple PLL as shown in FIG. 6 is constructed using a phase and frequency comparator and a charge pump circuit having such open-loop characteristics, the capacitance of the capacitor 7 constituting the low-pass filter can be reduced to zero. As shown in FIG. 1, it can be confirmed that the output signal waveform of the voltage controlled oscillator 8 includes a large jitter component having a frequency of one half of the fundamental frequency.

At this time, a phase error output having a frequency of one half of the fundamental frequency is obtained from the charge pump circuit 9, and its average output level moves on the γ line in FIG.

The pattern obtained when the rectangular wave output dependent on the phase difference between the input signals forms a closed loop, which cannot be obtained when used in an open loop, can be easily explained using FIG.

First, when the input frequency fm is at the γ1 point in FIG. ), f
l passes through fl and reaches the 12 point in Figure 4, causing the X terminal output to shift the Z terminal output to @H#.

When the two-terminal output becomes H-, the loop works to lower the output frequency of the voltage controlled oscillator 8, and when fm passes f2 and Cfm becomes lower than f2, the level of the X terminal changes again. become. ), return to point 11 in FIG. 4 1 again, and shift the 2-terminal output to ・L・ with the X terminal output.

Thereafter, since the same cycle is repeated, the frequency of the output signal of the voltage controlled oscillator 8 increases or decreases every cycle as shown in Figure 6. That is, it includes a jitter component with a frequency that is half the fundamental frequency.

This phenomenon cannot be avoided as long as a PLL is constructed using a phase and frequency comparator or a charge pump circuit whose open-loop output characteristics are as shown in Figure 3. Although it is possible to improve the degree of flatness by increasing the amount of capacitors constituting the filter or by changing the configuration of the low-pass filter to have a higher degree of specificity, problems with loop responsiveness and output signal Since the problems of the C/N ratio are in a conflicting relationship (if the C/N ratio is changed in the opposite direction, the responsiveness will deteriorate.

), many troubles were encountered when constructing a stable and highly accurate loop.

By the way, the phase and frequency comparator shown in FIG.
The charge pump shown in the figure can also be significantly improved in characteristics as far as the O7N ratio and responsiveness are concerned by only making slight modifications.

In other words, the cause of the worsening of the C/)f ratio of the output signal in the PLL shown in FIG. 5 is the output characteristic (FIG. 3) of the charge pump circuit 9. Therefore, as a charge pump circuit, for example, US Pat. 748,589, or the P-channel enhancement type MOS transistor 4 and N-channel enhancement type MO8 of the charge pump circuit shown in FIG. 2). By connecting resistors with the same resistance value between the drain and source of each of the Langinuta 3, it is possible to achieve the same result as shown in Fig. 4b of the paper by Mr. G111 or Fig. 4F of the above-mentioned Japanese Patent Publication No. 47-12923. The output characteristic (shown in Figure 7) can be obtained, or the X terminal of the phase and frequency comparator shown in Figure 1 or! By applying the output signal appearing at the terminal as it is to the low-pass filter,
In either case, when the capacitance of the capacitor 7 in FIG. 5 is brought close to zero, the output waveform becomes a waveform with very little jitter component, as shown in (2) in the same figure.

However, although the phase and frequency comparator with the output characteristics shown in FIG. 7 has a certain frequency discrimination function, the phase and frequency comparator with the ideal state output characteristics as shown in FIG. Compared to the above, problems such as deterioration of response characteristics and reduction of capture range when configuring a PLL remain.

By the way, F of US Patent No. 3,069,623
ig, 2 is a device that combines two set-reset flip-flops and two match gates to determine whether the frequency of one of the two input signals is higher or lower than the other. A circuit configuration as shown in FIG. 9 is disclosed.

When the input terminals M and B of the circuit shown in FIG.
gates 10, 11, mNll gates 12, 13, )fO
R game) 14.15 output signal waveform, and the leading edge (l) of the pulse signal applied to the input terminal
When there are two or more leading edges of the pulse signal applied to the input terminal B during the period from leading edge (leading edge) to the next leading edge, the ND gate 13 generates an output signal, and the NOR gate 16 outputs an output signal. The output level is set to ・L・, and as a result, the above N
The output level of the OR gate 14 shifts to wH#, and conversely, the leading edge of the pulse signal applied to the input terminal B changes between the leading edge of the pulse signal applied to the input terminal B and the next leading edge of the pulse signal applied to the input terminal B. exists at two or more locations, the ND gate 12 generates an output signal and causes the output level of the NOR gate 14 to be yvwo.L'-, so that the NOR' gate 1
6 output level or shifts to -H#.゛Therefore, depending on the output state of the bistable circuit configured by cross-coupling the input terminals and output terminals of the NOR gate 14 and the NOR gate 16, the voltage applied to the input terminal M and the input terminal B is It is possible to distinguish between high and low frequencies of pulse signals.

That is, if the frequency of the PALNU signal applied to the input terminal B becomes higher than the frequency of the pulse signal applied to the input terminal B, the output level of the NOR gate 14 becomes H; If the frequency of the pulse signal applied to the input terminal B becomes lower than the frequency of the pulse signal applied to the input terminal B, the NOR gate 16
The output level becomes @HM.

In other words, the circuit shown in FIG. 9 is an N circuit in which the input terminal and the output terminal are cross-coupled to each other.

The set terminal of the set-reset flip-flop (bistable circuit) by R gate 1o and NOR gate 11 is the first
A muND gate (coincidence gate) is connected to the input line a of the NOR gate 11, its tasset terminal is connected to the second input line S, and its input terminal is connected to the first input line a and the output terminal of the NOR gate 11. ) 12 is connected to the set terminal of the NOR gate 14 and the set-reset flip-flop formed by NOR gate 1 and 6, and the input terminal is connected to the second input line and the NOR
An output terminal of a second frequency detection means formed by an AND gate (coincidence gate) 13 connected to the output terminal of the gate 10 is connected to a reset terminal of a set-reset flip-flop formed by the NOR gate 14 and the NOR gate 16. While one pulse signal is applied alternately to the input line a or the input line A, all the pulse signals become valid pulses, and the pulse signals are inverted at an inversion period corresponding to the distribution period. If the inversion operation is repeated, but the frequency of the pulse signal applied to one input line becomes higher than the other, there will be a thicket, that is, between the leading edge of the pulse signal applied to the other input line and the next leading edge. When there are two or more leading edges of a pulse signal applied to one input line, the second and subsequent pulse signals can invert the output states of the flip-flops formed by the NOR gate 10 and the NOR gate 11. Therefore, at the leading edge of the pulse, the input terminals of the AND gate 12 or the MND gate 13 both become H, and an output signal is generated. The output state of the flip-flop by 16 is determined.

By the way, the above-mentioned operation occurs when the pulse width of the pulse signal applied to the input terminals 100 and B is extremely short (however, if it is too short, each gate will not respond at all).
It is carried out only in

To explain this situation using FIG. 10, in advance, the output levels of NOR game) 10,1.
OR game) 11. When a positive pulse signal is applied to the input terminal while the output level of 14 is -L, the above-mentioned NOR game)
While the level of one input terminal of 10 becomes ・H・, 1
The output level is delayed by the signal transmission time of one gate.
Then, with a further delay of one gate, the output level of the NOR gate 11 becomes @H#.

By the time the output level of the NOR gate 11 shifts to mHn, the pulse at the input terminal M has disappeared. In other words, if the trailing edge of the pulse signal applied to the input terminal has passed, the output level of the ANDNO gate will not reach H-, but as shown by the broken line in FIG. so that the NOR
If the level of the input terminal M remains unstable when the output level of the gate 11 shifts to ・H, the output level of the ND gate 12 becomes ・H with a delay of one gate.
·become.

At this point, the output level of the NOR gate 14 is already
Since it is L#, the above NOR game')14 and NO
Although the output state of the flip-flop by the R gate) 15 is not inverted, next, a pulse signal is applied to the input terminal B, and the output level of the previous fdNOR gate 1o becomes ・H#
When returning to , if the level of the input terminal B remains at -H# as shown by the broken line in FIG. 10B, the output level of the ND gate 13 reaches Ivf)
becomes H-, and the output rep of the ND gate 13 becomes H-.
When it becomes ., the output level of the NOR gate 15 becomes .L. with a delay of one gate as shown in FIG. 10, 14.15, and as a result, the output level of the NOR gate 14 becomes .H.

Thereafter, each time a valid pulse is applied to the input terminals M and B, the flip 70 knobs formed by the NOR gate 14 and the NOR gate 16 repeat the inversion operation, so that the NOR
It becomes impossible to determine whether the frequency of the input pulse signal is high or low based on the output state of the flip-flop formed by the R gate 14 and the NOR gate 16.

As can be seen from FIG. 10, the circuit shown in FIG. 9 operates normally. In other words, in order to operate as a frequency discrimination circuit, the pulse width of the pulse signal applied to the input terminals M and B (width to the leading edge color 11111 trailing edge) must be greater than the width corresponding to the delay time of 2 gates. It needs to be narrowed.

No. 3,069, 132:3! ′:j′
In special cases, the pulse signals in Figure 10 and B are created using a differentiating circuit, but the pulse signals for two gates are created using a general differentiating circuit (for example, a differentiating circuit using a capacitor and a resistor). It is difficult to obtain a pulse width shorter than the width equivalent to the delay time, and if it is made too short, problems such as not having enough power to drive each gate will occur, especially when converting the system to an LSI. If the pulse width of the input signal becomes even slightly wider, it will cause a malfunction, so it is not recommended to use the circuit shown in Figure 9 as is from the point of view of reliability. I also don't like it.

However, in the circuit shown in FIG. 9, the flip-flops formed by NOR gate 1o and NOR gate 11 are exactly the phase comparators seen in the above-mentioned Byrne paper, and when the circuit operates normally, 1OR gate 1
4 and a NOR gate 15, a frequency comparison output of the input signal is obtained. In other words, from the output terminals C and D in FIG.
Since the frequency comparison output signal of the input pulse signal can be obtained from the input pulse signal, the phase comparison output signal and the frequency comparison output signal can be taken out independently with a simpler configuration than the phase and frequency comparator shown in Fig. 1. It has the characteristic that it can be done.

The present invention provides a frequency comparator comprising a frequency detection means and a frequency discrimination means, in which the frequency of a pulse signal applied to at least one input terminal of the frequency discrimination means is set to the frequency of a pulse signal applied to the other input terminal. A frequency comparator or a phase and frequency comparator that can obtain an ideal three-state output by generating output signals corresponding to three stages: lower than, higher than, and equal to. It is in.

FIG. 11 shows a logical configuration diagram of a frequency comparator constructed in connection with the present invention. In FIG. 11, input terminals 101L and 111L and output terminals 100 and 110 are cross-coupled to each other. A first bistable circuit 16 with a configured NOR gate 10 and a NOR gate 11
, one input terminal 121L is connected to the first input line a, and the other input terminal 12b is connected to the first bistable circuit 1.
6, one input terminal 131L is connected to the second input line S, and the other input terminal 13b is connected to the output terminal 110 of the first bistable circuit 1.
A second ANDNO gate connected to the output terminal 100 of 6, the input terminals 141L, 151L and the output terminal 140
, 150 are carefully cross-coupled to each other.
The reset terminal 15b is connected to the output terminal 120 of No.2.
is connected to the output terminal 130 of the ND gate 13, which is exactly the same as in FIG. 9, but in FIG. A delay means using a NOR gate 21 is added.

In other words, the cent terminal 18b of the third bistable circuit 22 including the NOR gate 18 and the NOR gate 19 configured by cross-coupling the input terminals 181L and 191L and the output terminals 1.80 and 190 is connected to the input line a.
The reset terminal 19b is connected to the input line S, and the output terminal 180 of the third bistable circuit 22,
190 are input terminals 2o& of NOR gates 20 and 21, respectively.

211L is connected to the input line a, the input terminal 20b of the NOR gate 20 is connected to the input line a, the input terminal 21b of the NOR gate 21 is connected to the input line a, and the third input terminal 200,
210 are connected to the output terminals 100, 110 of the first bistable circuit 16, respectively, the output terminal 2δd of the NOR gate j20 is connected to the set terminal 10b of the first bistable circuit 16, and the NOR gate 21 output terminal 21 (1 is the reset terminal 1 of the first bistable circuit 16
1b.

Now, in such a logical configuration, the input terminals M and B,
NOR game) 18, 19, 20, 21.

10.11. MMD game) 12, 13.1fOR game)
14. , 15, the third bistable circuit 22 and the NOR game)
20. The operation of the delay means constructed by 21 will be mainly explained.

First, the output levels of NOR gates 18 and 10 are @H, and the output level of NOR gates 19 and 11 is ・L.
, when a PALNU signal as shown in FIG. 12 is applied to the input terminal M, the NOR gate 18 is activated at the leading edge of the first pulse.
Since the level of the input terminal 18b of the NOR gate 18 becomes ・H#, the output level of the NOR gate 18 becomes ・L・ with a delay of one gate.
, and after a delay of one gate, the NOR gate 1
The output level of 9 shifts to ・H#.

At this time, one of the input terminals of the NOR gates 20 and 21 is at the H- level, so its output level is L, and the ND gates 12 and 13 also have either of their input terminals at the H- level. Since it is at L level, its output level is L.

When the level of the input line a shifts to -L- at the trailing edge of the pulse signal applied to the input terminal 20, the level of all the input terminals of the NOR gate 20 becomes -L, and the 1-game (The NOR game was delayed by a minute)
The output level of 20 shifts to =.H.

As a result, the output level of the NOR gate 10 shifts to -L with a delay of one gate, and the output level of the NOR gate 11 shifts to -H with a delay of one gate.

When the output level of the NOR gate 11 shifts to -(,), the output level of the NOR gate 2o returns to -L with a delay of one gate.

Next, when a pulse signal as shown in FIG. 12B is applied to the input terminal B, the level of the input line becomes H at the leading edge of the first pulse, and after a delay of one gate, the NOR The output level of the gate 19 shifts to .L., and after a delay of one gate, the output level of the NOR gate 18 shifts to @H#.

When the level of the input line S shifts to -L# at the trailing edge of the pulse signal applied to the input terminal B, the V level of all input terminals of the NOR gate 21 becomes -
The output level of the NOR gate 21 shifts to IIH. with a delay of one gate.

As a result, the output level of the NOR gate 11 shifts to L with a delay of one gate, and then shifts to L with a delay of one gate.
Move to output bay y75E2H of gate 10.

When the output level of the NOR gate 1o shifts to @H, the output level of the NOR gate 21 returns to -L- again with a delay of one gate.

Thereafter, in exactly the same way, when effective pulses capable of inverting the output state of the first bistable circuit 16 or the third bistable circuit 22 are alternately applied to the input terminals M and B, the distribution period In order to repeat the inversion operation at an inversion period corresponding to When the frequency becomes higher than the frequency of the pulse signal applied to the input terminal of the first bistable circuit 16, and an invalid pulse as shown in FIG. and the output state of the second ice stabilizing circuit 22 is not inverted;
At the leading edge of the invalid pulse, the m
Since the input level of the D gate 12 or the ND gate 13 becomes II HIf, the input level of the ND gate 13 is delayed by one gate.
The D gate 12 or the ND gate 13 generates an output signal as shown in FIG. 12 or 13.

Note that even if a pulse signal with a wide pulse width as shown in FIG. 12 is applied to the input terminal M or B of the circuit in FIG. operation, the first bistable circuit 16 performs an inversion operation at the trailing edge of the pulse signal, and the module N constituting the frequency detection means
Since the D gate 12 and the ND gate 13 are connected to generate an output signal at the leading edge of the invalid pulse after the inversion operation of the first bistable circuit is completed, the reliability of operation is logical. guaranteed.

Note that the frequency comparator shown in FIG.
．． A phase comparison output signal as shown in Fig. 19 and 10.11 is obtained, and a frequency comparison signal (DC level Iv) is obtained from the output terminal of the second bistable circuit. Compared to a frequency comparator, it has the feature that the phase comparison output and the frequency comparison output can be taken out independently, but the phase comparison output terminal 0. By connecting a synthesis circuit as shown in Fig. 13 to D and frequency comparison output terminals R and F, the output terminals X and Y obtain exactly the same signals as the output terminals X and Y of the circuit shown in Fig. 1. You can also do that.

In addition, in FIG. 11, the output terminal ' of the third bistable circuit 22
180 and 190 are phase comparison output terminals and CKJ&'
However, as shown in FIG. 14, the output terminals 100, 110 of the first bistable circuit 16 may be connected to the phase comparison output terminals RI and C.

Now, FIG. 16 also shows a logical configuration diagram of another frequency comparator constructed in connection with the present invention, in which the input terminal 231
A first bistable circuit 26 is constituted by a NOR gate 23 and a NOR gate 24 whose output terminals 23d and 24d are cross-coupled to each other, and an input terminal 23b of the NOR gate 23 is a first input terminal. The line is already connected to the input terminal 24b of the NOR gate 24.
is connected to the second input line 26a, and one input terminal 26a
is connected to the second input line 1, and the other input terminal 26
b is connected to the output terminal 24d of the first bistable circuit 26, and the output terminal 260 of the OR gate 26 is connected to the input terminal 23Q of the NOR gate 23, one input terminal 2.
7& is connected to the first input line a, and the other input terminal 2
7b is connected to the output terminal 23d of the first bistable circuit 26, and the output terminal 270 of the OR gate 27 is connected to the NO
It is connected to the input terminal 240 of the R gate 24 to constitute a delay means.

FIG. 16 shows a signal waveform diagram of each part in FIG.
, , the output level of the NOR gates 24 and 15 is H. When a pulse signal as shown in FIG. 16 is applied to the input terminal M, the input of the OR gate 27 is Since the level of the terminal 271L becomes ・H, the above-mentioned OR gate 2 is delayed by one gate.
7's output level shifts to ・H-.

When the output level of the OR gate 27 shifts to -HII, the output level of the NOR gate 24 shifts to -L with a delay of one gate, and the output level of the OR gate 26 shifts to -L with a delay of one gate. moves from @HII to ・L・.

At this point, the parnu of the input terminal has disappeared.

That is, if the level of the input terminal M returns to -L II, the output level of the NOR gate 23 shifts to @L# with a delay of one gate after the output level of the OR gate 26 shifts to -L#. However, as shown in FIG. 10, the pulse width of the input pulse signal is wide, and immediately after the output level of the OR gate 26 shifts from・If it is,
The output level of the NOR gate 23 remains at L-.

At the trailing edge of the pulse applied to the input terminal, when the level shifts to -L#, the level at the input terminal 240 of the NOR gate 24 changes to -L# via the OR gate 27 faster than the level at the input terminal 240 becomes -L. Since the level of the input terminal 23b of the NOR gate 23 becomes to L, the output level of the NOR gate 23 quickly shifts to -H, and the output level of the NOR gate 24 remains at -L#. -Similarly, when a pulse is applied to input terminal B, at the leading edge of the knee, OR
The output level of the gate 26 shifts to a l (n, and as a result, the output level of the NOR game) 2g becomes @L, and then the output level of the OR gate 27 becomes -L.

NOR Gate 2 at Trailing Edge
4's output level shifts to ・H・.

While repeating this operation (while one pulse is applied alternately to input terminals M and B), as can be seen from Figure 16, the output of 12.13 The voltage level is @L#, but when an invalid pulse such as 82 in FIG. 16B is applied to the input terminal B, for example,
At the leading edge, the Mund Gate 1
The levels of output terminals 131L and 13b of 3 are both @
Since the output level becomes H#, the output level shifts to ・H. However, as the level of the input terminal B becomes ・H..., the output level of the NOR gate 24 shifts to L#, so the output level of the input terminal B becomes ・H. The period during which the output level of the ND gate 13 is .H. is a period corresponding to the signal transmission delay time of the NOR gate 24.

When an invalid pulse as shown in FIG. 16, M2 is applied to the input terminal M, the output level of the MND gate 12 shifts to H for a very short period.

Due to the invalid pulse B2 applied to the input terminal B, the
When the output level of gate 13 shifts to Hyr,
As shown in FIG. 14.15, first, the output level of the NOR gate 16 shifts to -L- with a delay of one gate, and then the output level of the NOR gate 14 shifts to -H. - Further, when the output level of the ND gate 12 shifts to ・H due to the invalid pulse 2 applied to the input terminal MU, the output level of the NOR gate 14 shifts to @L#, and then the output level of the NOR gate 14 shifts to @L#, and then the output level of the NOR gate 14 shifts to ) 15 output level -・H・
to move to.

The circuit of FIG. 16, like the circuit of FIG. 11, also includes delay means for completing the inversion operation of the first bistable circuit 26 after the trailing edge of the valid pulse applied to the input terminal M or B. Therefore, the reliability of the operation of the frequency detecting means for determining the frequency of the input signal is logically guaranteed.

By the way, if you look at Figure 16, you will see that OR gate 2 in Figure 15
It can be seen that the output signal waveform of OR gate 27 also depends on the phase difference between the pulse signals applied to input terminals M and B. Naturally, as shown in FIG. It is also possible to take out a comparison output signal.

Note that the frequency comparator shown in FIG. 11 or 15 may be used as a phase comparator alone without adding a charge pump circuit or a circuit for synthesizing the phase comparison output signal and the frequency comparison output signal. It is possible to achieve the same function as the device in which the phase and frequency comparator shown in FIG. 1 is connected to the charge pump circuit shown in FIG. 2.

For example, if the PLL shown in FIG. 6 is configured using the frequency comparator shown in FIG. 11 or FIG.
The terminals are shown in Figure 11 or Figure 16! Connect to the terminal.

), it can be confirmed that the operation of the loop is exactly the same as when using the phase and frequency comparator of FIG. 1 and the charge pump circuit of FIG. 2.

The frequency comparator in Figure 11 or Figure 16 can be used as is.
As can be seen from FIG. 12 or FIG. 16, it can be used as a phase and frequency comparator in LL when the signal frequency applied to one input terminal is 4th.
6 This is because when the pulse signal alternately increases and decreases as shown in Figure 1, a rectangular wave output is obtained from the output terminal E or F depending on the phase relationship of the pulse signal applied to the input terminals M and B. be.

Furthermore, if the phase comparison output and frequency comparison output of the frequency comparator shown in FIG. 11 or 16 are combined using a simple resistance combining circuit as shown in FIG. Exactly the same output characteristics as when the charge pump circuits shown in the figure are connected can be obtained.

In this way, the frequency comparator shown in FIG. 11 or FIG. 15 (the same applies to FIGS. 14 and 17), FIGS. 6th
It has a much simpler configuration than the circuit shown in the figure, and not only can it perform the same function, but also the phase comparison output and frequency comparison output can be taken out independently. By making the configuration more complex, even more functionality can be achieved.

Now, in an embodiment of the present invention, the leading edge of the pulse signal applied to the first input line is set at two or more points between the leading edge of the pulse signal applied to the second input line and the leading edge of the pulse signal applied to the first input line. a first frequency detection means that generates an output signal when the first frequency detection means is present;
An output signal is generated when there are two or more leading edges of the pulse signal applied to the second input line between one leading edge of the PALNU signal applied to the input line of the second input line and the next leading edge of the PALNU signal applied to the input line of In the device comprising a second frequency detecting means, at least two bistable circuits are operated by the output signals from the first and second frequency detecting means, and the second frequency detecting means operates according to the output state of the bistable circuit. The frequency of the pulse signal applied to the first input line is lower than or higher than the frequency of the PALNU signal applied to the first input line.

FIG. 19 is a logical configuration diagram of a phase and frequency comparator constructed based on the present invention, which includes a first bistable circuit set by the output signal of the tenth frequency detection means, and a second bistable circuit set by the output signal of the tenth frequency detection means. When the second bistable circuit set by the output signal of the frequency detection means and the first and second bistable circuits are both in the set state, the first and second bistable circuits are set. It has a reset means for resetting.

In FIG. 19, a bistable circuit 1'6 consisting of a NOR gate 10 and a NOR gate 11 has a first input line a and a second input line a.
The D flip-flop 28 and the D flip-flop 29 constitute a first and second bistable circuit. The bistable circuit 16 and the D
The D terminal D1 of the flip-flop 28 and the clock terminal C1 constitute the first frequency detection means, and the D terminal D of the bistable circuit 16 and the D flip-flop 29 constitute the first frequency detection means.
2 and the clock terminal C2 constitute the second frequency detection means, and the reset gate formed by the mul ID gate 30 constitutes the reset means.

Now, when a pulse signal as shown in FIG. 20 M and B is applied to the input terminal M and B of the phase and frequency comparator shown in FIG. Q1. Output terminal Q2゜ND gate 30 of D flip-flop 29. NOR gate 31. The output signal waveforms of the ND gate 32 and NOR gate 33 are shown in 10.11.2B and 29 in FIG. 20, respectively.
, 30° 31, 32, 33. First, the frequency of the pulse signal applied to the input terminal B is changed with the output level of the D flip-flop 28, 29 set to ・L・becomes lower and the number 3 in Figure 20 is lowered.
When an invalid pulse as shown in the figure appears, the level of the D terminal D1 of the D flip-flop 28 and the output level y of the NOR gate 11 are clearly H. The output level is set to @H#.

The D flip-flop 28 is set and the output terminal Q
Since the level of the set terminal S1 of the D flip-flop 28 becomes H at the same time as the level of the D flip-flop 28 becomes H, the clock terminal C1 of the D flip-flop 2B becomes
Even if a pulse signal is applied to the D flip-flop 2
The output state of 8 is never reversed.

Next, as the frequency of the pulse signal applied to the input terminal B increases (or as the frequency of the pulse signal applied to the input terminal B decreases), an invalid state as shown by B5 in B in FIG. 20 occurs. When the pulse is generated, the output level of the D-two flip-flop 29 is set to H, but when the output level 75f of the D flip-flop 29 shifts to H, the input terminal 301L of the ND game) 30, 3
Both the levels of 0b become 41 H., the output level of the ND gate 3o shifts to -H., and both the D flip-flops 28 and 29 are reset.

(The output terminal -300 of the ANDNO gate is connected to the reset terminals R1 and R2 of the D Friso flip flop 28.29.) The frequency of the pulse signal applied to the input terminal B becomes higher and reaches B4 in FIG. 20B. When the indicated invalid pulse occurs, the output level of the P flip-flop 29 is set to at Hn again, but this time the output level of the D flip-flop 28 is set to L.
The D flip-flop 290 set state is maintained until an invalid pulse occurs at the input terminal.

On the other hand, the output level of the NOR gate 31 becomes 2H level only when the frequencies of the palme signals applied to the input terminals M and B become completely equal (the signal waveform shown in Fig. 20 is an explanation of the operation). In order to make it easier to understand, the following example shows a case where the frequency of the pulse signals applied to the input terminals M and B suddenly changes, so even if the frequencies are not equal, the output level of the NOR gate 31 will be It appears to be ・H, but in reality, if there is even a slight difference in frequency, invalid pulses are generated continuously, so the output level of the NOR gate 31 is always ・L.) At this time, the rectangular wave output signal from the phase difference detection means by the bistable circuit 16 is transmitted to the ND gate 32.
The signal is applied to one input terminal 33a of the NOR gate 33 through the signal.

Since the other input terminal 33b of the NOR gate 33 is connected to the output terminal Q1 of the D flip-flop 28, the output signal appearing at the output terminal 330 of the NOR gate 33, that is, the signal at the output terminal 2 is as shown in FIG. As shown in 33, when the frequency of the pulse signal applied to input terminal B is lower than the frequency of the pulse signal applied to input terminal B, L, - level is constant, and when they become the same, both signals A square wave signal appears that depends on the phase difference of
When it gets high, the H level remains constant.

Therefore, according to the phase and frequency comparator shown in FIG. 21, the ideal 3-nutate output characteristics as shown in FIG. 8 can be obtained.

Of course, D flip-flops 28 and 2 in FIG.
It goes without saying that if a reset circuit is provided so that 9 can be reset by external operation (manual operation), it will operate as a phase comparator that can control the frequency even when used in an open loop.

In FIG. 19, the ND gate 32 and the NOR gate 33 constitute a synthesizing means for synthesizing the phase comparison output and the frequency comparison output, but in the case of FIG. It is used as a sum gate, and the N
The OR gate 33 is also used as a negative logic AND gate.

Now, FIG. 21 shows another logical configuration of a phase and frequency comparator that performs the same operation as FIG.
NI) First bistable circuit 36 with gate 34 and NARD gate 36, NARD gate 37 and NARD gate 3
The second bistable circuit 39 by 8, the reset gate (reset means) by 4 manual NANI) gate 40, the synthesis means by OR gate 41 and ND gate 42 are constructed according to the present invention, and the IIAND gate 43 and NARD gate A third bistable circuit 46 based on 44 and a fourth bistable circuit 48 based on a NARD gate 46 and a common ND gate 47.
, the fourth bistable circuit 48 and the three-person HAND gate 4
9 and a delay means by a three-way ND gate 60, the third bistable circuit 46. and the delay means and the OR gate 51
the third bistable circuit 4;
6, the delay means, and the second frequency detection means including the OR gate 62 are all constructed based on FIG.

The first frequency detection means and second frequency detection means in FIG. 21 have exactly the same configuration as the first frequency detection means and second frequency detection means in FIG. 11, and one has a positive logic configuration. In contrast, the other has a negative logic configuration.

In addition, in FIG. 21, HAND gate 34, HAND gate 36, HAND gate 37, NARD gate 38
．． The circuit configuration of the 4-man power NAND gate 40 consists of four 2-man power HAND gates and one 4-man power HA in FIG.
The circuit configuration is exactly the same as the circuit configuration using ND gates, but in Figure 1, these six NAND gates detect the phase difference and the high/low frequency of the pulse signals that are applied alternately to the two input terminals. On the other hand, in FIG. 21, these operating functions are carried out by separately provided phase difference detection means and first and second frequency detection means, and the circuit is composed of six NAND gates. corresponds to three stages in which the frequency of the pulse signal applied to one input terminal is lower than, higher than, or equal to the other, based on the output signals from the first and second frequency detection means. It constitutes a discrimination circuit that generates a DC output, and the output levels of the six HAND gates do not change except during transitions when the frequency of the input pulse signal suddenly changes.

Now, Fig. 2 shows a signal waveform diagram of each part of the frequency discrimination circuit and synthesis circuit of Fig. 21, in which the OR gate 51 constitutes the first frequency detection means and the second frequency detection means constitutes the signal waveform diagram. FIG. 22 51 from the OR gate 62, respectively.
．． When a signal waveform as shown in 52 is applied, HAN
D gate 34, NAND gate 36, HAND gate 3
7. The output signal waveforms of the NAND gate 38 and HAND gate 4o are shown in FIG. 22, 34, 35, 37, and 3, respectively.
8.

It will be like 40.

That is, the output level of the HAND gate 34.37 is set to @L H1 the NAND gate 35.38
First, with the output level of ・H#,
When a negative direction pulse is applied to the output line C of the frequency detection means (this state occurs when the frequency of the pulse signal applied to the input terminal B becomes higher than the frequency of the pulse signal applied to the input terminal B). ), at its leading edge, the output level of the WAND gate 34 shifts to -H#, and then the output level of the Nmu HD gate 36 shifts to -L#.

Even if a pulse signal is further applied to the output line C, the output level of the HAND gate 34, 35, 37, 38, 40 does not change at all, but the frequency of the pulse signal applied to the input terminal M is low. , so that when a negative direction pulse as shown in FIG. 22 is applied to the output line d of the second frequency detection means, the output level of the HAND gate 37 becomes .H- at its leading edge. Then, the output level of the HAND gate 38 shifts to L#.

Since the level of all input terminals of the NAND gate 40 becomes H- at the trailing edge of the PALNU applied to the output line d, the HA)in gate 40
The output level of shifts to M L jl, and the bistable circuit 36
And after 39 is reset, it returns to .H. (point 1 in FIG. 22).

When the frequency of the pulse signal applied to the input terminal C becomes high again and the pulse shown in FIG. 22 is applied to the output line C, the NAND gate 34 shifts to H again, and then The output level of 36 becomes @L#.

Subsequently, when the frequency of the pulse signal applied to the input terminal M becomes low and the pulse shown in FIG. 22C is applied to the output line d, the output level of the HAND gate 37 becomes .H.
Then, the output level of the HAND gate 38 becomes -
However, since the reset gate by the HAND gate 40 generates a reset pulse, the bistable circuit 36
and 39 are reset.

If the M+ wave number of the pulse signal applied to the input terminal B is even slightly lower than the frequency of the pulse signal applied to the input terminal B, C' in FIG.

Negative direction pulses are applied to the output line d one after another like d, e, and f, but when the pulse shown in d in FIG. 22 is applied, the output level of the HAND gate 37 reaches ・H#. Then, the output level of the NARD gate 38 becomes ・L・
This state remains unchanged unless a pulse is applied to the output line C.

To summarize the above operation, when the frequency of the pulse signal applied to the input terminal B becomes higher than the frequency of the pulse signal applied to the input terminal B, the OR gate 61 constituting the first frequency detection means continuously It is a HAND gate because it generates a pulse in the negative direction.

The output level of 34 is fixed to H#, and on the other hand, when the frequency of the pulse signal applied to the input terminal B becomes lower than the frequency of the pulse signal applied to the input terminal B, the second frequency detection means is configured. Since the OR gate 62 continuously generates negative pulses, the output level of the HA) iD gate 37 is fixed at @H#1, and in these transition regions, the first and second frequency detection means When the pulse signal is no longer supplied from the input terminal B, that is, when the frequencies of the pulse signals applied to the input terminals M and B become completely equal, the output levels of the NARD gate 34 and the NARD gate 37 both become ・L・Fixed.

Therefore, one input terminal 41! L is connected to the output terminal 460 of a phase difference detection means constituted by a bistable circuit 48 made up of a WAND gate 46 and a NANI) gate 47, and the other input terminal 41b is connected to the output terminal 340 of the first bistable circuit 36. A positive logic OR gate formed by the OR gate 41 and one input terminal 42! L is the above O
A combination composed of a positive logic AND gate using a N...D gate 42 connected to the output terminal 410 of the R gate 41 and whose other input terminal 42b is connected to the output terminal 380 of the second bistable circuit. The output terminal 2 of the means has a 22nd
As shown in FIG. 42, the pulse applied to the input terminal -
When the frequency of the signal becomes the same as the frequency of the pulse signal applied to input terminal B, a rectangular wave signal that depends on the phase difference between the two signals appears, and the frequency of the signal becomes higher than the frequency of the pulse signal applied to input terminal B. When the frequency becomes high, an H level output appears, and when the frequency becomes lower than the frequency of the pulse signal applied to input terminal B, an L level output appears.

In the circuit shown in FIG. 21, the first bistable circuit 36
Alternatively, when a set pulse is applied to the second bistable circuit 39, the WAND
Although the gate 40 is configured to generate a reset pulse, in order to simplify the configuration, the output terminals of the first bistable circuit and the second bistable circuit are connected as shown in Fig. 2-3. The reset means may be constituted by a two-man HAND gate (or a two-man OR gate) connected to the two-man HAND gate (or two-man OR gate).

However, from the standpoint of reliability of circuit operation, the reset means shown in FIG. 21, which operates sequentially, is preferable.

Now, FIG. 24 shows a combination of the first frequency detection means and second frequency detection means shown in FIG. 16, and the phase difference detection means, with the frequency discrimination means and synthesis means shown in FIG. , 7<sofa amplifier 53.54 is the first
6 is used as a delay means to widen the pulse width of the output PULLN shown in FIG. 12 or FIG. 16 and FIG. 13.

21, 23, and 24 are all configured as phase and frequency comparators, but the first and second
By suitably combining the output signals of the two bistable circuits, a frequency comparator that can obtain three-stage comparison outputs can be constructed.

For example, in the frequency comparator shown in FIG. 26, the level of the output terminal G becomes H only when the frequencies of the pulse signals applied to the input terminals M and B become equal, and the level of the pulse signal applied to the input terminal M becomes H. Only when the frequency of the pulse signal applied to input terminal B becomes higher than the frequency of the pulse signal applied to input terminal B, an H label is generated.

Furthermore, as explained earlier, the conventional phase and frequency comparator shown in FIG.
For example, the first frequency detection means and the second frequency detection means can be omitted from the circuit of FIG. 26, and the output lines C and d can be connected to the output lines X and ! of the circuit of FIG. The frequency comparator of the present invention can be constructed by connecting the terminals, and the phase and frequency comparator of the present invention can be constructed by extracting the phase difference detection signal from the circuit of FIG. 1 using an appropriate matching gate. It can also be configured.

It should be noted that the frequency comparator or phase and frequency comparator of the present invention shown above are all AND, OR, and NOR in their specific implementation configuration diagrams.

Although logic gates such as HAND are used, the use is not necessarily limited to these logic gates, and any circuit that is most rational in configuring the system or LSI may be configured.

Figures 26 and 27 both show examples in which the phase and frequency comparator of the present invention is constructed using IIL elements (or multi-output inverter logic). (The source is omitted.)
In FIG. 26, the first IIL element 96. Second II
L element 96, third I engineering L element 97, fourth
III.

Element 9B, 5th III, element 99, 6th
10-0. 7th IIL
The phase difference detection means based on FIG. 11 and the first and second The frequency detection means is configured,
11th IIL element 105, 12th OI ILx
V) N) 106, 13th (7) IIL element 10
7, 14th IIL element 10B, 15th (DI
IL engineering V) 1) 109, 16th IIL element 11o, 17th IIL element 111, 18th I
The IL element 112 constitutes frequency discrimination means and synthesis means based on FIG.

Similarly, in FIG. 27, the eight IIL elements at the front stage are used to detect the phase difference detection means based on FIG.
The eight IIL elements in the latter stage constitute frequency discrimination means and synthesis means based on FIG. 21.

By the way, Fig. 11, Fig. 14, Fig. 16, Fig. 17,
Fig. 19, Fig. 21, Fig. 23, Fig. 24, Fig. 26,
The phase and frequency comparators shown in Figures 26 and 27 all use a pulse signal with a narrow pulse width as an input signal, that is, the length from the leading edge to the trailing edge of the pulse waveform is sufficient compared to its repetition period. Requires a short pulse signal.

When the pulse width of the input pulse signal becomes too wide, although these phase and frequency comparators do not malfunction like the frequency comparator shown in FIG. 9, the error in the phase comparison output increases. (For example, if the pulse width of the input pulse signal occupies 10% of the repetition period, the phase detection error will also become 10%.) Therefore, applying a square wave with a duty of 60% as the input signal is Undesirable.

However, this level of restriction is not a big problem.

This is because, for example, as in the frequency comparator shown in Figure 9, if the pulse width of the input signal exceeds the width equivalent to the delay time of two gates, the circuit will malfunction, which could be fatal. Although this can be a major drawback, these phase and frequency comparators do not have very strict constraints and can easily convert a square wave to a differential waveform if there are no severe constraints on the pulse width.

For example, FIG. 28 is an example of a circuit that converts a pulse waveform of any duty cycle into a differential The wave is converted into a differential wave and appears at the terminal.

Moreover, FIG. 29 shows a similar differential wave generation circuit with four IILs.
This shows an example composed of elements. (29th
In the figure, the injector as a current source is omitted. ) Furthermore, in a PLL frequency synthesizer, etc., the output of a crystal oscillator is applied to a divider, while the output of a voltage controlled oscillator (VCO) is applied to a programmable frequency divider, and then the output signal of the frequency divider and the programmer amplifier are applied. The output signal of the 7-channel frequency divider is applied to the input terminal of the phase comparator,
As the output signal of the programmable frequency divider, a differential waveform is easier to extract (the reset signal or preset signal of the programmable frequency divider has a differential waveform).The frequency divider may also have a configuration as shown in FIG. 30, for example. By setting the output terminals P, Q, and R of each stage.

A differential output is obtained from S (output terminal, M.

A square wave output is obtained from N and O. ), there is no problem with the constraint that it is necessary to narrow the parnu width of the input signal.

As described above, the frequency comparator or the phase and frequency comparator according to the present invention includes the first and second bistable circuits set by the output signal from the frequency detection means, and therefore has a simple circuit. With this configuration, it is possible to obtain output signals corresponding to three stages when the frequency of one of two systems of pulse signals applied to the input line is lower, higher, or equal than the other, and in particular, based on the present invention. The phase and frequency comparator has great effects, such as being able to obtain an ideal three-state output with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a logic configuration diagram showing an example of a conventional phase and frequency comparator, Fig. 2 is a circuit connection diagram showing an example of a charge pump circuit used in conjunction with the circuit in Fig. 1, and Fig. 1
Output characteristics diagram when the circuit shown in the figure and the circuit shown in Fig. 2 are used together,
FIG. 4 is an output characteristic diagram to explain the operation of the circuit in FIG. 1, and FIG. 6 is a block diagram showing an example of a simple PLL.
Figure 6 is a circuit connection diagram showing another example of a charge pump circuit, Figure 7 is an output characteristic diagram when the circuit in Figure 6 is used in combination with the circuit in Figure 1, and Figure 8 is an ideal diagram. Output characteristic diagram of the phase and frequency comparator. Figure 9 is a logical configuration diagram showing an example of a conventional frequency comparator. Figures 1 and 0 are signal waveform diagrams of each part of the circuit in Figure 9. Figure 11. is a logical configuration diagram of a frequency comparator or a phase and frequency comparator related to the present invention, FIG. 12 is a signal waveform diagram of each part of the circuit of FIG. 11, and FIG. 13 is a phase comparison output of the circuit of FIG. 11. A logic block diagram of a synthesis circuit for synthesizing a signal and a frequency comparison output signal, FIG. 14 is another logic block diagram of a frequency comparator or a phase and frequency comparator related to the present invention, and FIG. 15 is a logic block diagram of a synthesis circuit related to the present invention. 16 is a signal waveform diagram of each part of the circuit in FIG. 16, and FIG. 17 is a frequency comparator related to the present invention, or another logical configuration diagram of a phase and frequency comparator. Other logical configuration diagrams of the phase and frequency comparators, FIG. 18, are similar to FIGS.
7 is a circuit wiring diagram showing a synthesis circuit to obtain the output characteristics shown in FIG. 7, FIG. 19 is a block diagram of a phase and frequency comparator based on the present invention, and FIG.
9 is a signal waveform diagram of each part of the circuit, FIG. 21 is a logical configuration diagram of a phase and frequency comparator based on an embodiment of the present invention,
Figure 22 is a signal waveform diagram of each part of the circuit in Figure 21;
24 are another logical configuration diagram of a phase and frequency comparator based on an embodiment of the present invention, FIG. 26 is a logical configuration diagram of a frequency comparator based on an embodiment of the present invention, FIG. , FIG. 27 is a circuit connection diagram of a phase and frequency comparator configured according to an embodiment of the present invention, FIG. 28 is a logical configuration diagram of a conversion circuit for converting a square wave into a differential wave, and FIG. FIG. 29 is a circuit connection diagram of the conversion circuit, and FIG. 30 is a logical configuration diagram showing an example of a branching unit that can obtain a differential pulse output. a...First input line, b...Second input line, 12.13...MuND gate (coincidence gate), 16.17,22...・,...Bistable circuit, 20.21...,, -N Ol' -) (coincidence gate), 20,21°22...Delay means %12
, 16, 20, 21, 22...First frequency detection means, 13, 16, 20°21.22...Second frequency detection means, 23°24...・・NOR gate (matching gate), 26・River・・Bistable circuit, 26
, 27・Mountain...OR gate, 23゜24.2-6.27
・・・・・・Delay means, 12, 25° 26, 27...
...First frequency detection means, 13°25.26.2
7...Second frequency detection means, 28.29...
・・・Bistable circuit, 30・・・・・・muND gate (
reset means), 32...mND gate (negative logic OR game)), 33...hOR gate (
Negative logic AND gate), 36, 39, 46...
...Bistable circuit, 40...NARD gate (
reset gate), 41...OR gate (logical sum gate), 42...mu ND gate (logical product game)), 48...bistable circuit (phase difference detection means), 49.50...HAND gate (matching gate), 51.52..., OR gate (matching gate)
, 4B, 49, 60... Delay means, 45
．． 4j, 49.50.51...first frequency detection means, 45, 48, 49. 50.52...Second frequency detection means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 4 Figure 6 Figure 7 Figure 13 Figure 15 Figure 17

Claims (1)

[Claims] (1) There are two or more leading edges of the pulse signal applied to the first input line between one leading edge of the pulse signal applied to the second input line and the next leading edge of the pulse signal applied to the second input line. a first frequency detection means for generating an output signal when a pulse signal is applied to the second input line between leading edges of the pulse signal applied to the first input line; a second frequency detection means that generates an output signal when two or more leading edges of the pulse signal exist; a first bistable circuit that is set by the output signal of the first frequency detection means; a second bistable circuit that is set by the output signal of the second frequency detection means; and when both the first bistable circuit and the second bistable circuit are in the set state, resetting means for resetting the bistable circuit of the first and second bistable circuits;
A frequency comparator characterized in that a frequency comparison output signal of the pulse signals applied to the first and second input lines is obtained from a bistable circuit. (2) a third bistable circuit that repeats an inversion operation at an inversion period corresponding to a distribution period of the pulse signal when a pulse signal is applied alternately to the first input line and the second input line; When a valid pulse capable of inverting the output state of the third bistable circuit is applied to the first and second input lines, the inversion of the third bistable circuit occurs after the trailing edge of the valid pulse. a delay means for completing the operation; an input terminal is connected to the first input line and the output terminal of the third bistable circuit, and the input terminal is connected to the first input line to invert the output state of the third bistable circuit; an input terminal is connected to a first coincidence gate that generates an output signal at its leading edge when an invalid pulse that cannot be caused is applied, and an output terminal of the second input line and the third bistable circuit; a second coincidence gate that generates an output signal at its leading edge when an invalid pulse that cannot invert the output state of the third bistable circuit is applied to the second input line; The third bistable circuit, the delay means, and the first coincidence gate constitute the first frequency detection means, and the third bistable circuit, the delay means, and the second coincidence gate constitute the second frequency detection means. 2. The frequency comparator according to claim 1, wherein the frequency comparator comprises a frequency detecting means. (3) The delay means has a set terminal connected to a first input line, and a reset terminal connected to a second input line,
a fourth bistable circuit that performs an inversion operation at the leading edge of the effective pulse applied to the first and second input lines; □A third circuit to which the input terminal is connected and generates a set signal for the third bistable circuit at the trailing edge of the effective pulse applied to the first input line.
and a coincidence gate of the fourth bistable circuit, the input terminal being connected to the second input line and the output terminal of the fourth bistable circuit, and at the trailing edge of the effective signal μ applied to the second input line. 3. The frequency comparator according to claim 2, further comprising a fourth coincidence gate that generates a reset signal for the three bistable circuits. (4) The delay means is arranged so that the third coincidence gate and the fourth coincidence gate are cross-coupled to each other.
The input terminal of the third matching gate is connected to the first input line, the input terminal of the fourth matching gate is connected to the second input line, and the input terminal is connected to the second input line. An output terminal of a sixth matching gate connected to the second input line and an output terminal of the third bistable circuit is connected to an input terminal of the third matching gate, and the input terminal is connected to the input terminal of the third matching gate. A patent characterized in that the output terminal of a sixth coincidence gate connected to the first input line and the output terminal of the third bistable circuit is connected to the input terminal of the fourth coincidence gate. A frequency comparator according to claim 2. (6) The reset means includes an output terminal of the first frequency detection means, a second output terminal, an output terminal of the second frequency detection means, an output terminal of the first bistable circuit, and a second bistable circuit. When the input terminals are connected to the output terminals of the respective output terminals, and both the first bistable circuit and the second bistable circuit are set to a set state by the output pulse signal from the first or second frequency detection means. , comprising a reset gate that generates a reset pulse signal to the first bistable circuit and the second bistable circuit at the trailing edge of the output pulse, or The frequency comparator according to item 2. (6) Phase difference detection means for obtaining a rectangular wave output according to the phase difference between the pulse signal applied to the first input line and the pulse signal applied to the second input line, and the second input line a first frequency that generates an output signal when there are two or more leading edges of the pulse signal applied to the first input line between one leading edge of the pulse signal applied to the first input line and the next leading edge of the pulse signal applied to the first input line; When there are two or more leading edges of the pulse signal applied to the second input line between the leading edge of the pulse signal applied to the detection means and the first input line and the next leading edge of the pulse signal applied to the first input line. a second frequency detection means that generates an output signal, a first bistable circuit that is set by the output signal of the first frequency detection means, and a first bistable circuit that is set by the output signal of the second frequency detection means. a second bistable circuit; a reset means for resetting the first and second bistable circuits when both the first bistable circuit and the second bistable circuit are in a set state; The output signal of the phase difference detection means and the output signals of the first and second bistable circuits are combined, and the output signal of the first bistable circuit is synthesized.
The frequency of the pulse signal applied to the input line of the second
When the frequency is lower than the frequency of the pulse signal applied to the input line of the pulse signal, the first DC level output is generated, when the frequency is equal, a rectangular wave output is generated according to the phase difference between both pulse signals, and when it is high, the second DC level output is generated. A phase and frequency comparator, characterized in that it comprises a synthesis means for generating a DC level output. (7) a third bistable circuit that repeats an inversion operation at an inversion period corresponding to a distribution period of the pulse signal when a pulse signal is applied alternately to the first input line and the second input line; When a valid pulse that can reverse the output state of the third bistable circuit is applied to the first and second input lines, after the trailing edge of the valid pulse, the output of the third bistable circuit a delay means for completing an inversion operation, an input terminal connected to the first input line and an output terminal of the third bistable circuit, and an output state of the third bistable circuit to the first input line; a first match gate that generates an output signal at its leading edge when an irreversible pulse that cannot be reversed is applied; input terminals are connected to the second input line and the output terminal of the third bistable circuit; A second bistable circuit is connected to the second input line and generates an output signal at its leading edge when an invalid pulse that cannot reverse the state of the output 1 of the third bistable circuit is applied to the second input line.
The third bistable circuit, the delay means, and the first coincidence gate constitute a first frequency detection means, the third bistable circuit, the delay means,
7. The phase and frequency comparator according to claim 6, wherein the second coincidence gate constitutes a second frequency detection means. 2) The delay means has a set terminal connected to a first input line, a reset terminal connected to a second input line, and a leading of the effective PAP applied to the first and second input lines. a fourth bistable circuit that performs an inverting operation at the edge; an input terminal is connected to the first input line and the output terminal of the fourth bistable circuit; and an effective pulse is applied to the first input line. a third coincidence gate that generates a set signal for the third bistable circuit at the trailing edge of the second bistable circuit, and an input terminal connected to the second input line and the output terminal of the fourth bistable circuit; Claim 7, characterized in that it is constituted by a fourth coincidence gate that generates a reset signal for the third bistable circuit at the trailing edge of the valid pulse applied to the second input line. Phase and frequency comparator as described. (9) The delay means includes a third match gate and a fourth match gate that are cross-coupled to each other.
The input terminal of the third match gate is connected to the first input line, and the input terminal of the fourth match gate is connected to the first input line.
The input terminal of the match gate is connected to the second input line, and the output terminal of the sixth match gate whose input terminal is connected to the second input line and the output terminal of the third bistable circuit is connected to the output terminal of the sixth match gate. The input terminal of the sixth coincidence gate is connected to the input terminal of the third coincidence gate, and the output terminal of the sixth coincidence gate whose input terminal is connected to the first input line and the output terminal of the third bistable circuit is connected to the fourth coincidence gate. 8. The phase and frequency comparator according to claim 7, wherein the phase and frequency comparator is connected to an input terminal of a coincidence gate. (1o) The phase and frequency comparator according to claim 7, characterized in that the third bistable circuit constitutes phase detection means. (11) The phase and frequency comparator according to claim 7, wherein the fourth bistable circuit constitutes phase detection means. (12) The phase and frequency comparator according to claim 7, wherein the sixth coincidence gate constitutes phase detection means. (13) The phase and frequency comparator according to claim 7, wherein the sixth coincidence gate constitutes phase detection means. (14) Input terminals are connected to the output terminal of the first frequency detection means, the output terminal of the second frequency detection means, the output terminal of the first bistable circuit, and the output terminal of the second bistable circuit, respectively. , when both the first bistable circuit and the second bistable circuit are set to the set state by the output pulse signal from the first or second frequency detection means, the output pulse is detected at the trailing edge of the output pulse. The phase control system according to claim 6 or 7, wherein the reset means is constituted by a reset gate that generates a reset Hals signal to the first bistable circuit and the second bistable circuit. Frequency comparator. (15) A logic axis gate to which the output signal from the phase detection means and the output signal from the first or second bistable circuit are applied to the input terminal, and the output signal from the second or first bistable circuit. and the output signal from the OR gate is applied to the input terminal, and the synthesis means is constituted by an AND gate.
Phase and frequency comparator as described in section.