JPS5875230A - Input and output control circuit - Google Patents

Abstract

PURPOSE:To eliminate unnecessary time, and to obtain optimum transfer time, by monitoring data on a two-way data transmission line after a signal is outputted, and holding the time when the data output of a line driver is enabled optimum according to the two-way data transmission line. CONSTITUTION:When a transmission permit signal (d) is supplied, a line driver 21 sends transmission data (e) to a line 31, and a line receiver 22 receives data (b) sent from the line 31 and sends it to the data input terminal 12 of an input and output processor 1. This data (b) and a data output request signal (a) from the terminal 13 of the processor 1 are inputted to a gate circuit 23, which sends a preset signal (c) to an FF24. When the signal is sent, the FF24 is preset once receiving the signal (c) to output a signal (d). The signal (a), on the other hand, is sent out to the output request signal line 32 of a two-way data transmission line 3 through a line driver 25.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control circuit, particularly an input/output control circuit that performs input/output control for determining the data transfer direction of data transfer via a bidirectional data transmission path in input/output control in a data processing device. It relates to an output control circuit.

A conventional input/output control circuit includes a first line driver for sending a data output request signal supplied from an input/output processing device to a partner device, and a first line driver that is supplied from the partner device and has an odd parity. a plurality of line receivers for receiving all received data to be suppressed when a data output request is supplied and supplying the received data to the input/output processing device; and outputting a preset signal obtained by delaying the data output request signal by a predetermined time. a delay circuit, a flip-flop that is preset to output a transmission permission signal when the preset signal is supplied when the data output request signal is supplied, and a flip-flop that is supplied from the input/output processing device and outputs an odd parity signal. and a plurality of second line drivers for transmitting all transmission data to the partner device when the transmission permission signal is supplied.

In this way, when a data output request signal is sent from an input/output processing device, the conventional input/output control circuit automatically transmits the data output request signal to all lines without monitoring the data transfer status of the bidirectional data transmission path. While the data output request signal is sent to the other device by the driver, a preset signal is generated after a certain delay time has elapsed from the sending of the data output request signal.
The flop was preset, and a transmission permission signal was generated to permit data output, thereby making it possible for the line driver to output.

This delay time must be determined to sufficiently satisfy the time from when the data output request signal is sent until the other device prohibits data output. The time it takes to inhibit a data output request signal line largely depends on the length of the data output request signal line. Normally, the length of the bidirectional data transmission path and the length of the data output request signal line are equal, but the length of this bidirectional data transmission path is not necessarily constant, so this delay time is not constant.

Here, if the delay time is too large, wasted time unrelated to data transmission will occur, and if the delay time is insufficient, data will be output to bidirectional data transmission from both sides of the input/output control circuit and the other device at the same time. This had the disadvantage of causing crosstalk.

In other words, conventional input/output control circuits have the drawback that the setting of the data transfer start time is not precise and is not optimized because it causes wasted time and crosstalk due to simultaneous data output. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output control circuit that can eliminate waste time, avoid crosstalk caused by simultaneous data output, and optimize data transfer start time.
That is, an object of the present invention is to solve the above drawbacks by monitoring the data on the bidirectional data transmission line after sending the data output request signal, and to control the data output of the line driver from the sending of the data output request signal. An object of the present invention is to provide an input/output control circuit that can always keep the time required to enable bidirectional data transmission to an optimum value depending on the length of a bidirectional data transmission path.

The input/output control circuit of the present invention includes a first line driver for sending a data output request signal supplied from an input/output processing device to a partner device, and a first line driver that is supplied from the partner device and has an odd parity. a plurality of line receivers for receiving received data that is suppressed when the data output request signal is provided and supplying the received data to the input/output processing device; a gate circuit that outputs a preset signal if the data output request signal is suppressed; a flip-flop that is preset and outputs a transmission permission signal when the data output request signal is supplied and the preset signal is supplied; a plurality of second line drivers for transmitting transmission data supplied from an input/output processing device and having an odd parity value to the counterpart device when the transmission permission signal is supplied; Consists of.

That is, the input/output control circuit of the present invention is connected to an input/output processing device and transmits data via a bidirectional data transmission path having odd parity. A plurality of line receivers, a data output request signal that determines the data transfer direction of a bidirectional data transmission path sent by the input/output processing device, and a signal received by the plurality of line receivers are used to generate the data output request signal. A gate circuit that detects that the other device has prohibited data output during transmission, a flip-flop that is set by an output signal from this gate circuit and reset when transmission of the data output request signal is completed, and this flip-flop. a plurality of line drivers that control the output of output data from the input/output processing device to the bidirectional data transmission line depending on the state of the input/output processing device; and a line driver that sends the data output request signal to the other party (I11 device). , how data is sent from the input/output processing device
6- Constructed to enable data output from the line driver after the input/output control circuit detects that the other device that received the request signal completely prohibits data output to the bidirectional data transmission path. be done.

That is, the input/output control circuit of the present invention includes a plurality of line receivers for receiving data from a partner device via a bidirectional data transmission path, and a plurality of line receivers for receiving data from an input/output processing device on a bidirectional data transmission path. a gate circuit that uses a data output request signal that determines a data transfer direction and data received by a plurality of line receivers to detect that a partner device has prohibited data output while the data output request signal is being sent; A flip-flop that is set by an output signal from the circuit and reset when the transmission of the data output request signal is completed, and output control of the output data from the input/output processing device to the bidirectional data transmission path depending on the state of this flip-flop. and a line driver that sends the data output request signal to the other party's i location.

Next, examples of the present invention will be explained in detail with reference to the drawings.
This will be explained at t1.

FIG. 1 is a circuit diagram including an embodiment of the present invention, in which the input/output control circuit 2 shown in FIG.
A plurality of line drivers 21 transmit the transmission data e to the data line 31 of the bidirectional data transmission path 3 when the transmission permission signal d is supplied, and the data line 31 is connected to the data line 31 from the other device 4. receive data b supplied through
Received data b to data input terminal 12 of input/output processing device 1
'6 Sending line receiver 22 and this line receiver 2
2 and the data output request signal a supplied from the data output request signal terminal 13 of the input/output processing device 1.
Gate circuit 23 which takes f input and outputs preset signal ci
Then, the preset signal C from the gate circuit 23 is supplied to the preset terminal PS, and the data input terminal is grounded.
The flip-flop 24 is supplied with the clock terminal CPVC data output request signal a and outputs the transmission permission signal d from the output terminal Q, and the data output request signal a is sent to the data output request signal line 32 of the bidirectional data transmission line 3. It is composed of a line driver 25 for sending out data.

Further, both ends of the data line 31 of the bidirectional data transmission line 3 are grounded via terminating resistors 33 and 34'lr. Further, the counterpart device 4 has a line driver 41 that outputs the received data b' to the data line 31 of the fully bidirectional data transmission line 3;
Transmission data ef supplied from the bidirectional data transmission path 3
It includes a line receiver 42 for receiving data, and a line receiver 43 for inputting the data output request signal line 32 and supplying the data output request signal a' to a line driver 41Jc.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

The data output request signal a sent from the data output request signal terminal 13 of the input/output processing device 1 is normally "'O",
It becomes 1" only when there is a data output request from the input/output processing device 1 and during data output. Also, the initial state of the flip-flop 24 is reset, and the output terminal a
The transmission permission signal d output from the input/output processing bag M1 is O''. Therefore, when there is no data output from the input/output processing bag M1, the data output request signal ap is not output and the line driver of the input/output control circuit 2 is activated. 2
All outputs of 1 are prohibited, and output of received data b' from the other party's device 4 is permitted.

Now, at time Ta, the data output request signal a is output from the input/output processing device 1, and the data output request signal terminal 13 is 61''.
Suppose that it becomes This generates a data output request signal a' through the line driver 25, data output request signal line 32, and line receiver 43, inhibits the line driver 41 of the other device 4, and suppresses the generation of received data b'. Therefore, all data lines 31 become 0''.

When all the data lines 31 become 0'', the line receiver 2
21C When the suppressed received data b arrives, the outputs of the line receiver 22 are all '1', so the gate circuit 2
Since the data output request signal a+j) 3 is set to "1", it is detected that the data lines 31 have become all 0", and the preset signal C is set to '1'.
becomes 0”.

When the preset signal 0 from the gate circuit 23 becomes '0', the flip 70 knob 24 is preset by the preset signal 0 supplied to the preset terminal P8 and the data output request signal a supplied to the black terminal CP, and is output. The transmission permission signal d from the side terminal Q becomes 11'', and output of the transmission signal data b from the line driver 21 is permitted, and the transmission data from the input/output processing device 1 is transferred to the data ff531 of the bidirectional data transmission path 3. Output.

That is, from the time when the data output request signal a is sent until it is detected that the output of the received data b' from the other party's device 4 is prohibited, the transmitted data e from the line driver 21 is not transmitted.
Since output is prohibited, the input/output HjlJ control circuit 2 and the partner device 4 will not output data at the same time.

In addition, since the transmission data a output from the input/output processing device 1 has an odd parity, if the parity bit is included, all bits will not become '0' at the same time during transmission, so the data will be sent from the input/output control circuit 2. When the signal C starts to be output, the preset signal C from the gate circuit 23 becomes 1", and does not become 0 again during transmission.

Next, if there is no data output from the input/output processing device 1 at time Tb and the data output request signal a supplied from the data output request signal terminal 13 becomes 0'', then a data output request is supplied to the clock terminal CP. Since the signal a fell from ``1'' to ``0'', the flip-flop 24 is reset, and the transmission permission signal d output from the output terminal Q becomes ``0'', and the transmission signal data from the line driver 21 is Output of e is prohibited. The data output request signal a is further transmitted to the line driver 25 and the data output request signal line 32.
Since the data output request signal a' outputted through the line receiver 43 becomes 1'', reception from the line driver 41 of the partner device 4 is possible.
Return to initial state (1) By providing a gate circuit instead of a delay circuit, the input/output control circuit of the present invention outputs a preset signal that specifies the data transfer start time and outputs a data output request signal at a predetermined time. Instead of making a decision by delaying the data output request signal by a certain amount of time, the decision can be made by detecting that the received data is being suppressed while the data output request signal is being supplied. Since the time at which the preset signal is output is automatically determined according to This has the effect of completely avoiding crosstalk due to simultaneous data output from both sides of the control circuit and the partner device, and optimizing the data transfer start time.

That is, the input/output control circuit of the present invention is configured to start data output upon detecting that all data lines have become O'' due to suppression of received data, thereby controlling the data output request signal. This has the effect that the time from sending to when the input/output control circuit outputs data can be kept optimal.

13-

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
5 is a time chart for explaining the operation of the embodiment shown in the figure. DESCRIPTION OF SYMBOLS 1... Input/output processing device, 2... Input/output control circuit, 3... Bidirectional data transmission path, 4...
. . . Other party device, 11 . . . Data output terminal, 12 . . . Data output terminal, 13 . . . Data output request signal terminal, 21 . Driver, 22...Line receiver, 23...
・Gate circuit, 24...Flip-flop, 2
5... line driver, 31... data line, 32... data output request signal line, 33...
...Terminal resistor, 34...Terminal resistor, 41
... Line driver, 42 ... Line receiver, 43 ... Line receiver, -a, a / ... Data output request signal, b,
b',,. ...Received data, C...Preset signal, d
・Old...Transmission permission signal, e...Transmission data, D
・・River・Data terminal, CP・・・・Black terminal,
PS: preset terminal, Q: output terminal, 14- Ta: time, Tpd: propagation delay time,
Tb...Time. 15-

Claims (1)

[Claims] a first line driver for sending a data output request signal supplied from the input/output processing device to all counterpart devices; a plurality of line registers for receiving and supplying received data to the input/output processing device, which is suppressed when the received data is suppressed when the data output request signal is supplied; a gate circuit that outputs all preset signals; a flip-flop that is preset and outputs a transmission permission signal when the preset signal is supplied when the data output request signal is supplied; and the input/output processing device. an input/output control circuit comprising: a plurality of second line drivers for transmitting transmission data having odd parity supplied from the second line driver to the other party device when the transmission permission signal is supplied.