JPS5874065A - Mounting structure for semiconductor device - Google Patents
Mounting structure for semiconductor deviceInfo
- Publication number
- JPS5874065A JPS5874065A JP17403781A JP17403781A JPS5874065A JP S5874065 A JPS5874065 A JP S5874065A JP 17403781 A JP17403781 A JP 17403781A JP 17403781 A JP17403781 A JP 17403781A JP S5874065 A JPS5874065 A JP S5874065A
- Authority
- JP
- Japan
- Prior art keywords
- package
- chip
- signal wire
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
本発明はLll等の半導体装置を高密度にプリント基板
に実装する構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for mounting semiconductor devices such as Lll on a printed circuit board at high density.
従来LSI等の半導体装置を多数組み合せてプリン)基
板に実装し電子回路等を構成する際の実装構造を第1図
に示す。FIG. 1 shows a conventional mounting structure in which a large number of semiconductor devices such as LSIs are combined and mounted on a printed circuit board to form an electronic circuit or the like.
図示するように半導体チップを搭載したデエアルインラ
イン型の七う々ツクパッケージより導出された外部リー
ド線2はプリント板8上に形成されている所定パターン
の半田のような導体層のパターン4に合致するようなス
ルホール(図示せず)を介して該基板に設置されている
。しかしこのようにプリント基板8上に1個づつパッケ
ージの直方体形状の六面体のうち最も面積の広い部分を
プリント基板に当接するようにして設置したのではプリ
ント板に搭載されるパッケージの個数が少なくなる。As shown in the figure, external lead wires 2 led out from an in-line seven-channel package with a semiconductor chip mounted are connected to a pattern 4 of a conductive layer such as solder in a predetermined pattern formed on a printed circuit board 8. It is installed in the substrate through matching through holes (not shown). However, if the packages are placed one by one on the printed circuit board 8 so that the widest part of the hexahedron of the rectangular parallelepiped is in contact with the printed circuit board, the number of packages that can be mounted on the printed circuit board will be reduced. .
い
また該パッケージの側面より出す遂外部リード線はプリ
ント基板に設けられた端子すなわち導体層によって所定
のパターンに形成されて該パッケージ内の半導体チップ
を選択するためのチップ七しタ)端子やあるいは半導体
チップを駆動させるための電源端子や、あるいは半導体
チップより導出される信号線と接続するそれぞれの端子
と接続されているが、これらのうち共通の導締をとりま
とめて接続した方が実装密度が増加する。Furthermore, the external lead wires coming out from the side of the package are formed into a predetermined pattern by terminals provided on the printed circuit board, that is, conductor layers, and are used as chip terminals for selecting the semiconductor chips in the package. It is connected to the power supply terminal for driving the semiconductor chip or to each terminal that connects to the signal line led out from the semiconductor chip, but it is better to connect the common conductors together for higher packaging density. To increase.
本発明は前記プリント基板上にパッケージを形成する六
面体壷状の最も面積の小さい長方彰形状の面がプリント
基板上に当接するようにパッケージを設置し、また共通
の信号線を共通の端子に接続させるようにして、プリン
)基板上に高密度に半導体装置を実装する半導体装置の
実装構造の提供を目的とするものである。In the present invention, the package is installed on the printed circuit board so that the rectangular-shaped surface with the smallest area of the hexahedral pot shape that forms the package is in contact with the printed circuit board, and the common signal line is connected to the common terminal. It is an object of the present invention to provide a mounting structure for semiconductor devices in which semiconductor devices are mounted at high density on a printed circuit board in a manner such that they are connected to each other.
かかる目的を達成するための半導体装置の実装構造は、
バッ、ケージ内に半導体チップを収容し、表面に該チッ
プからの信号線を導出してなる半導体装置を基板上に複
数個隣接して実装してなり、それぞれの該信号線が隣接
せる他の半導体装置の対応する信号線に直接接続され、
該信号線のうち少なくともチップ選択用信号線が該基板
に設けたチップ選択用パターンにそれぞれ接続されてな
ることを特徴とするもので、ある。以下図面を用し1て
本発明の一実施例につき詳細に説明する。The mounting structure of the semiconductor device to achieve this purpose is as follows:
A semiconductor device is formed by accommodating a semiconductor chip in a cage, and mounting a plurality of semiconductor devices adjacent to each other on a substrate, each having a signal line led out from the chip on the surface, and each signal line is connected to another adjacent semiconductor device. Connected directly to the corresponding signal line of the semiconductor device,
It is characterized in that at least the signal lines for chip selection among the signal lines are respectively connected to the chip selection patterns provided on the substrate. An embodiment of the present invention will be described in detail below with reference to the drawings.
第意図より第4図までが本発明の半導体装置の実装構造
の一実施例を示i斜視図であるO會ず第意図に示すよう
に本発明の半導体装置の実装構造はプリン)基板ll上
に六面体、構造のパッケージ12を六面体のうちで最も
表面積の小さい面が当接するようにして配置する。そし
てプリン)基板にはパッケージ内の半導体チップを選別
してそのチップのみ書き込み読み出し動作させるような
チップセレクト端子13を所定のパターンに半田すけし
ておき、その部分にパッケージの外部リード線が当接す
るようにしておく。そしてチップより得られた信号を導
出するための信号線は同電位の信号線のみをチップf信
号線の端子よりパッケージ表面に所定パターンにメタラ
イズして設けた導体層14に接続するようにする。そし
てこの導体層は共通のものを集めて第8図に示すような
例えばペークライシで形成した端子板15に集めるよう
にする。ここで第8図の16はチップセレクト端子のう
ち共通のものを集めた端子でパッケージの実装した端部
に設けたベークライトの端子部材17に形成されている
。Figures 1 through 4 are perspective views showing one embodiment of the mounting structure of the semiconductor device of the present invention. A package 12 having a hexahedral structure is placed so that the surfaces of the hexahedron with the smallest surface area are in contact with each other. Chip select terminals 13 are soldered to the printed circuit board in a predetermined pattern to select the semiconductor chips in the package and write/read only those chips, and the external lead wires of the package come into contact with these terminals. Let's do it like this. As for the signal lines for deriving the signals obtained from the chip, only the signal lines of the same potential are connected from the terminal of the chip f signal line to the conductor layer 14 provided on the package surface by metallization in a predetermined pattern. The common conductor layers are then assembled into a terminal board 15 formed by, for example, paklyshi as shown in FIG. Here, reference numeral 16 in FIG. 8 is a collection of common chip select terminals and is formed on a bakelite terminal member 17 provided at the end of the package where it is mounted.
′:
このように端子板15と、端子部材17とで実装したパ
ッケージの端部を固定するようにすれば実装がより確実
なものとなる。': By fixing the ends of the package mounted with the terminal board 15 and the terminal member 17 in this way, the mounting becomes more reliable.
會た第4図に示すように実装すべきパッケージの間にセ
ラミックのような絶縁熱放散板18をはさみ込むように
すれば半導体装置からの熱放散がよくなり更に半導体装
置の特性が安走して高信頼度の実装構造が形成される。As shown in FIG. 4, if an insulating heat dissipation plate 18 such as ceramic is sandwiched between the packages to be mounted, heat dissipation from the semiconductor device will be improved and the characteristics of the semiconductor device will be improved. A highly reliable mounting structure is formed.
また以上の実施例のくせにセラミックのような絶縁板を
介してパッケージを多段に積み上げて積層して実装する
ことも可能である。Further, in spite of the above embodiments, it is also possible to stack packages in multiple stages and laminate them with insulating plates such as ceramics interposed therebetween.
また以上の実施例においてはセラミックのパッケージに
例を用いて述べたがその他セラ電ツタ等絶縁基板で形成
したチップ中ヤリアを用いても差し支えない。Furthermore, although the above embodiments have been described using a ceramic package as an example, it is also possible to use a chip inner layer formed of an insulating substrate such as a ceramic vine.
第1図は従来の半導体装置の実装構造を示す図で、第意
図より第4図までは本発明の半導体装置の実装構造を示
す図である。
閣において1.12はパッケージ、2は外部リーF18
は絶縁板を示す。FIG. 1 is a diagram showing the mounting structure of a conventional semiconductor device, and from the first intention up to FIG. 4 are diagrams showing the mounting structure of the semiconductor device of the present invention. In the cabinet, 1.12 is a package, 2 is an external Lee F18
indicates an insulating plate.
Claims (1)
からの信号線を導出してなる半導体装置を基板上に彼数
個隣接して実装してなり、それぞれの該信号線がii*
せる他の半導体装置の対応する信号線に直接接続され、
該信号線のうち少なくともチップ選択用信号線が該基板
に設けたチップ選択用パターンにそれぞれ接続されてな
ることを特徴とする半導体装置の実装構造。A semiconductor chip is housed in a package, and several semiconductor devices are mounted adjacently on a substrate, each having a signal line leading from the chip on the surface, and each signal line is
directly connected to the corresponding signal line of other semiconductor devices
A mounting structure for a semiconductor device, wherein at least a chip selection signal line among the signal lines is connected to a chip selection pattern provided on the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17403781A JPS5874065A (en) | 1981-10-29 | 1981-10-29 | Mounting structure for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17403781A JPS5874065A (en) | 1981-10-29 | 1981-10-29 | Mounting structure for semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5874065A true JPS5874065A (en) | 1983-05-04 |
JPH0378786B2 JPH0378786B2 (en) | 1991-12-16 |
Family
ID=15971519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17403781A Granted JPS5874065A (en) | 1981-10-29 | 1981-10-29 | Mounting structure for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5874065A (en) |
-
1981
- 1981-10-29 JP JP17403781A patent/JPS5874065A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0378786B2 (en) | 1991-12-16 |
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