JPS5874059A - Wiring substrate - Google Patents

Wiring substrate

Info

Publication number
JPS5874059A
JPS5874059A JP17227481A JP17227481A JPS5874059A JP S5874059 A JPS5874059 A JP S5874059A JP 17227481 A JP17227481 A JP 17227481A JP 17227481 A JP17227481 A JP 17227481A JP S5874059 A JPS5874059 A JP S5874059A
Authority
JP
Japan
Prior art keywords
conductor
chip
pad
mounting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17227481A
Other languages
Japanese (ja)
Inventor
Yoshitaka Fukuoka
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17227481A priority Critical patent/JPS5874059A/en
Publication of JPS5874059A publication Critical patent/JPS5874059A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To save material cost to possible degree, by providing a plurality of hollow parts on a pad pattern for mounting noble metal parts. CONSTITUTION:A junction pad 11 for supporting and fixing a chip and a pad 13 for other junction are provided on a ceramic substrate 10. This middle pad 11 forms a lattice and forms a plurality of hollow parts 12 in the surface of the substrate 10. The die bonding pad 11 has the tendency wherein an IC chip becomes large accompanied by a high integration, and accordingly, in this constitution, a noble metallic material of Au, etc. can be saved by the area of the hollow parts 12.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は、単層あるいは多層のｌ　Ｃノ譬ｙケージある
いはマルチチ、グツ母、ケージに使用される配線基板に
一関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a wiring board used for a single-layer or multi-layer LC cage, multilayer cage, or cage.

（２）従来技術 近年、高密度高集積化技術の進歩によＪ）ＩＣのチップ
サイズはだんだん大きくなって行く傾向にある。そのた
めＩＣチ、プを実装する単層あるいは多層のｉ　Ｃ−り
ｙケージ用の配線基板あるいはそれ等のＩＣチップを複
数個実装し全体をシールする所謂マルチチッゾノヤ、ケ
ージ用の単層あるいは多層の配線基板上のＩＣＣクツＪ
”ｆｌ載用の導体ツタターンであるグイポンディング／
４ツドの大きさも、ＩＣチップサイズの増大に伴ない大
きなものとなって行く傾向にある。(2) Prior art In recent years, due to advances in high-density and high-integration technology, the chip size of ICs has been gradually increasing. Therefore, a single-layer or multi-layer wiring board for an IC chip is used to mount an IC chip, or a so-called multi-layer wiring board for mounting a plurality of IC chips and sealing the entire cage is used. ICC shoes on the board
``Guipponding, a conductor vine turn for FL mounting/
The size of the quadrant also tends to become larger as the IC chip size increases.

これらの配線基板？製造方法としては、グリーンシニト
基板上にｗＩｈるいは、Ｍｅ、Ｍｕ等の貴金属導体（−
ストを印刷し、乾燥、焼成する事によシ導体）７ターン
を形成し、しかるｉ＆ンディング性を＾好にするためそ
の導体ノ４ターン上にＮｌメ、キ層および貴金属である
Ａｕメ、キ層を警戒する方法（所謂還元雰囲気炉で同時
焼成する印刷積層法あるいはシート積層法）ある−はア
ルミナ等のセラミ、り基板上に厚膜導体ペーストを印刷
し、乾燥、焼成する事によ）導体・母ターンを形成する
所謂厚膜配線法等が挙げられる。後者の方法においても
ファインライン性、がンディング性あるいは耐腐食性の
観点よ秒、導体ノ譬ターンは貴金属ペーストである例え
ばＡｕペースト、等を用いて形成することが多い。These wiring boards? As for the manufacturing method, precious metal conductors such as wIh, Me, Mu, etc. (-
7 turns of the conductor are formed by printing, drying, and firing, and in order to improve the I&nding property, Nl layer, gold layer, and Au layer, which is a noble metal, are formed on the 4 turns of the conductor. There is a method (printed lamination method or sheet lamination method in which simultaneous firing is carried out in a so-called reducing atmosphere furnace) to prevent the formation of double layers.One method is to print a thick film conductive paste on a ceramic or resin substrate such as alumina, dry it, and then bake it. ) The so-called thick film wiring method for forming conductors and mother turns can be mentioned. Even in the latter method, conductor turns are often formed using a noble metal paste, such as Au paste, from the viewpoint of fine line properties, bonding properties, or corrosion resistance.

（３）従来技術の問題点 ＩＣチ、デ搭載用のダイーンディングノ豐、ド尋の導体
／？ターンの面積が増大した場合には、貴金属系の導体
材料からなる導体ノ量ターンの材料費の上昇によシ配線
基板のコストが増大し、ひいてはＩ　Ｃ／譬、ケージあ
るいはマルチチ、！・譬、ケージのコスト高を余儀なく
する結果となる。(3) Problems with the conventional technology: Is the conductor of the IC chip or the conductor for the mounting of the IC? When the area of the turns increases, the cost of the wiring board increases due to the increase in the material cost of the conductor turns made of precious metal-based conductor materials, which in turn increases the cost of the wiring board. - This results in an unavoidable increase in the cost of the cage.

（４）発明の目的 本発明の目的は、ＩＣ／ｌ　ｙケージあるいはマルチチ
ッデノ譬ツケージ用の単層あるいは多層の配線基板を構
成する場合等に、貴金属系の導体を含む導体／４ターン
の材料費を極力弁えることができる配線基板を提供する
ととにある。(4) Purpose of the Invention The purpose of the present invention is to reduce the cost of conductor/four-turn material including noble metal conductors when configuring a single-layer or multi-layer wiring board for an IC/ly cage or a multi-chip device. Our goal is to provide a wiring board that can be used as effectively as possible.

（５）発明の要約 本発明は、導体パターンの一部例えばＩＣチ、プ勢のチ
、ｆ部品搭載用のグイがンディンダ・量、ドとして用い
られる導体ツクターンの基板面内に複数の中空部を設け
たことを特徴としている。(5) Summary of the Invention The present invention provides a plurality of hollows in the substrate surface of a conductor pattern, such as an IC chip, a pusher chip, and a guide for mounting f-components. It is characterized by having the following.

（６）発明の効果 本発明によれば基板面内に中空部を有しない所謂ソリ、
ド構造の導体パターンのみで全ての導体・臂ターンを形
成する従来の配線基板に比べ、導体・臂ターンの外縁形
状および寸法が同じ場合、導体・リーンの材料使用量を
少なくでき、その材料費、ひいては配線基板全体のコス
トを効果的に引下げることができる。また１導体ノ々タ
ーンの基板面内に中空部を設けても、特にその導体ノ譬
ターンがｌイ〆ンディングノぐ、ド勢に用いられるもの
てあ、５場合は、機能上なんら支障はない。(6) Effects of the invention According to the present invention, the so-called sled, which does not have a hollow part within the plane of the substrate,
Compared to conventional wiring boards in which all conductors and arm turns are formed using conductor patterns with a straight structure, if the outer edge shape and dimensions of the conductor and arm turns are the same, the amount of material used for the conductors and legs can be reduced, and the material cost can be reduced. Therefore, the cost of the entire wiring board can be effectively reduced. Furthermore, even if a hollow part is provided within the board surface of one conductor turn, there will be no functional problem, especially if the conductor turn is used for electrical purposes. do not have.

（７）発明の実施例 第１図は、本発明の一実施例として単層のＩＣパ、ケー
ジ□用の配線基板の平面を示している。図において、１
０はアルミナ等のセラミック基板であシ、この基板１０
上にノー、チングで示すようＫＡｕ等の貴金属系の導体
を含む導体・臂ターンが形成されている。これらの導体
ノ母ターンのうち、１１はＩＣチ、ゾ等のチ、ｆ部分を
搭載して支持固定するためのグイがンディング／ｌツド
、１３はＡｕ１ｌ勢のワイヤーがンディング郷によ１）
ＩＣチ、ｆ等のチップ部品のインナーリードがンディン
グノ々ツドと電気的に接続されるアウターリードｙＦン
ディンダノ譬ツド、１４はアウターリードがンディング
ｌ譬、ドＩＳとＩＣノ臂フッケージＩ１０リードと０電
気的接続をなすぺ〈形成された配線ノ譬ターンを示して
いる。ここで、グイーンディングノ譬、ド１１は格子状
に形成され、基板１０面内に複数の中空部１２を有する
。(7) Embodiment of the Invention FIG. 1 shows a plan view of a wiring board for a single-layer IC pad and cage □ as an embodiment of the invention. In the figure, 1
0 is a ceramic substrate such as alumina, this substrate 10
A conductor/arm turn including a noble metal conductor such as KAu is formed as shown by the tings above. Of these conductor mother turns, 11 is a guide for mounting and supporting and fixing parts such as IC chip, z, etc., and 13 is a wiring for Au1L wires.1)
14 is an example of an outer lead where the inner leads of chip components such as IC chip and f are electrically connected to the terminal nodes. It shows an analogy of formed wiring patterns for making electrical connections. Here, the grooves 11 are formed in a lattice shape and have a plurality of hollow portions 12 within the surface of the substrate 10.

グイ？ンディングノ々、ド１１は、近年の高密度高集積
化技術の進歩によるＩＣチ、ｆサイｌの増加に伴ないそ
の寸法ＡＸＩＩを大きくする必要が生じている。しかし
、ダイがンディングノ母、ド１１を図の如き形状に形成
すれば、寸法ＡＸＢが同じで、ソリッド状に形成された
従来のものに比べ、中空部１２０面積分だけ導体ノ譬タ
ーンの材料を減らすことができ、その材料費を大きく低
減することが可能となる。Guy? With the recent progress in high-density and high-integration technology, it has become necessary to increase the dimensions AXII of the terminals and gates 11 as IC chips and f-sizes have increased. However, if the die is formed into the shape shown in the figure, the dimensions AXB are the same, and the material of the conductor turns is reduced by 120 areas of the hollow part, compared to the conventional die formed in a solid shape. This makes it possible to significantly reduce the material cost.

第２Ｍは、本発明の他の実施例として多層のマルチチ、
ゾノや、ケージ用配線基板に適用した例を示しえもので
ある。２０は、アルミナ轡のセラミック基板、２１はＩ
Ｃチッゾ尋のチップ部品搭載用のグイぎンディングノ４
　ラドで４り、ダイがンディングノ量、ド２１は第１図
と同じく格子状に形成され、複数の中空部２２を有する
。The second M is a multilayer multi-chip as another embodiment of the present invention.
An example of application to a wiring board for a zono or a cage can be shown. 20 is an alumina ceramic substrate, 21 is an I
C Chizzo Hiro's Guigindingno 4 for mounting chip parts
The groove 21 is formed in a lattice shape as in FIG. 1, and has a plurality of hollow portions 22.

ま゛た、２３はアウターリードゲンディングノ譬ツド、
２４はＩＣチップのシーリング用キヤ、デを装着するた
めの／４’ターン、２５はｌ１０ＩＪ’−）”装着用の
ノ母ターンを示している。この実施例によっても、ダイ
デンディング／４’ツド２１が格子状に形成されている
ことにより、先の実施例と同様な効果が得られる。４に
この実施例のよう′にメイゴンディングノ臂、ド２１が
多数ある場合、本発明による導体パターンの材料量低減
による配線基板のコストの低減効果は大である。Also, 23 is a parable of outer lead leading.
Reference numeral 24 indicates a /4' turn for mounting the IC chip sealing carrier, and 25 indicates a mother turn for mounting the IC chip. By forming the conductor 21 in a grid shape, the same effect as in the previous embodiment can be obtained.In the case where there are a large number of 21 in the 4th embodiment as in this embodiment, the conductor according to the present invention may be used. The effect of reducing the cost of the wiring board by reducing the amount of material for the pattern is significant.

なお、上記各実施例ではダイがンディング／４．ドを格
子状に形成したが、これに限定されるものではなく、例
えば第３図に挙げたような種々の形状が考えられる。第
３図（ａ）〜（ｃ）のいずれに示されたダイーンディン
グノ豐、ド３１も基板平面内に複数の中空部３２を有し
ており、ダイーンディングノｆ、ドとして必要な機能を
有しながらも、導体の使用量は従来に比べ少なくなって
いる。Incidentally, in each of the above embodiments, die bonding/4. Although the grid is formed in a lattice shape, it is not limited to this, and various shapes such as those shown in FIG. 3 can be considered, for example. The die-ending nozzle 31 shown in any of FIGS. 3(a) to 3(c) also has a plurality of hollow portions 32 in the plane of the substrate, which are necessary for the die-ending nozzle f and do. Although it has the same functionality, the amount of conductor used is smaller than in the past.

以上説明したように、本発明によれば導体ノ９ターンの
材料量の減少によ）、配線基板コストの低減ひいてはＩ
Ｃノヤッケージあるいけマルチチッデノ４ツケージ等の
デバイスのコストの低減をはかる事が可能となる。As explained above, according to the present invention, by reducing the amount of material for the nine turns of the conductor), the cost of the wiring board can be reduced, and the I.
It becomes possible to reduce the cost of devices such as a C-type package or a multi-chip package.

なお、ＩＣチ、ｆのマウント方法は、ハンダによるもの
博電工４キシによるもの、熱圧着によるもの等、種々考
え′られ、本発明はこれら各種のマウント方法について
有用□であるが、特に導電工４キシによるマウントグロ
セスを用いる場合に有効である。まえ、実施例において
は、主ＫＩＣチッデ搭載用のグイデンディングノ臂。Note that there are various ways to mount IC chips and f, including soldering, Hakudenko 4x, thermocompression bonding, etc., and the present invention is useful for these various mounting methods, but it is particularly suitable for conductive mounting. This is effective when using mount grosses using 4x. In the embodiment, there is a guiding arm for mounting the main KIC chip.

ドに本発明を適用した例を説明したが、これに限定され
るものではなく、他９チップ部品搭載用・量、ドその他
の比較的大きな占有面積を有する導体ツヤターンについ
て同様に本発明を有することができる。Although an example in which the present invention is applied to a conductor has been described, the present invention is not limited thereto, and the present invention is similarly applicable to conductor glossy turns that are used for mounting chip components, and which occupy a relatively large area. be able to.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は本発明の実施例に係る配線基板の
平面図、第３図は本発明に基くダイがンディングノ譬、
ド形状の他の例を示す平面図である。 １０．２０・・・セラミ、り基板、１１．ｉｌｌ。 ３１・・・グイゲンディングノ臂ッド、１２，２１゜３
２・・・中空部。 ’、１１１１ ：１．１゜ 出願人代理人　　弁理士　鈴　江　武　彦第１図 へ１１ 第２図 フ　　　　　第３図1 and 2 are plan views of a wiring board according to an embodiment of the present invention, and FIG. 3 is an example of die mounting according to the present invention.
FIG. 7 is a plan view showing another example of the curved shape. 10.20... Ceramic substrate, 11. ill. 31...guigendingno arm, 12,21゜3
2...Hollow part. ', 1111: 1.1゜Applicant's agent Patent attorney Suzue Takehiko Go to Figure 1 11 Figure 2 F Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）　　貴金属系の導体を含む導体パター／を基板上
に形成してなる配線基板において、前記導体ツリー、ン
の一部の前記基板面内に複数の中空部を設けたことを特
徴とする配線基板。(1) A wiring board in which a conductor pattern containing a noble metal conductor is formed on a board, characterized in that a plurality of hollow portions are provided in a part of the board surface of the conductor tree. wiring board. （２）　　基板面内に複数の中空部を設けた導体ノ４タ
ーンは、チアゾ部品葺、載用のダンがンディング・母ツ
ドであることを特徴とする特許請求の範囲第１項記載の
配線基板。(2) The wiring according to claim 1, wherein the four turns of the conductor having a plurality of hollow portions in the substrate surface are covered with a thiazo component, and the mounting pad is a landing pad. substrate.
JP17227481A 1981-10-28 1981-10-28 Wiring substrate Pending JPS5874059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17227481A JPS5874059A (en) 1981-10-28 1981-10-28 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17227481A JPS5874059A (en) 1981-10-28 1981-10-28 Wiring substrate

Publications (1)

Publication Number Publication Date
JPS5874059A true JPS5874059A (en) 1983-05-04

Family

ID=15938869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17227481A Pending JPS5874059A (en) 1981-10-28 1981-10-28 Wiring substrate

Country Status (1)

Country Link
JP (1) JPS5874059A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715353A3 (en) * 1994-11-29 1996-10-16 Shinko Electric Ind Co Board for a semiconductor chip
JP2007208276A (en) * 2007-03-08 2007-08-16 Texas Instr Japan Ltd Semiconductor device and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744570B2 (en) * 1976-06-18 1982-09-22
JPS587336B2 (en) * 1979-12-18 1983-02-09 第一製薬株式会社 improved granulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744570B2 (en) * 1976-06-18 1982-09-22
JPS587336B2 (en) * 1979-12-18 1983-02-09 第一製薬株式会社 improved granulator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715353A3 (en) * 1994-11-29 1996-10-16 Shinko Electric Ind Co Board for a semiconductor chip
US5744224A (en) * 1994-11-29 1998-04-28 Shinko Electric Industries Co., Ltd. Board for mounting semiconductor chip
JP2007208276A (en) * 2007-03-08 2007-08-16 Texas Instr Japan Ltd Semiconductor device and its manufacturing method
JP4484891B2 (en) * 2007-03-08 2010-06-16 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof

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