JPS5872266A - Electronic device - Google Patents

Abstract

PURPOSE:To optimize the saving of power consumption by inhibiting a power consumption saving releasing command signal through a program in an electronic device incorporating a power consumption saving function. CONSTITUTION:An electronic device in which a power consumption saving mode is selected by inhibiting a synchronous signal to stop its operation and the mode is released independently by plural releasing command signals is provided with plural releasing command gate groups 7-1-7-3 so that the power consumption saving mode is prevented from release by inhibiting an optional one of releasing command signals 3-1-3-3 by control signals 2-2-2-4. Thus the optimum power consumption can be selected by executing selective release through the control signals 2-2-2-4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device having a built-in function for saving power consumption.

Recently, the power consumption of electronic devices has become extremely low due to the shift to C-MOS in large-scale integrated circuits (LSI) and the shift to liquid crystal display elements. Power consumption is not a big problem when using commercial power as a power source, but portable or handheld electronic devices such as calculators are often battery-powered, so power consumption is limited to the range of use. This will be an important factor for expansion. It is desirable for such electronic devices to significantly reduce power consumption.

This reduction in power consumption makes it possible to drive the device with a battery, and even to use a low-capacity battery, which promotes the miniaturization and weight reduction of electronic devices.

Power consumption in a C-MO8 circuit is usually reduced by stopping the dynaic operation. C
- Most of the power consumption of the MO8 circuit is the charging and discharging power during gate switching, so if the signal movement is stopped, only the leakage current is consumed. Therefore, when idling, there is a synchronous clock that does not require CPU operation.

The dynamic operation is suppressed by killing the irradiation, etc., and power consumption can be reduced.

When the CPU is required to operate, this dynamo operation prohibition must be canceled;
If this happens too often, it will not be effective in reducing power consumption. This often becomes a problem, especially when there are multiple release conditions.

An object of the present invention is to achieve optimal power saving effects by providing hardware that can selectively cancel when there are multiple cancellation conditions.

According to the present invention, a means for controlling whether the power saving mode (hereinafter referred to as HALT mode) release command is active or inactive is added. By controlling the control means of the controller by the CPU, it becomes possible to select only the necessary HALT mode release command signal, thereby obtaining the optimum power consumption depending on the application.

The present invention will be explained in more detail below with reference to the drawings.

FIG. 1 shows an embodiment of the invention. Here, control of the entire system is executed by the program memory 1, and when a stop (HALT) command is issued from there, it is decoded and checked by the gate latch group 2. As a result, when the HALT command is issued, the signal line 2-1 becomes @1# level.

At this time, if the output of the NO gate 8 is at the "1" level, the condition is met at the NAND gate, IO, and the scissors output is 10.
AND the signal from the synchronization signal generation circuit 6.
Prohibited at Gate 11. Konoto Mai, program memory 1
．． In stock, fetch group 2, and C
7 lip 70 knobs in PU main part 12, for example 13
The synchronizing signal of the circuit to which the equal synchronizing signal is supplied is inhibited, and the CPU 12 stops operating and enters HALT mode. Since the synchronization signal supplied to program memory 1 is now disabled, the program does not proceed and HA
Continue executing LT commands. Next, when the output of the NOR gate 8 becomes "0" level, the HALT command signal 2-1
is prohibited, the output of the NAND gate 10 becomes 11" level, a synchronizing signal is applied to the AND gate 11, and the program starts to proceed again. There is a group of ANDN gates that control the NOR gate 8. This is the gate means according to the present invention. In this embodiment, three AND gates (7-1.7-2.7-3) are provided.
- One input of gate group 1.7-2.7-3 is synchronized with the release command, and an output signal 3-1.3 from gate group 3 is provided.
-2.3-3 is connected.

In addition, on the other hand, there is an instruction,
Outputs 2-2.2-3.2-4 are input, respectively.

The output 2-2.2-3.2-4 is the release command signal 3-1.
3-2' and 3-3 are actively and inactively controlled. In other words, if the control signal 2-2.2-3゜2-4 is at the 10" level, the release command signal 3-1.3-2.3-3 is prohibited or inactivated; on the other hand, if it is at the @l" level, Activate it. Therefore, any signal of release command signal 3-1.3-2.3-3 is inhibited by control signal 2-2.2-3.2-4, and HALT
You can prevent the mode from being canceled. If control signal 2
-2 is at the 10# level and is in HALT mode, even if the release command signal 3-1 goes to the 11" level, the condition of the AND gate 7-1 cannot be met.
0” level, therefore the output of NOR gate 8 is 11
”HALT command signal 2-1 is NA because the level is maintained.
It is not prohibited by the ND gate 10 and the HALT mode is not released. By controlling the control signals 2-2.2-3.2-4 by the program memory 1 in this way, the optimal H
ALT mode can be released. This control signal 2
-2.2-3.2-4 may be controlled, for example, by the operand section of the program memory, or may be controlled by the output of general registers. One-way release command signal 3-1.3
-2.3-3 is the output of the release command synchronization latch group 3, and the input of the crest latch group is the timer 2 system 4-1.4-2.
A key human power signal 5 from outside is illustrated as an example. The timer counter 4 and release command synchronization latch group 3 are directly driven by the synchronization signal generation circuit 6, and therefore the HALT
It works even when in mode. Therefore, for example, when the timer reaches a certain value or when a key is input, the release command signal 3-1.3-2.3-3 is sent to HA L'I.
'Can occur regardless of mode. If the release command signal is unconditionally input to the NOR gate 8, the H
Since the AL'l' mode is canceled, the effect of power saving cannot be improved. Therefore, control signal 2-
Optimum power consumption can be achieved by executing selection cancellation in steps 2, 2-3, and 2-4.

As described above, according to the present invention, the HALT release command signal is arbitrarily prohibited according to the program, so that an optimal power saving effect can be obtained.

In the present description, there is only one synchronization signal, but even if there are multiple types of synchronization signals, the gist of the present invention can be expanded without changing the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Program memory, 2...Instruction fetch latch group, 3...Release command synchronization latch group, 7...Release command inhibition gate group, 10 ...HALT command generation game), 11
・・・・・・Synchronization signal prohibition gate.

Claims (2)

[Claims] (1) In an electronic device that stops operation by disabling a synchronization signal and enters a power saving mode, and in which the mode is independently canceled by a set cancellation command signal, a plurality of gate means, and An electronic device characterized in that a control means for the gate means is provided to arbitrarily inhibit the plurality of release command signals by means of a program memory. (2) An electronic device according to claim (1), characterized in that a plurality of gate means and a control means for the gate means are integrated into an integrated circuit on the same substrate as the electronic device.