JPS5871896U - alarm device - Google Patents
alarm deviceInfo
- Publication number
- JPS5871896U JPS5871896U JP16522781U JP16522781U JPS5871896U JP S5871896 U JPS5871896 U JP S5871896U JP 16522781 U JP16522781 U JP 16522781U JP 16522781 U JP16522781 U JP 16522781U JP S5871896 U JPS5871896 U JP S5871896U
- Authority
- JP
- Japan
- Prior art keywords
- response
- assigned
- terminal
- signal
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Alarm Systems (AREA)
- Small-Scale Networks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はこの考案による警報装置のブロック図、第2図
は同警報装置の中実装置のブロック図、第3図は同警報
装置の各中間装置及び端末装置に異常のない状態のタイ
ムチャート、第4図は同警報装置の中間装置2−2のF
b送信機に異常がある状態のタイムチャート、第5図は
同警報装置の中間装置2−1に属する端末装置3−1が
異常が検出した状態のタイムチャートである。
1・・・中実装置、2−1乃至2−10・・・中間装置
、3−1乃至3.−n・・・端末装置、4−1乃至4−
10・・・呼び出し送信機、8−1乃至8−10・・・
呼び出し受信機、9,10・・・応答送信機、11.1
2・・・応答受信機、17.18−1乃至18.22・
・・中間装置異常指示用論理回路、23・・・常態信号
受信機、25−11乃至25−10n、26−1乃至2
6−10・・・端末装置異常指示用論理回路。Fig. 1 is a block diagram of the alarm device according to this invention, Fig. 2 is a block diagram of the solid equipment of the alarm device, and Fig. 3 is a time chart when there is no abnormality in each intermediate device and terminal device of the alarm device. , Figure 4 shows F of the intermediate device 2-2 of the same alarm device.
5 is a time chart when an abnormality is detected in the terminal device 3-1 belonging to the intermediate device 2-1 of the alarm device. 1... Solid device, 2-1 to 2-10... Intermediate device, 3-1 to 3. -n...terminal device, 4-1 to 4-
10...Call transmitter, 8-1 to 8-10...
Call receiver, 9, 10...Response transmitter, 11.1
2...Response receiver, 17.18-1 to 18.22.
...Intermediate device abnormality instruction logic circuit, 23...Normal signal receiver, 25-11 to 25-10n, 26-1 to 2
6-10...Logic circuit for terminal device abnormality indication.
Claims (1)
れn台付属している端末装置とからなり各端末装置はそ
れぞれに割当てられた相異なる周波数の常態信号を自己
が監視しているものに異常がなければ発生し異常がある
と停止するように構成されており、上記各中間装置は互
いに相異なる周波数のm個の応答信号のうち自己に割当
てられたものを送信する応答送信機を有し、上記中実装
置は、上記各中間装置にそれぞれ対応して割当てた相異
なる周波数の呼び出し信号を順に送信する複数台の呼び
出し送信機を有し、上記各中間装置は、自己に割当てら
れた呼び出し信号を受信し自己が有する応答送信機の応
答信号と自己に属する端末装置の常態信号とを送出する
呼び出し信号受信機を有し、さらに上記中実装置は、上
記m個の応答信号を受けるm台の応答信号受信機と、上
記n個の常態信号を受ける常態信号受信機と、上記各中
間装置にそれぞれ対応して設けられており対応する中間
装置が呼び出されているときに対応する中間装置に割当
てられた応答信号を受信する上記応答信号受信機が受信
していないと出力を発生する中間装置異常指示用論理回
路と、上記各中間装置の各端末装置にそれぞれ対応して
設けられて: おり対応する端末装置が付属する上記
中間装置が、 呼び出されているとき対応する端末装置
からの常゛ 前信号を上記常態信号受信機が受信して
いないと′ き出力を発生する端末装置異常指示用論
理回路とを備えてなる警報装置。It consists of a solid device, multiple intermediate devices, and n terminal devices attached to each terminal device, and each terminal device monitors normal signals of different frequencies assigned to each terminal device. The intermediate device is configured to generate a signal if there is no abnormality and to stop if there is an abnormality, and each intermediate device has a response transmitter that transmits the one assigned to it among m response signals of mutually different frequencies. The solid device has a plurality of paging transmitters that sequentially transmit paging signals of different frequencies respectively assigned to each of the intermediate devices, and each of the intermediate devices has a The solid device has a paging signal receiver that receives the received paging signal and transmits a response signal of its own response transmitter and a normal signal of a terminal device belonging to the solid device, and the solid device further transmits the m response signals. m response signal receivers that receive the above-mentioned normal signals, normal signal receivers that receive the above-mentioned n normal signals, and are provided correspondingly to each of the above-mentioned intermediate devices, and respond when the corresponding intermediate device is called. an intermediate device abnormality indication logic circuit which generates an output when the response signal receiver that receives the response signal assigned to the intermediate device that is assigned to the intermediate device receives the response signal assigned to the intermediate device; Terminal: A terminal that generates an output when the above-mentioned intermediate device to which the corresponding terminal device is attached is not receiving the normal signal receiver from the corresponding terminal device when the above-mentioned intermediate device is called. An alarm device comprising a logic circuit for indicating a device abnormality.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16522781U JPS5871896U (en) | 1981-11-05 | 1981-11-05 | alarm device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16522781U JPS5871896U (en) | 1981-11-05 | 1981-11-05 | alarm device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5871896U true JPS5871896U (en) | 1983-05-16 |
JPH029436Y2 JPH029436Y2 (en) | 1990-03-08 |
Family
ID=29957432
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16522781U Granted JPS5871896U (en) | 1981-11-05 | 1981-11-05 | alarm device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5871896U (en) |
-
1981
- 1981-11-05 JP JP16522781U patent/JPS5871896U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH029436Y2 (en) | 1990-03-08 |
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