JPS587057B2 - Hand tie souchi - Google Patents

Hand tie souchi

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Publication number
JPS587057B2
JPS587057B2 JP50041720A JP4172075A JPS587057B2 JP S587057 B2 JPS587057 B2 JP S587057B2 JP 50041720 A JP50041720 A JP 50041720A JP 4172075 A JP4172075 A JP 4172075A JP S587057 B2 JPS587057 B2 JP S587057B2
Authority
JP
Japan
Prior art keywords
film
oxide film
depletion layer
junction
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50041720A
Other languages
Japanese (ja)
Other versions
JPS51116678A (en
Inventor
池田和子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP50041720A priority Critical patent/JPS587057B2/en
Publication of JPS51116678A publication Critical patent/JPS51116678A/en
Publication of JPS587057B2 publication Critical patent/JPS587057B2/en
Expired legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 本発明は接合端面を窒化硼素で保護した高耐圧プレーナ
素子の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a high-voltage planar element whose bonded end faces are protected with boron nitride.

従来のシリコン酸化膜でPN接合端面を保護したプレー
ナ型構造半導体装置に於いて、耐圧の低下する原因とし
ては、(1)接合面の曲面部分への電界の集中と(2)
シリコン酸化膜表面及び、シリコン酸化膜中に存在する
正電荷による界面部分への電界集中が考えられている。
In a conventional planar structure semiconductor device in which the PN junction end face is protected with a silicon oxide film, the causes of a decrease in breakdown voltage are (1) concentration of electric field on the curved part of the junction face and (2)
It is considered that the electric field is concentrated on the surface of the silicon oxide film and at the interface portion due to positive charges existing in the silicon oxide film.

この問題の解決をはかるには、シリコン基板表面の空乏
層を広げて電界集中を少くしてやればよい。
To solve this problem, the depletion layer on the surface of the silicon substrate can be expanded to reduce electric field concentration.

このために、中央電極を、酸化膜を間に挾んで基板面ま
で広げたフィールドプレートを用いた構造あるいはガー
ドリングを設けた構造が考えられている。
For this purpose, a structure using a field plate extending to the substrate surface with an oxide film interposed between the center electrode or a structure including a guard ring has been considered.

フィールドプレートを用いた構造は、空乏層の先端とプ
レートの先端の間の酸化膜に大きな電圧がかかるため実
用上余り高耐圧にする事が出来ない。
In a structure using a field plate, a large voltage is applied to the oxide film between the tip of the depletion layer and the tip of the plate, so it is practically impossible to achieve a very high breakdown voltage.

そこでシリコン酸化膜の上にさらに高抵抗層を重ねた構
造が試られているが、高抵抗層を流れるリーク電流が増
大することになる。
Therefore, a structure in which a high-resistance layer is layered on top of the silicon oxide film has been tried, but this results in an increase in leakage current flowing through the high-resistance layer.

なお、フィールドプレートをもつ構造は端子間の静電容
量が増加するために高周波用の素子には不適当であると
いう欠点がある。
Note that the structure having a field plate has the disadvantage that it is unsuitable for high frequency devices because the capacitance between terminals increases.

また、ガードリングを用いた構造は、主接合とガードリ
ング接合の距離、絶縁膜と基板との間における界面の電
荷密度、接合の深さ等、耐圧を決める諸要素に対する設
計上ならびに製造上の問題が多く、特に浅い接合に対し
ては、原理的に大きな効果は得られない。
In addition, the structure using a guard ring requires design and manufacturing considerations for various factors that determine withstand voltage, such as the distance between the main junction and the guard ring junction, the charge density at the interface between the insulating film and the substrate, and the depth of the junction. There are many problems, and in principle no great effect can be obtained, especially for shallow junctions.

この発明の目的は、絶縁膜として従来ルツボ材料などに
用いられている窒化硼素の膜を用いることにより、N型
シリコン基板表面に正の電荷を誘起させることにより、
基板表面の空乏層の幅を拡げ、高耐圧とした半導体装置
を提供することにある。
The purpose of this invention is to induce positive charges on the surface of an N-type silicon substrate by using a boron nitride film, which is conventionally used as a crucible material, as an insulating film.
An object of the present invention is to provide a semiconductor device with a high breakdown voltage by widening the width of a depletion layer on the surface of a substrate.

本発明のさらに他の目的は、窒化硼素膜の被着により、
素子切断側面まで空乏層が広がるのが適尚に限定された
半導体装置を提供するにある。
Still another object of the present invention is that by depositing a boron nitride film,
It is an object of the present invention to provide a semiconductor device in which the depletion layer extends to the cut side surface of the element in an appropriate manner.

本発明によれば、フィールドプレートによる手段のよう
な欠点もなく、浅い接合のプレーナ型に対しても有効に
耐圧の向上された半導体装置が得られる。
According to the present invention, it is possible to obtain a semiconductor device which has effectively improved breakdown voltage even for a planar type device with a shallow junction, without the disadvantages of the method using a field plate.

さらに空乏層が広がり過ぎて、不安定特性を示すことの
ない半導体装置が得られる。
Furthermore, a semiconductor device that does not exhibit unstable characteristics due to excessive expansion of the depletion layer can be obtained.

つぎに図面により本発明を詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.

第1図は本発明に関連ある技術を示し、図において、1
はN型シリコン基板であり、2はN型シリコン基板に酸
化膜マスクを用いてP型不純物の拡散により形成したP
型層である。
FIG. 1 shows a technology related to the present invention, in which 1
is an N-type silicon substrate, and 2 is a P-type silicon substrate formed by diffusing P-type impurities using an oxide film mask on the N-type silicon substrate.
It is a type layer.

3はPN接合、4は、P層形成後酸化膜を除去し、スパ
ッタリングによりシリコン表面に被覆した窒化硼素の保
護膜を示し、さらにシリコン酸化膜によりその上をマス
クし、加熱リン酸溶液に浸漬してP層2の表面部分の窒
化硼素膜を部分的に除去してP層2の表面を露出させ、
そこに電極6、裏面に電極7が形成されている。
3 shows a PN junction, and 4 shows a protective film of boron nitride that was coated on the silicon surface by sputtering after removing the oxide film after forming the P layer, and then masking it with a silicon oxide film and immersing it in a heated phosphoric acid solution. and partially remove the boron nitride film on the surface of the P layer 2 to expose the surface of the P layer 2,
An electrode 6 is formed there, and an electrode 7 is formed on the back surface.

5は窒化硼素膜の部分的エッチングマスクとして用いた
シリコン酸化膜を表わす,かかる構造の半導体装置にお
いては、シリコンに面する窒化硼素の表面には1012
cm−2オーダーの多量の負電荷が存在するため、図の
点線8,9内領域で示す空乏層11の表面が広がり、高
耐圧が得られる。
5 represents a silicon oxide film used as a partial etching mask for the boron nitride film.In a semiconductor device having such a structure, 1012
Since there is a large amount of negative charge on the order of cm-2, the surface of the depletion layer 11 shown by the dotted lines 8 and 9 in the figure expands, resulting in a high breakdown voltage.

第5図は、第1図構造のダイオードの耐圧特性向上の効
果を示す図であり、横軸のX・は接合の深さ、縦軸は耐
電圧vBにとってあり、曲線12?本発明によるダイオ
ードの特性で、N型基板1の比抵抗は30〜40Ω一α
であり、窒化硼素膜3の膜厚は5000人である。
FIG. 5 is a diagram showing the effect of improving the withstand voltage characteristics of the diode having the structure shown in FIG. 1, where X on the horizontal axis is the junction depth and the vertical axis is the withstand voltage vB. Due to the characteristics of the diode according to the present invention, the specific resistance of the N-type substrate 1 is 30 to 40Ω-α
The thickness of the boron nitride film 3 is 5000.

曲線13は従来のSiO保護膜を用いたダイオードの特
性を示し、図から明らかなとおり、従来の約600ボル
トの耐電圧が、1000〜1050ボルトと大幅に耐電
圧が向上し、かつ接合が浅い場合も耐圧低下は見られな
い。
Curve 13 shows the characteristics of a diode using a conventional SiO protective film, and as is clear from the figure, the withstand voltage has been significantly improved from the conventional approximately 600 volts to 1000 to 1050 volts, and the junction is shallow. In this case, no decrease in pressure resistance was observed.

第2図は再結合中心の多い表面層をエッチングにより除
去後、窒化硼素膜4およびシリコン酸化膜5で被覆して
さらにリーク電流を小さくした本発明に関連ある他の例
を示す。
FIG. 2 shows another example related to the present invention in which the surface layer with many recombination centers is removed by etching and then covered with a boron nitride film 4 and a silicon oxide film 5 to further reduce leakage current.

第3図は窒化硼素膜被着により空乏層が素子の側面まで
広がった場合、切断等における側面部の機械的歪のため
に特性が劣化するのを防ぐため高濃度のn+層のガード
リング10を形成したものである。
Figure 3 shows a guard ring 10 made of a highly concentrated n+ layer to prevent properties from deteriorating due to mechanical strain on the side surfaces during cutting, etc. when the depletion layer extends to the side surfaces of the device due to the deposition of the boron nitride film. was formed.

ガードリング層10があることにより空乏層の外縁線8
の終端はガードリング10に終り、したがって、特性の
不安定な切断側面まで空乏層は広がらないから、切断側
面による不安定要因は避けられる。
Due to the presence of the guard ring layer 10, the outer edge line 8 of the depletion layer
ends at the guard ring 10, and therefore the depletion layer does not extend to the cut side surface, where the characteristics are unstable, so that instability factors due to the cut side surface can be avoided.

第4図は、素子周辺近傍面は、シリコン酸化膜を被着さ
せておくことにより、望外の空乏層外縁の延長を防止し
た本発明実施例であり、第4図の例においては、望外硼
素膜3はPN接合3の露出端部から素子周辺近傍迄の空
乏層11の広がる基板面上のみに被着され、この室化硼
素膜3の上およびその外側には、この膜を包むようにシ
リコン酸化膜5が被着されている。
FIG. 4 shows an embodiment of the present invention in which an undesired extension of the outer edge of the depletion layer is prevented by depositing a silicon oxide film on the surface near the periphery of the element. The film 3 is deposited only on the substrate surface where the depletion layer 11 extends from the exposed end of the PN junction 3 to the vicinity of the device periphery, and on and outside of this boron nitride film 3, silicon is deposited so as to surround this film. An oxide film 5 is deposited.

この第4図の実施例構造においては、空乏層11の外縁
線8は素子周辺部のシリコン酸化膜5に終り、切断側面
には表われないので、第3図に示した本発明に関連ある
技術の場合と同様に、空乏層が不安定な切断側面に露出
することが防がれて素子耐電圧特性の不安定きなること
はない。
In the structure of the embodiment shown in FIG. 4, the outer edge line 8 of the depletion layer 11 ends at the silicon oxide film 5 at the periphery of the device and does not appear on the cut side surface. As in the case of the technology, the depletion layer is prevented from being exposed on the unstable cut side surface, and the device withstand voltage characteristics do not become unstable.

上述のとおり本発明の半導体装置は、接合端面保護の絶
縁膜を従来のシリコン酸化膜の代わりに窒化硼素膜にす
ることにより飛躍的に耐電圧を向上せしめられており、
特にガードリングによる効果が余り表われなかった浅い
接合の素子に対しても何等の差別なく有効に耐圧が向上
されており、また、窒化硼素膜の被着範囲を適当に制限
し、シリコン酸化膜との組合せにより空乏層の望外の広
がり過ぎを抑制して、切断側面による悪影響が避けられ
ているという、勝れた効果を有するものである。
As mentioned above, the semiconductor device of the present invention has dramatically improved withstand voltage by using a boron nitride film instead of the conventional silicon oxide film as the insulating film for protecting the junction end face.
In particular, the withstand voltage has been effectively improved without any discrimination even for elements with shallow junctions where the effect of the guard ring was not so apparent. This combination has the superior effect of suppressing the undesired excessive expansion of the depletion layer and avoiding the adverse effects of the cut side surfaces.

さらに窒化硼素膜は熱電導がよいので熱放散特性が特に
改善されるという効果も備えている。
Furthermore, since the boron nitride film has good thermal conductivity, it also has the effect of particularly improving heat dissipation characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

図1図は本発明に関連のある半導体装置の一例の断面図
、第2図は表面をエッチングしてさらに性能を高めた場
合の一例の断面図、第3図はガードリングを設けた例の
断面図、第4図はシリコン酸化膜で素子周辺傍面を覆い
この内側に室化硼素膜を設けた本発明実施例の半導体装
置の断面図、第5図は本発明に関連ある第1図の半導体
装置の効果を説明するための曲線図、である。 図において、1はN型シリコン基板、2はP型不純物拡
散層、3はPN接合、4は窒化硼素膜、5はシリコン酸
化膜、8は空乏層の外縁線、9は空乏層内縁線、11は
空乏層を示す。
Figure 1 is a cross-sectional view of an example of a semiconductor device related to the present invention, Figure 2 is a cross-sectional view of an example in which the surface is etched to further improve performance, and Figure 3 is a cross-sectional view of an example in which a guard ring is provided. 4 is a sectional view of a semiconductor device according to an embodiment of the present invention in which a silicon oxide film covers the periphery of the element and a boron chloride film is provided inside the silicon oxide film, and FIG. 5 is a diagram of FIG. 1 related to the present invention. FIG. 3 is a curve diagram for explaining the effect of the semiconductor device of FIG. In the figure, 1 is an N-type silicon substrate, 2 is a P-type impurity diffusion layer, 3 is a PN junction, 4 is a boron nitride film, 5 is a silicon oxide film, 8 is an outer edge line of the depletion layer, 9 is an inner edge line of the depletion layer, 11 indicates a depletion layer.

Claims (1)

【特許請求の範囲】[Claims] 1 N型基板にP型不純物を拡散して形成されたPN接
合を有し、この接合端面が絶縁膜にて保護されたプレー
ナ型半導体装置において、該縁膜保護膜のうち素子周辺
部の保護膜はシリコン酸化膜からなり、その内側の主と
して空乏層の広がる部分の保護膜は室化硼素膜からなる
ことを特徴とする半導体装置。
1. In a planar semiconductor device that has a PN junction formed by diffusing P-type impurities into an N-type substrate, and the end face of this junction is protected by an insulating film, protection of the peripheral part of the element in the edge film protective film is used. 1. A semiconductor device characterized in that the film is made of a silicon oxide film, and the protective film on the inner side mainly in a portion where a depletion layer spreads is made of a boron nitride film.
JP50041720A 1975-04-05 1975-04-05 Hand tie souchi Expired JPS587057B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50041720A JPS587057B2 (en) 1975-04-05 1975-04-05 Hand tie souchi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50041720A JPS587057B2 (en) 1975-04-05 1975-04-05 Hand tie souchi

Publications (2)

Publication Number Publication Date
JPS51116678A JPS51116678A (en) 1976-10-14
JPS587057B2 true JPS587057B2 (en) 1983-02-08

Family

ID=12616247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50041720A Expired JPS587057B2 (en) 1975-04-05 1975-04-05 Hand tie souchi

Country Status (1)

Country Link
JP (1) JPS587057B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20120836A1 (en) 2012-05-15 2013-11-16 Rinaldo Franceschini DEHYDRATION EQUIPMENT FOR CENTRIFUGATION OF FOOD WASTE

Also Published As

Publication number Publication date
JPS51116678A (en) 1976-10-14

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