JPS5870408A - Transmitting system for pulse code modulation signal - Google Patents

Abstract

PURPOSE:To simplify an error correcting device required for correcting an error, by substituting a specified information for an error or information which has been decided to have possibility of an error, and executing an error correction. CONSTITUTION:An error correcting signal is added by an encoder 6 after convering to a series code, an error detecting signal is added by a generating circuit 8 for an error detecting signal through an interleaving circuit 7, and thereafter, it is recorded in a VTR11 through circuits 9, 10. When reproducing, a PCM signal is decided as to existence or absence of an error by an error detecting circuit 14, the PCM signal is supplied to a deinterleaving circuit 15 together with a result of decision, is rearranged to its original order and is corrected by a decoder 16 if the error can be corrected. In case when there is no error, or in case when an error has been corrected, the PCM signal is supplied to D/A converters 18L, 18R, but in case when it is impossible to correct the error, said signal is supplied to a serial/parallel converter 17 through an error correcting circuit 19, and is outputted from the D/A converters 18L, 18R.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides, for example, when recording and reproducing a digital audio signal obtained by converting an audio signal into PCM.
The present invention relates to a PCM signal transmission system equipped with an error correction function for correcting errors occurring in recorded and reproduced signals.

Conventionally, in an audio signal PCM reproduction system,
A method has been adopted in which the presence or absence of an error in the PCM reproduction signal is detected by separately providing a tinterleave circuit (RAM) for error judgment pulses in the error correction device. The circuit had the disadvantage that the two-circuit configuration was complex and expensive.

Here, the present invention has an error due to the error detection device. Alternatively, the present invention provides a PCM signal transmission method that aims to simplify the error correction device necessary for performing error correction by replacing information determined to have a possibility of error with specific information. It is something.

Hereinafter, two embodiments of the present invention will be described based on the drawings. 1st
2 and 2 are schematic configuration diagrams of a recording and reproducing system having an error correction method suitable for using an error correction device, and show a case where a VTR is used as a recording medium. In the same figure,
(IL) and (1R) are terminals to which the left channel and right channel signals of the stereo audio signal are respectively supplied, and these signals are respectively supplied with a low pass filter (2
L) and (2R), sample and hold circuit (3L)
and (3R).

PC via A/D converter (4L) and (4R)
M modulated.

Since the output of this A/D converter (4T, ) (4R) is a parallel code, it is converted into a serial code by a parallel-to-serial converter (5), and an error correction signal is added to it by an encoder (6). After that, the signal is supplied to the interleave circuit (7), and after the error detection signal is added to the error detection signal generation circuit (8), it is sent to the time base compression circuit (9) and the synchronization signal separation circuit OQ.
is recorded on the VTR θl). Here, the synchronizing signal separation circuit (10) and the VTR (11) convert the PCM signal into the same form as the video signal.

Next, during playback, the signal generated from the VTR (+1) is supplied to the time axis expansion circuit 0 through the synchronization signal separation circuit 04, and the original continuous PCM signal is obtained from this output. . Furthermore, the PCM signal is processed by an error detection circuit (14
) to determine whether there is an error.

Together with this judgment result, the PCM signal is supplied to the tinterleave circuit 0!5) and rearranged in the odd order of the binary signals. Corrected.

Here, if there is no error, or if the error is correctly corrected, it passes through the serial/parallel converter 07) and then the D/A converter (
The PCM signal is supplied to 18T, ) and 18R, but if an error cannot be corrected, the PCM signal is supplied to the serial/parallel converter a'71 via the error correction circuit 0. This D
The outputs of the /A converters (18L) and (18R) are passed through low-pass filters (2OL) and (2OR), respectively, and a left channel signal and a right channel signal are obtained at output terminals (21L) and (21R), respectively.

Next, the operation of the recording/reproducing apparatus having the above configuration will be described in detail. Now, assume that A/D converters (4L) (4R) that convert an analog signal into an N-bit tintal signal are used. As a result, the number of stages that can be obtained, that is, the number of quantization M, is MV. Assuming that the input signal is a sine wave whose amplitude has a peak-to-peak ratio of ■, the dynamic range D can be approximately determined by the following equation.

: o = -6X N +1.75 (aB) For example.

In case of N-16 quantization number M=65535 D-4-9
7,76d, BN-15 Quantization number M=3276
8 peaks is 91.76 dB. Therefore, in a high quality audio signal PCM recording and reproducing system, generally N=
175 is used.

In addition, the output signal of the A/D converter (4T,) (4U can express both positive and negative audio signals).
Generally offset binary, 2'S conbriment,
A binary system called folded binary is used.

For example, in the case of offset binary, N=16 A/
The output signals of the D converters (4L) (4R) are as follows.

10v... 111111111111111
10V-KO...1111111111111110
0... ・1oooooooooooooooo.

-v-oooooooooooooooo.

5- The A/D converter thus obtained (4T,) (4
Output signal 1 of R): constitutes one word with N bits and is supplied to the encoder (6) to which an error correction signal is added. As an example of such an encoder (6), Let's consider a method that can ask the parity check code corresponding to each bit.

Now, the PCM signal of the right channel at a certain time is R1,
Let it be the left channel PCM signal QL+. This 1+@
, the parity check signal obtained by the encoder (6) is P
1, R1■L1 = Pi. The interleave circuit (7) transfers the PCM signal of the right channel and the PC of the left channel.
The M signal and the parity check signal 71 are delayed by different times.

For example, if the delay time of the right channel PCM signal is −0, the delay time of the left channel PCM signal is 2, and the delay time of the parity check signal is 2, then the output of the ink-leave circuit (7) is For example, if 14 signals consisting of the words R4Lk and R2 are simultaneously applied.

Thereafter, an error detection signal is added to the output signal of the ink-leave circuit (7) by an error detection signal generation circuit (8). This error detection signal is 1 normally cRcc (cycllc
Red, Undancy Check Code) is used. It's ox.

1. At this time, the error detection signal added to the [~LkP2k] signal is set to 01. Then, the time axis compression circuit (9) compresses this I↓I signal by a time of 111+, and when the synchronization signal is added to the synchronization signal addition circuit θ (j), it is recorded on the VTR (II). The format of the final PCM audio signal is as shown in FIG.

On the other hand, in the case of two-sided raw silk, after detecting the synchronizing signal in the synchronous signal detailed circuit (1'4) for the endogenous signal from the VTR (lυ), the 2 time axis expansion circuit (1'4) directly converts the original PCM signal to the original PCM signal. In addition, it is checked whether an error has occurred in the recording/reproducing system using an error detection signal from the error detection circuit (14).

” - As stated (When detecting errors using CRCC, there is a limit to the error detection ability, but it is possible to determine with a very high probability whether or not an error has occurred in the signal [R1LkP2kC1]). However, with this method, it is not possible to determine where the error is even by changing its location. Therefore, for example, if there is an error in the word R1, CR
If it is determined that there is an error as a result of the C check,
Even if there is no error in Lk and P2k, it is determined that there is a possibility of error. That is, the result of ORO check.

If it is determined that there is an error, a flag of '1'' is added to each word in R1, :r, indicating that there is a possibility of an error in each word in R2.
Let's set up g.

Thereafter, nine interleave processing is performed in the nine interleave circuit 05). At this time, it is necessary to set the flag together with the Ushidaya word. As a result, R+
, Lj, and Pi, with flags attached to the valley words, respectively.

Due to the characteristics of the parity check code, if an error does not occur in only one word, the error can be completely corrected.

For example, if an error El occurs in the word R4, the syndrome S1 becomes 5i = R4 ■ E1 ■ L1 ■ E1 in P, and it is known from the flag that the word in which the error occurred is a pattern R1. , it can be seen that it can be corrected using J'L.

What is important at this time is that the correction ability is not related to the pattern of errors that occur in the word R1, and that the pattern ``1'' can be corrected in the same way.

For example, if fl and ag are 1'' and there is one word that is determined to have a possibility of error, it is obvious that there may or may not be an actual error.

Here, it is important if fl and ag are "1" in two words. It is clear that the probability in such a case is lower than when the flag is in one word, but such a case cannot be corrected by the Haritite check code 1.

=9- On the other hand, even if f lag is "1", no error may occur. Let's consider this point further.

Now suppose there are errors in two words. And R
If there is an error of ET on 4 and R2 on Li, then
Syndrome S1 becomes 5i=Ei*E2, and since Ei and R2 cannot be determined individually, correction cannot be made.

Next, whether there is actually an error El in one word R1,
When there is no error in the other word L1.

Jintrow input S1 becomes 1 in Si=, and it should be possible to correct the word R1 using ET, but if both flags are set in R4 and Lj, the decoder Q61 will think that there is an error in R1. Since it is not possible to determine whether there is an error in , or Ll, the error cannot be corrected after all.

Furthermore, there is actually no error in either words R+ or Li, and the combination becomes -10--Sl = 0. Therefore, regarding this error correction, fl is applied to R1 and Ll.
It may be possible to determine that there is no error even if ag is set, but if this is done, the same pattern of error occurs in R1 and Ll.

If this error is overlooked, a click sound will be generated in the reproduced audio signal, resulting in a serious defect.

Therefore, in gaintal audio systems that require high quality, in order to minimize the occurrence of such lick sounds, two cases are determined to have a possibility of an error even if there is actually no error. , if there are two or more words, it is wise to assume that there is an error and move on to correction.

As is clear from the above, if the CRCC determines that there is a possibility of an error, even if there is an actual penalty! It has become clear that the next operation must be executed regardless of whether there is an error or not, and the error pattern has no relation at all.

In order to perform the above error correction, as described above, it is necessary to perform gain interleave processing on each word as well as on a flag indicating whether or not there is a possibility of an error. Therefore, only two tinterleaving circuits are required, one for each word 1 and one for fl and ag, but if this nine interleaving is complex, a RAM is usually used to perform the nine interleaving. Even if one bit is sufficient, it is necessary to prepare a dedicated RAM for the flag, which causes an increase in the scale of two circuits, higher prices, and lower reliability.

Therefore, if RAM for flags and RAM for words could be used together, this problem could be solved, but as mentioned above, in a commercial quality gain audio system, one word is It is generally composed of 16 bits. On the other hand, commercially available RAM has an input number of 8 bits or 16 bits,
When one bit of the flag is determined to be 17 bits I, there is no RAM on the market that exactly matches this.

Therefore, when an error is detected by C, RCO, it stops setting the flag, and there is! +: The pattern of f′iJl will be applied. However, the pattern selected at this time should be one that rarely occurs in normal Oteio ships.

A secondary method can be considered as a method of selecting such a pattern.

(1) Bit pattern D indicating the maximum positive or negative level
Choose ma7. In normal music, the probability of this pattern occurring is almost zero. This is because if a sound that is even slightly louder than this comes in, no more sound can be transmitted, so by assuming that all of these are at Dmax, they will be reproduced as nine cut sounds as shown in Figure 4. This is because the sound will crack and become unbearable. Therefore, it is necessary to keep the actual maximum level of music below the system's capacity. Therefore, actually]
) ITIax sounds are rarely recorded or played back.

-13- Therefore, if -Dmax is recorded, l1nax should be used as the error determination pattern.

The word is determined to have an error, but if there is no possibility of an error in the other words, that is, if the pattern in the other mode is not Dmax, the sound is correctly played back to Dmax.

If there is a possibility of error in other words as well, i.e. Dm
When two ax patterns appear, correction is required, but to avoid this, in advance, when a Dmax pattern appears on the decoder (161 side), use a lower level pattern, and in the recording/reproducing system. , Dmax may be set as an inhibit pattern that does not appear in the data signal.

In this way, if it is determined that there is a possibility of an error in the data signal of the PCM signal, the error determination flag is set.
Correct correction is performed by applying the maximum level bit pattern Dmax instead of , but if the error correction code is a parity check code as shown in this example, there is a possibility of error 9 in the error correction code. Even if it is determined that the flag is −14=, Dmax cannot be used. 11I] If so.

This is because even if the take signal is not 1:)max, the parity check code may have the same pattern as Dmax. Therefore, in this case, it is necessary to separately provide fl and ag for the abbreviated sign. usually.

Since the number of error correction codes is small compared to the number of take signals, only a small amount of RAM is required, and the above-mentioned effects can be sufficiently improved.

As a result, if there is no error in the output of the post-coder (IO), if the error is correctly corrected, then the serial-to-parallel converter (+7
After converting from serial code to parallel code in step 1, D/
It is supplied to the A converter (18L) (18R), but if error correction is not possible in the decoder θ0, it passes through the error correction circuit board and is corrected by the method described above, and then is sent to the serial/parallel converter 07. ). Until now, this D/A converter (
The outputs of 18T, ) (18R) are passed through low-pass filters (2OL) and (2OR), respectively.The left channel signal and right channel signal of the stereo audio playback signal are output from the output terminals (21L and 21R). can get.

As described above, the present invention allocates a specific pattern to data determined to be erroneous or to a take determined to be erroneous, and forcibly allocates all of the 16 bits constituting one word. 1" and then performs nine-interleaving processing to detect this "1" and use this as a means of determining error take. Therefore, the conventional dinterleave circuit (usually RAM) dedicated to error correction results is used.
There is no need to provide separate circuits, which simplifies the two-circuit configuration and improves reliability.

Also, the number of Douji transformation steps will be reduced by one when changing the take pattern, but if you keep this as the maximum level pattern, you will actually have two problems.

[Brief explanation of drawings]

The drawings relate to one embodiment of the present invention, and FIGS. 1 and 2 are configuration diagrams when the error correction device is applied to a recording and reproducing device;
FIG. 6 shows a PC for recording and playing back on the VTR shown in FIGS. 1 and 2. FIG. 4 is a waveform diagram showing the structure of the M-coded audio signal, and FIG. 4 is a waveform diagram of the audio reproduction signal processed at the maximum positive level Dmax. In the drawing, (14) is an error detection circuit, 01 outbound J deinterleave circuit, 06) is a decoder, and (1!it is an error correction circuit. Patent applicant: Z-Larue Co., Ltd. 17-

Claims (2)

[Claims] (1) In an error correction method in which error detection results are gain interleaved with data signals and then error correction is performed, a specific pattern is assigned to data determined to be an error or data determined to have a possibility of an error. A PCM signal transmission system characterized in that detection is performed after dinterleave processing and used as means for determining error data. (2) In the decoder, when a specific pattern occurs in the data, it is changed to the next quantization step and transmitted.
PCM signal transmission method described in section.