JPS5870334A - Automatic clearing circuit - Google Patents

Abstract

PURPOSE:To output clear signals surely regardless of the rise time duration of the power supply voltage, by providing a pack gate bias circuit which works in response to the supply of the power. CONSTITUTION:The power supply voltage VDD is applied and exceeds the threshold voltage of an MOS transistor TR421 of a gate bias circuit 41. At a result, the TR421 is turned on. In this case, the threshold voltage is applied to the gate of an MOS TR11 by the pack gate bias effect of the circuit 41. Thus the TR11 is turned off. The TR11 is turned on when the voltage VDD rises up to a level approximately two times of the threshold voltage. At the same time, a capacitor 12 is charged, and the voltage Va rises gradually at an input terminal 14 of an inverter 13.

Description

[Detailed Description of the Invention] The present invention particularly relates to an auto clear circuit (
Two matters.

In general, digital circuits used in small electronic computers, etc. (2) need to be cleared, or initial reset, when the power supply voltage is turned on, in order to prevent excessive operation. An auto clear function that operates when voltage is applied and outputs an initial reset signal (hereinafter referred to as Clear I No. 8).
clear) circuit.

This auto-clear circuit conventionally consists of two circuits, as shown in Figure 1 (2).
For example, a P-channel M (JS transistor 1) and a capacitor 12 are connected in series (two connected, this P-channel MO8) transistor (hereinafter simply referred to as a MOS transistor) 11 has its gate grounded. Then, the inverter 130 input terminal 14 is connected to the common connection point a of the transistor 1 (M08, M08 transistor 1) and the capacitor 12, and this inverter 13 is connected between the power supplies (between VDD and ground) (two P channel and N channel IVIO8). 15.16 are connected in series (two are connected, this MOS) Kunjis, Ri1
The gates of both transistors 5 and 16 are commonly connected to the input terminal 14 (-). From the output terminal 17 of this inverter 13, that is, the common connection point of the MOS transistors 15 and 16, a clear signal 1-9CL is output.

When the power supply voltage VDD is applied to this auto clear circuit as shown in FIG. It will be in a charging state. Therefore, the voltage Va at the input terminal 14 of the inverter 13 rises and increases gradually (2). At this time, that is, when the voltage Va is at a low level, the fVI of the inverter 13
Since the OS transistor 15 is in the on state and the 1ViOS transistor 16 is in the off state, "1" is output from the output terminal 17.
” A clear signal UL is output. voltage Va
When exceeds the inverter 130 circuit threshold voltage V thc, the inverter 13 performs an inversion operation, that is, the M(JS) fungistor 15 is turned off and the MOS transistor 16 is turned on, and the clear signal CL becomes "0" and is released. be done. During the period when the clear signal CL is rising, that is, when it is "1", the digital circuit (not shown) to which the clear No. 4g CL is supplied is initial reset.

In this way, the clear signal CL is outputted from the inverter 13 for a certain period using the period when the power supply voltage VDD rises to a certain voltage, and an initial reset is performed. However, in the conventional auto clear (b) path as described above, as shown in FIG.
If the rise time of D is slow, first, the power supply voltage VDD becomes the threshold voltage Vt of the MOS transistor 11.
b. When the voltage Va exceeds 1, the capacitor 12 enters a charged state, and the voltage Va gradually increases from the point td in FIG. 3 to the power supply voltage VDD. At this time, inverter 13
Then, the power supply voltage VDD is the current hold voltage v th,! of the MOS transistor 15. Since the input voltage .m' voltage Va is charged to the power supply voltage VDD in the vicinity of +, the MOS transistor 15 may not turn on.

Therefore, in this case, the output terminal 17 of the inverter 13 does not output the clear signal CL, which is "1".
It has the disadvantage that it cannot perform initial reset of the digital circuit.

This invention was made in view of the above-mentioned circumstances, and is a circuit that outputs a clear signal using the rise period of the power supply voltage. It is an object of the present invention to provide an auto clear circuit which can stably initial reset a digital circuit by outputting a C clear signal.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows the configuration of an auto clear circuit according to an embodiment (2) of the present invention, between the power supply (between VDD and ground).
(For example, a P-channel M(,)S transistor (hereinafter simply referred to as MOS) transistor) 11 and a capacitor 12 are connected in series (in contrast, a back gate bias voltage is applied to the MOS transistor 1). A pack gate bias circuit wJ (hereinafter referred to as a gate bias circuit) 41 is provided to apply a pack gate bias circuit.
MOS transistor 42 which sets electrical characteristics such as threshold voltage similar to Tobaba. The gate of this MOS) Kunister 42° is grounded. Sara (2IVI)
O8) Source of transistor 421 and above 1vi OS
The gate of transistor 11 is connected. Here, ~1
When the 0S transistor 421 is a P-channel MOS transistor, between the drain of the P layer and the NN substrate (two voltages VDD
is applied, so that the reverse diode 43 consisting of the drain and the root is valved so that the power supply voltage VDD is I'vlO8) to the gate of the run raster 1 (2 is supplied (2). Note that the gate bias jgl path 4) C: Depending on the requirements, multiple stages of MOS) transistors 42. to 42n are connected in parallel (two stages, the gate of the previous stage MOS) Kunister 421 and the source of the subsequent stage MOS) transistor are connected, and the last stage MOS) transistor The gate of 42n is grounded. For example, an input terminal 14 of an inverter 130 of a waveform shaping circuit is connected to a common connection point a between the MOS transistor 11 and the cavitation valve 12. This inverter 13 is connected, for example, between the power supplies (two P-channel and N-channel MOS transistors 15 and 16 are directly connected to each other), and this M
(JS) An output terminal 17 is connected to the common connection point of the fungistors 15 and 16, and an input terminal 14 is commonly connected to each gate of the MOS transistors 15 and 16.

The auto clear circuit configured in this manner (2) The threshold voltage of the transistor 42. When voltage exceeds vth, 2 (approximately the same value as voltage vth, ,) (t in Fig. 3),
d, ), M OS ) transistor 42 is turned on. At this time, the MOS transistor 1 is in the OFF state because the voltage Vtb, □ is applied to the MOS transistor 22 due to the bank gate bias effect caused by the gate bias circuit 4. Voltage V
When the DD voltage rises to 2Vtb, 2 (t in Figure 3)
d2), the MOS transistor 1 is turned on and the capacitor 12 is charged. Therefore, the voltage Va at the input terminal 14 of the inverter 13 starts to rise gradually.

In this way, even if the rise of the voltage VDD is slow, the bank gate bias effect (MOS transistor 42) of the gate bias circuit 41 takes the time for the bank gate bias effect (MOS) run raster 1 of the gate bias circuit 41 to turn on. The voltage vth, , min, i.e. [td2 t'
It can be delayed by +J. Therefore, the rise time of the voltage Va, which is the input voltage of the inverter 130, can also be delayed, so that the power supply voltage VDD becomes the voltage Vth of the MOS transistor 15 of the inverter 13.

When it exceeds the voltage Va, the voltage Va is at a low level, and the MOS transistor 15 is turned on. Due to this operation of the M (J8 transistor 15 (MOS transistor 16 is off) Circuit threshold voltage thc
Above (in the second case, the inverter 13 is inverted operation, that is, MOS), the transistor 15 is off, and the MOS transistor 1
6 is turned on, and the clear signal C1 is released (rOJ
) to be done. Note that when a plurality of MOS transistors 421 to 42n of the gate bias circuit 41 are provided, the delay time [td, ~td,) is approximately equal to that of the MOS transistors 4
When the voltage Vth, which is an integer multiple of the number of 21 to 42n (n*Vth, , ), that is, the power supply voltage ratio VDD becomes approximately "(n1i) ・Vth42J l=, the MOS transistor 11 is in the on state. becomes.

FIG. 5 shows another embodiment of the present invention, in which the source of the MOS transistor 11 and the voltage VDD are used instead of the auto-clear circuit shown in FIG. A diode circuit 5I is provided between them. For example, this diode circuit 5 includes a plurality of diode circuits 52. 52n are connected in series, and the gate of the MOS transistor 1 is grounded.

Auto clear like this! ! When the electric voltage VDD is applied to the circuit C2, the voltage VDD is applied to the diode 52. of the diode circuit 51. The number of ~52n (=the corresponding output level % tE is applied to the MOS) is applied to the source of the transistor 11. That is, diodes 521-52
If the voltage between each anode and cathode of n is the voltage Vr, the power supply voltage VDD is the voltage vt of MOS transistor 1.
h1. Even if it rises to (td in Figure 3), IV
IO8) Runraster 1 source is JVth, -
Since a voltage of n@VpJ is applied, the MOS transistor 11 is in an off state. Furthermore, (=, the source voltage VDD rises, and the voltage VDD becomes MOS, including the voltage drop (n VF) of the diode circuit 510'), the voltage vth of the fungistor 11, or more (as shown in Fig. 3) td2),
MOS) transistor 11 is turned on, and capacitor 12 is turned on. However, 'power supply' turtle Lf:
When VDD exceeds the voltage vth, and M
OS) Since transistor 11 is off, inverter 13
There are cases where the voltage Va, which is the 0 input voltage, is at a low level,
Inverter 130M0S transistor 15 is turned on (MOS) transistor 16° is turned off), and inverter 13
The clear signal CL which is "1" is outputted from the output terminal 17 of
is released (rOJ) as in the above embodiment.

Further, as another embodiment of the present invention, in the auto clear circuit shown in FIG.
] and each threshold hold voltage Vth of the inverter 130 MO8 transistor 15, , Vth, Ilwo [l Vthl, l> I vth,, H) as follows.
This shows the case of Nu. That is, when manufacturing an auto clear circuit which is an integrated circuit, the MOS transistor 11.1
5 valley threshold voltage Vl) III-Vthl
5 MOS transistor Qs 911, J By a known manufacturing method such as adjusting the channel width and channel concentration of 5, the voltage l Vthu l becomes the voltage l vth
l, set so that it is larger than l. therefore,
In such an auto clear circuit, t = voltage VDD
When the voltage VDD is turned on, the voltage VDD gradually rises (if it rises to the voltage vth, , the MOS), the voltage Vth of the transistor 11 is at a lower level, so the MOS
The transistor 11 is in the off state.At this time, the voltage Va, which is the input voltage of the inverter 13, is at a low level, and the MOS transistor 15C2 is almost at the voltage Vt.
i.

Since the voltage VDD is applied, the MOS transistor 15 is turned on. Therefore, inverter 13
A clear signal ct, f which is "1" is output from the output terminal 17 of
Ji is output. Also, the release of the clear signal CL CrOJ
) is the same as in the above embodiment.

In addition, in the above embodiment (2), the MOS transistor l 1
, 15 , 42. ~42n is P channel/l/IVI
In the case of an OS transistor (I mentioned two, of course, the same effect can be obtained in the case of an N-channel M (J8 transistor).

As detailed above, according to the present invention (-), a clear signal is output using the rising period of the power supply voltage [!l
! Even if the rise time of the power supply voltage is slow, the MOS transistors of inverters etc.
can output a clear signal. Therefore, by using this clear signal, the initial reset of the digital circuit can be performed stably.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional auto clear circuit, FIGS. 2 and 3 are diagrams explaining its operation, FIG. 4 is a block diagram of an auto clear circuit according to an embodiment of the present invention, and FIG. 5 11. 15, 42I to 42n... P channel MO8 transistor, 12... Capacitor, 16... N channel MOS transistor, 52 .~52n...Diode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 4 Figure 2 Figure 3 Figure 5

Claims (3)

[Claims] (1) The first ones are connected in 11 rows between the power supplies. The operation of a 1gl path consisting of a transistor (MOS) and a capacitor and at least one second MOS) transistor to which the voltage across the terminals of this capacitor is supplied as an input signal (2) and at least one third MOS transistor for applying a pack gate bias voltage to the gate of the first MOS transistor, the back gate bias operating in response to the supply of power. An auto clear circuit characterized by comprising a circuit. (2) A transistor and a capacitor between the power supplies (the first MOS connected in two rows C), and a voltage between both terminals of the capacitor is supplied as an input signal, and at least one transistor is supplied with the above-mentioned power supply. means for outputting a clear signal according to the operation of a circuit consisting of a second MOS) transistor; and at least one diode connected in series (two connected) between the first MOS) transistor and the power supply; An auto clear circuit characterized by comprising: (3) The first M provided by connecting two Cs in series between the power supplies
A clear signal is output in response to the operation of a circuit consisting of an OS) transistor and a capacitor, and at least one second MOS) transistor to which the voltage between both terminals of the capacitor is supplied as an input signal and the above power is supplied. and means for setting the threshold voltage of the first MOS transistor to be higher than the threshold voltage of the second MOS transistor.