JPS5869438A - Device for monitoring and protecting no-break power source ac switch - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention relates to a monitoring and protection device for AC switches used in parallel redundant type uninterruptible power supplies, and is made by connecting in parallel AC switches with exactly the same configuration to existing 4IK AC switches. Moreover, even when the power supply is in constant operation, the power supply side can perform a specified test on the AC switch without any influence on the load side. The aim is to provide a monitoring protection device.

As is well known, an uninterruptible power supply with parallel redundancy consists of multiple sets of inverters, and if any inverter fails, the inverter of the failed machine is disconnected and the load is shared by the healthy machine. Although it is placed on the inverter side to continue supplying a predetermined power, an AC switch constructed by connecting thyristors in antiparallel is responsible for disconnecting a faulty machine and switching over to a healthy machine. Therefore, an AC switch is required to have a highly reliable circuit configuration that is as simple as possible.However, when testing the operation of such an AC switch during α operation and OFF operation, conventional methods For example, some people say that a fault diagnosis is performed to check whether an AC switch is operating normally by cutting off the load to a specified periodic inspection port in advance. It is easy to cause problems such as not operating at the point when it actually should be operating (there is a big problem in terms of reliability).Therefore, fault diagnosis of the current switch is possible even when the uninterruptible power supply is in constant operation. There is a desire to realize a diagnostic system, but since conventional AC switches have only one set of AC switches for each inverter, it is difficult to
If we were to perform a test to confirm the operation of a certain AC switch, other inverters would have to bear the load being shared, and the inverter whose load sharing would increase would experience a significant load change. The effect of the load side is extremely large, such as a temporary drop in the output voltage (and cannot be used in practice at all).

The present invention was invented in view of this point (in particular, the present invention is based on the fact that a new AC switch is installed individually in addition to the existing AC switch, and that the forced arc extinguishing circuit of the AC switch is the same as the existing AC switch. The main feature is that a predetermined failure diagnosis can be carried out by using the system as it is, and it will be described in detail below based on each embodiment shown in the gI diagram and FIG. 2.

FIG. 1 shows a specific example of a circuit when this embodiment is applied to an arbitrary AC switch. In this embodiment, 1 is an existing AC switch, which is constructed by connecting thyristors S and xgs in antiparallel. Reference numeral 2 indicates an AC switch which is a main part of the present application, and this AC switch is constructed by connecting thyristors to B4 in antiparallel as shown in the figure, and is connected to the existing AC switch y f K.
connected in parallel. 5 is an ignition circuit for igniting the existing AC switch 1; similarly, 4 is an ignition circuit for igniting the newly added AC switch 2; 51 to 5■ are each AC switch 1- 2 is a current detection current transformer for extracting the alternating current output current, and 6□ to 1 are not shown, but it is a current detection circuit for extracting a desired current detection signal from between its terminals. This is an arc-extinguishing thyristor for forcibly extinguishing the AC switch, ■ is an ignition circuit for firing the arc-extinguishing thyristor 7, and 9 is an isolation transformer for taking out the AC output power voltage of the uninterruptible power supply. 10 is a rectifier circuit composed of a diode rectifier for rectifying the AC input power supply voltage,
The commutating capacitor C, the commutating reactor L, the commutating diode D, and the charging current suppressing resistor, respectively, constitute an extinguishing circuit for forcibly extinguishing the AC switch.

The embodiment shown in Fig. 2 shows an example of a circuit for diagnosing faults in the α operation and OFF operation of the AC switch constructed as described above. 12 is a detection circuit for detecting the failure state of each unit inverter that constitutes the power supply, such as commutation failure of the inverter or overvoltage of the DC intermediate circuit. In this case, a flip-flop circuit generates a "1" output at the output terminal, and conversely, a "river" output occurs at the output terminal if it is in a faulty state.Ta and 14°1s are the output signals of the flip-flop 1 and 17 are NAND gates that take an AND condition with the output signal of a counter, which will be described later.
18 is a gate circuit for giving a gate signal to j.
A monomulti that operates depending on the way the ONAND gaiter comes out, ■
1 is a gate circuit K that provides a gate signal to the arc-extinguishing thyristor 7 shown in FIG. So, for the catfish, use the black signal and switch 21.
ZS is a gate that takes an AND with the contact output of , and counts a predetermined group of clock signals, and each time this group of signals is input, a signal that becomes Kl'l)J is sent to the output terminal Q.
, , Q, K are the comparators for comparing the current detection signal of each AC switch and the reference value shown in Fig. 26
This is a flip-flop V-flop circuit that operates with an output of -27.

To describe the operation of this embodiment configured as described above, assuming that the uninterruptible power supply is operating normally and the prescribed failure diagnosis test is not performed, the first flip-flop l1 circuit! The output signal which becomes "1" from 2 is further transmitted to each output terminal Q1゜Q! of counter n. 13-15 K are respectively derived from each NAND gate, and the logical AND condition of each NAND gate is satisfied and the gate is closed, thereby gate circuit 16-1
? A signal called rOJ is input to the mono multi-ill K, and the gate circuits 16-17 operate, and a desired gate signal is applied to each AC switch 1-2 shown in FIG. 1 via the ignition circuit 3-4. , thyristors 81 to B of each AC switch
4, a desired constant voltage and constant frequency power is supplied to the load.

On the other hand, the third gate circuit 19
Since the output of the switch has dropped to zero, it is in a non-operating state, and the arc-extinguishing thyristor S shown in FIG. 1 is in a non-conducting state.

The commutating capacitor C shown in FIG. 1 is connected via the path of insulation transformer 9 → rectifier circuit 10 → charging current suppressing resistor R → commutating capacitor -y-c during the steady state of the uninterruptible power supply.
The battery is charged to approximately the power voltage value according to the polarity shown. During such a steady state, if the unit inverter of the uninterruptible power supply fails for some reason such as commutation failure, the AC switch 1 shown in FIG. 1 is connected to the unit inverter of this failed unit.
-2.

In this way, failure detection circuit 11 detects failure of the unit inverter using a well-known method, and when this detection signal is input to flip-flop 12, an open signal is output to the output terminal of flip-flop 12. 13-14 NAME) gate, the output signal of the flip-flop 12 is leap, and the signal output from the output terminals 91 to Ch of the counter is "1".
Under these conditions, the AND condition does not hold, and the gate is opened, gate circuits 16-17 are cut off, and each AC switch shown in FIG. The gate signals supplied to the -2 thyristors 81 to S4 are instantaneously gate-blocked. In parallel with this operation, the third NAND gate 15 shown in FIG. The logical product condition is not satisfied and the gate is open, and as a result, the NAND gate 15 outputs a "moon" signal to the monomulti 18, and the gate circuit 19 operates with the output of the monomulti 18. Gate circuit 1
9 operates, a predetermined gate signal is applied to the arc extinguishing thyristor 8s of FIG. 1 via the 50th ignition circuit 8, and S
Thyristor Ss of No. 6 is turned on.

Here, if it is assumed that the thyristor 81*ss of the AC switch 1-2 is in a conductive state when the thyristor S is turned on, and the load current ■ is flowing in the direction of the arrow shown in the figure, then the arc-extinguishing thyristor S6 When the commutator capacitor CK is turned on, the charge that is charged with the polarity shown in the diagram is transferred from the commutator capacitor C to the commutator reactor L → the arc-extinguishing thyristor 8I → the thyristor S1 or S3 of the AC switch 1-2 → the commutator capacitor. CF) Discharge on the route,
The discharge current enters a free oscillating state due to the series resonant circuit of the commutating capacitor C and the commutating reactor L. The value of the discharge current in the free vibration state is the value of each thyristor 81 to s.
At the point when the load current flowing through the gate 01 exceeds the load current flowing through each thyristor S! ~Bm is forcibly extinguished, the unit inverter of the faulty machine is cut off, and the load that was being shared by the faulty machine is switched to the unit inverter of the healthy machine to continue the predetermined power supply service.

Next, to describe the operation when performing fault diagnosis, which is the main part of the present application, first, during fault diagnosis, each of the AC switches 1 to 2 shown in FIG. - Fault diagnosis shall be performed during 70-degree operation and 0FiF operation by turning OFF. Now, in the failure diagnosis mode, first switch 2 shown in Figure 2.
1 and causes the counter to sequentially count the oscillator output signal group, thereby transitioning to the failure diagnosis mode. However, when the first clock signal is input to the counter, the output terminals Q1 to Q3 of the counter section, which were each "1" in the steady mode, change to Q
l → rOJ*ch → "The signal for the moon is the first and third ONAND gates 13.15 K, while the signal that is "1" is the second and third NAND gate) 14.15 K
Each is input.

Each of these NAND gates 13 to 15 receives a signal indicating that the uninterruptible power supply is normal from the 12 flip-flop circuits, so the conditions for the output signal of the flip-flop and the output signal of the counter are The AND condition is not satisfied for the first and fifth ONAND gates 13 and 15, and as a result, the first gate circuit 16 is opened and at the same time, the third gate circuit 19 is turned on by the output signal of the monomulti 18. On the other hand, the second NAND gate 14
The AND condition is satisfied and the gate is still in a closed state, and a predetermined gate signal is applied to the thyristor am, 84 of the AC switch 2 shown in FIG. Therefore, when the first gate circuit 16 is cut off and the third gate circuit 19 is turned on, the gate of the thyristor 8bS is blocked through the ignition circuit 3 of FIG. Thyristor I of AC switch 1-2! , and ll=, the charged electric charge of the commutating capacitor C1, which is charged with the polarity shown by turning on the lever and the arc-extinguishing thyristor ss, becomes the commutating capacitor C → commutating capacitor L → arc-extinguishing. When the discharge current is discharged through the path of thyristor 8 and thyristor s2 or s4, the discharge current becomes a free oscillation state due to the resonance phenomenon, and the commutating capacitor C is recharged with a polarity opposite to that shown.

This inverted charge is the commutating capacitor C → Cyrisk sl
It is discharged again through the path s or 4 → commutating diode D1 → commutating reactor L. During this discharge,
When the value of the discharge current exceeds the load current, the gate voltage is set to 0.
The discharged thyristor s is forcibly extinguished, the AC switch is cut off, and the thyristor s4, to which the gate signal is continuously applied, is turned off when the discharge current value falls below the load current. The conduction state continues, and the desired power continues to be supplied to the load.

In this way, the first AC switch 1 is forcibly cut off,
Assuming that the OFF operation of the AC switch 1 is completed, the current detection signal taken out from the current detection current transformer S1 shown in FIG. 1 becomes zero, and this current detection signal and the reference value The output of the first comparator that compares the output becomes zero, and the non-gate n, which is the logical sum of this zero output and the signal "0" output from the output terminal q1 of the counter section, is opened. 1.
Thyristor S of the first AC switch 1 through the loop circuit!
The OFF operation causes a display circuit (not shown) to display that the current is positive. In addition, in this operation, if the operation when the AC switch 1 is turned off is incomplete and the load current is not cut off, the output of the comparator U becomes "1" with the current detection signal "present", and the output of the comparator U becomes "1". Output signal nJ and output terminal Q of counter n! The output of a NOR gate (not shown) that takes a logical sum condition with the output signal of AC switch 1 becomes zero, the gate is closed, and the thyristor S! of AC switch 1 is stored in a failure detection memory (not shown). At the same time, it memorizes that the operation is abnormal when it is OFF, and at the same time displays it on a display circuit (not shown) to notify the driver.Next, when the second clock signal is input to the counter of n,
The output terminal Ql of the counter n is "su→"month.

The output terminal ~ changes from "Month to Mark", and this causes the condition of the 10th WIND gate 13 which takes the AND condition of the "1" output signal from the BlipFlo l1 circuit 12 and the "Month" output signal from the counter Neyori. is established, the gate is closed, the first gate circuit 16 is turned on again, a predetermined gate signal is given to each thyristor S18 of the AC switch 1, and the
The second NAND & gate 14 receives the output signal "1" and the leap signal of the counter section, and similarly inputs the "month signal" and "0" signal of the counter n and the "1" signal of the flip-flop my circuit 12. 15, the AND condition is not satisfied based on these input signals, the gate is closed, the second gate circuit 17 is cut off, and The third gate circuit 19 is re-energized by the output of the monomulti 18. Therefore, as described above, when the thyristor 5lye of the AC switch 1 is re-ignited, the thyristor 88*84 of the other AC switch 2 is gate blocked, and the extinguishing thyristor S is re-ignited.
Assuming that the load current is flowing through the thyristor S4 of the second AC switch 2, the arc-extinguishing thyristor S
The thyristor S4 of the AC switch 2 is forcibly extinguished by the discharge current caused by the firing of the thyristor S! The load current value gradually rises.

In this way, the thyristor 8 of the AC switch 1. side operation is completed, while thyristor B4 of AC switch 2
Assuming that the OFF operation of is also performed perfectly, the NOR gate output of the logical sum of the output signal of the comparator of section 1 and the output signal of 0 of the comparator becomes 1, Through the flip-flop circuit No. 4, a display circuit (not shown) indicates that the OFF operation of the thyristor S4 of the AC switch 2 is normal. thyristor. If, for example, the thyristor 84 of the AC switch 2 does not extinguish the arc during such an operation, the current detecting current transformer 5! of FIG. The output of a logic gate (not shown) in the detection system that takes the logical sum of the current detection signal outputted from the current detection signal and the same output signal of the Kalantaco becomes zero, and the gate is closed and the OFF state of the thyristor S4 is stored in the fault detection memory (not shown). The fact that the operation at the time is abnormal is memorized, and at the same time, the fact is displayed on a display circuit (not shown) to notify the user.

By repeating the above operations, a predetermined fault diagnosis of the AC switch is performed based on the clock signal.

As described above, in the present invention, AC switches having exactly the same configuration are connected in parallel to each existing AC switch, and failure diagnosis tests of the AC switches can be performed even during normal operation of the uninterruptible power supply. There are many 5K races that are held, and the following are some that have a variety of effects.

■ Since it is possible to perform a fault diagnosis test on the AC switch while the uninterruptible power supply is in the middle of its regular operation, it is extremely reliable as it can quickly detect whether there is an abnormality in the AC switch itself, compared to conventional methods. Can provide uninterruptible power supply.

(2) Since a predetermined fault diagnosis test is performed without interrupting the load, it does not affect the load or unit inverter in any way, making it possible to realize a highly stable fault diagnosis system.

■ The presence or absence of an abnormality in each AC switch is determined simply by the synchronization trap of the clock signal, so the time required for fault diagnosis is extremely short and the presence or absence of an abnormality in an AC switch can be detected with high accuracy. .

■ Since failures are detected using only a combination of logic gates, it can be made extremely compact, and combined with the simplification of the circuit configuration, an inexpensive uninterruptible power supply can be realized.

[Brief explanation of drawings]

Figure 1 is a specific configuration diagram of the main circuit of a monitoring and protection device showing one embodiment of this invention, and FIG. 2 is a specific circuit configuration diagram showing a detection system for fault diagnosis applied to the device. 1-2 is an AC switch, S-4-6 is an ignition circuit, 6.
-4° is a current detection circuit, 11 is a unit inverter failure detection circuit, 12-28 is a flip-flop circuit, 1
) 115 is a NAND gate, 16-17-19 is a gate circuit, and 18 is a monomulti. Add is an oscillator, 22 is an AND gate, 23 is a kakunta, 2
4-Kudzu is a comparator, 2nd I is a NOR gate, s1~
S. is a thyristor, C is a commutating capacitor, L is a commutating reactor, D is a commutating diode, and R is a resistance for suppressing charging current.

Claims (1)

[Claims] In a parallel redundant type uninterruptible power supply system that is designed to protect the AC output of a unit inverter by detecting the presence or absence of an abnormality in the AC switch that supplies the AC output to the load, a thyristor is connected in inverse parallel to each of the AC switches. The connected AC switch groups are connected in parallel, and a failure detection signal from a detection circuit for detecting a failure of the commutating condenser is provided between the terminals of the existing AC switch and the new AC switch as a pair; Fault diagnosis is performed by logically multiplying the clock signal with the output signal of the counter that counts the clock signal. A selection circuit that gives an ignition command, a detection signal that detects the output current of the AC switch, and a logical condition of the output signal of the counter are taken, and pressure is applied to perform a predetermined fault diagnosis regardless of the selected intersection. Monitoring and protection device for uninterruptible power supply stone AC switch.