JPS5869171A - Vertical profile compensating circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution, by multiplexing two video signals to be delayed by 1H and using a delay line delaying two delayed video signals and an AGC circuit to compensating level fluctuation due to the delay line in common. CONSTITUTION:A video signal E1 from an emitter follower circuit 2 is applied to one balanced modulator 20 of a quadrature two-phase balanced modulator via a clamp circuit 3, modulated with a carrier wave from an oscillator 5 and delayed at a 1H delay line 24. The gain of a delayed modulation wave is adjusted at an AGC circuit 25, the output and the level of the modulation wave before delay are compared at a comparator 26, the reference level is made constant and the output of the circuit 25 is applied to demodulators 28, 29. A video signal E2 delayed by 1H from the demodulator 28 is applied to the other balanced modulator 21, modulated with a carrier wave shifted by 90 deg. and applied to a band amplifier 23 with multiplexing with an output from the modulator 20. The delay line 24 and the circuit 25 and the like are used in common for the video signals E1, E2 and the vertical profile compensation is performed at an addition circuit 16 and a subtraction circuit 17 with the output of the demodulators 28 and 29.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical contour correction circuit suitable for correcting an output video signal of a television camera to improve image quality.

In a television camera, when an electron beam scans a target on which the image of the subject is formed, the diameter of the electron beam cannot be made infinitely small, so the electron beam scans the target with a width equal to the diameter. For this reason, the output video signal from the television camera contains average information content in the direction of the width scanned by the electron beam, and adjacent regions of the beam width in successive horizontal scans of the electron beam are close to each other. Alternatively, if there is some overlap, the information content of each horizontal scanning period of the output image line signal will be averaged to some extent between adjacent horizontal scanning lines.

By the way, when the electron beam scans a part of the target where the height does not change, there is no problem because the information content of adjacent horizontal scanning lines is almost the same.
When the electron beam scans the contour of an image, the information content of each horizontal scan is naturally calculated.If the information content of the resulting image signal is averaged, the contour of the reproduced image will not appear faithfully and the image quality will deteriorate. Manekkoto K becomes.

Therefore, it is necessary to process the video signal by a vertical contour correction circuit in order to emphasize the contours of the image, but due to the S/N ratio, the video signal output from the television camera is processed.

FIG. 1 is a block diagram showing an example of a conventional vertical contour correction circuit, in which 1 is an input terminal, 2 is an emitter follower circuit,
3 is a clamp circuit, 4 is an amplitude modulator, 5 is an oscillator, 6 is a band P wave generator, F is an IH delay line (however, H is a horizontal scanning period), 8 is an automatic gain control circuit, 9 is a comparator, 10 is a demodulator, 11 is a band r-wave device, 12 is an IH delay line, 13 is an automatic gain control circuit, 14 is a comparator, 15 is a demodulator, 16 is an addition circuit, 17 is a subtraction circuit, 18.19 is an output It is a terminal.

Next, the operation of the above-mentioned prior art will be explained.

In the same figure, a video signal Et from a television camera (not shown) supplied to the input terminal IK (Fig. 2 (1)
)) is supplied to a clamp circuit 3 and an adder circuit 16 through an emitter follower circuit 2.

The video signal whose reference level is fixed at a constant level /&/ by the clamp circuit 3 is supplied to the amplitude modulator 4 and then to the oscillator 5.
After modulating the carrier wave from and removing unnecessary components by the band r wave generator 6, it is supplied to the IH delay tube @7 and is subjected to IH delay. IH
The delayed amplitude modulated wave is supplied to the automatic gain control circuit 8, where it is amplified to a constant level, demodulated by the demodulator 10, and the IH-delayed Eirin signals E and K are supplied to the input terminal IK. A signal El (FIG. 2(b)) is obtained.

On the other hand, the output signal of the automatic gain control 4 circuit 8 is
1 to remove noise components, and then supplied to the IH delay line 12 for IH delay. The IH-delayed amplitude modulated wave is supplied to the automatic gain control circuit 13, amplified to a constant level, demodulated by demodulation@15, and supplied to the input terminal LK. The video signal Es (
FIG. 2(C)) is obtained.

Note that the automatic gain control circuit 8 is controlled by a control signal obtained from K when its output signal and the input signal of the IH retarder line 7 are compared in level by a comparator 9, and the automatic gain control circuit 13 is controlled by the control signal obtained from K when its output signal and the input signal of the IH retardation line 7 are compared in level. When the signal and the input signal of the IH delay line 120 are compared in level by the comparator 14, the signal is controlled by a control signal obtained from K.

In this way, the automatic gain control circuits 8 and 13 each have an IH
Corrects signal level fluctuations due to delay line 7.12.

Video signal E1 and video signal E delayed by 2H.

are supplied to the adder circuit 16, and their sum signal IC4 (see FIG. 2(d)) is obtained and supplied to the subtracter circuit 17. Further, the subtraction circuit 17 receives the video signal E, and the video signal E! delayed by IH! is supplied, and a difference signal Ei between this video signal E and a signal E4/2 obtained by attenuating the above sum signal E by 1/2 is obtained.
((•) in FIG. 2) is obtained, and this is supplied to the output terminal 191C as a signal for vertical contour correction. On the other hand, the output terminal 18 receives the video signal E.

is obtained, and in the adder circuit (not shown), the output terminal 18
By adding the video signal B from K and the vertical contour correction signal E from the K output terminal 19, a corrected video signal (FIG. 2(f)) is obtained.

In this manner, it is possible to obtain a video signal capable of reproducing a picture image whose contours have been corrected in the vertical direction.

However, in the above conventional technology, the IH slow heron line 7.12
must be an expensive broadband delay line, and it is extremely uneconomical to use two such delay lines, and the space required for them is also large.
Passing the IH signal through the delay line inevitably causes fluctuations in the reference level, so an automatic gain control circuit 8.13 must be provided for each IH delay line 7.12, making the circuit configuration complicated. was there.

An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, and to make it possible to share an IH slow W, line and automatic gain control circuit for two video signals. is to provide.

To achieve this objective, the present invention multiplexes two video signals to be delayed and delays them by 1. Hereinafter, an embodiment of a vertical contour correction circuit according to the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention,
20.21 is a balanced modulator, 22 is a 90 degree phase shifter, 23 is a band amplifier, 24 is an IH delay line, 25 is an automatic gain control circuit, 26 is a comparator, 27 is a phase shifter, 28. 29 is a demodulator, 30 is a 90-degree phase shifter, and parts and signals corresponding to those in FIG. 1 are given the same reference numerals, and some explanations are omitted.

Next, the operation of this embodiment will be explained.

In the figure, a video signal E whose reference level is fixed at a constant level by a clamp circuit 3 is supplied to one balanced modulator 20 constituting a quadrature two-phase balanced modulator to modulate a carrier wave from an oscillator 5. , unnecessary components are removed by a band amplifier 23 and delayed by an IH delay line 24. The IH-delayed modulated wave is supplied to the automatic gain control circuit 25, and its output signal and the input signal of the IH delay 1124 are level-compared by a comparator 26.The gain is controlled by the control signal obtained by K, and the reference level is reached. will reach a certain level. The modulated wave from the automatic gain control circuit 25 is supplied to the demodulators 28 and 29, and the phase shifter 27 changes the phase of the carrier wave from the oscillator 5 to the phase of the modulated wave from the balanced modulator 20 which is IH delayed. Since the phases are adjusted to match, the above modulated wave is demodulated by the demodulator 2B. As a result, the demodulator 28 obtains the video signal E, which is IH-delayed with respect to the video signal E, K supplied from the input terminal 1.

The Eirin signal E obtained in this way is output from the output terminal 18.
and K are supplied to the subtraction circuit 17.

A part of it is also supplied to the other balanced modulator 21 constituting the quadrature two-phase balanced modulator. A carrier wave from the oscillator 5 whose phase has been shifted by a 90-degree phase shifter 22 is supplied to the balanced modulator 21, and is modulated by the video signal E. Of course, at the same time, the balanced modulator 20 also receives gI! A signal E1 is provided and modulates the carrier wave as described above.

Then, the modulated waves from the balanced modulators 20 and 21 are mixed and converted into a video signal E1, a multiplexed signal by quadrature two-phase modulation, which is sent to the band amplifier 23, the IH delay line 24,
It is fed through an automatic gain control circuit 25 to a demodulator 28,29.

Therefore, the demodulator 28 uses the balanced modulator 20 as described in 5 above.
Since the multiplexed signal is demodulated using a carrier wave that is in phase with the IH-delayed version of the modulated wave from the Occur.

On the other hand, the carrier wave supplied to the demodulator 29 is 90
Since the carrier wave is phase-shifted by 90 degrees with respect to the carrier wave supplied to the demodulator 28 by the degree shifter 30, the balanced modulator 21
The demodulator 29 obtains a video signal E that is IH-delayed with respect to the video signal E obtained by the demodulator 28, which is in phase with the IH-delayed modulated wave from the demodulator 28.

Video signal E1 from input terminal 1 and video signal E from demodulators 28 and 29! , Ea, an output terminal 19K[l] is obtained from the addition circuit 16, the subtraction circuit 17, and K, and the vertical contour correction signal can be used to correct the image signal obtained at the output terminal 18. , which is similar to the prior art described in FIG.

In this way, in order to obtain the video signal E which is delayed by IH and the video signal E which is delayed by 2H,
Since the delay is achieved by multiplexing the video signal E1 and the Eirin signal E obtained by delaying it by IH, one IHH extension line can be shared as a delay means for each Eirin signal. Moreover, since quadrature two-phase balanced modulation is used as the multiplexing means, the frequency band of the multiplexed signal is not widened for each individual video signal, so there is no need for a particularly wide-band IH slow-delay line. Furthermore, only one automatic gain control circuit and one comparator are required.

FIG. 4 is a block diagram showing another embodiment of the vertical contour correction circuit according to the present invention, which is a 31,321 subtraction circuit, and parts corresponding to those in FIG. Omitted.

FIG. 5 is a signal waveform diagram showing signals of each part in the block diagram of FIG. 4.

In Fig. 4, the demodulator @28 outputs the IH signal El supplied from the input terminal 1 (Fig. 5 (a))
Similar to the embodiment shown in FIG. 3, the delayed video signal E (FIG. 5(b)) is inputted.

This video signal E is supplied to the output terminal 18, and a portion thereof is supplied to the subtraction circuit 31.

Further, the video signal E is also supplied to the subtraction circuit 31, and a difference signal E, (Wp!:, 1-E@) (FIG. 5) between the video signal E and h is obtained. This difference signal E6 is supplied to the balanced modulation circuit 21.

Therefore, the video signal E1 and the difference signal E supplied to the input terminal IK are multiplexed by one quadrature two-phase parallel modulation as in the embodiment shown in FIG. 23, an IHH extension 24, and an automatic gain control circuit 25 to the demodulators 2B and 29. The demodulator 28 generates a video signal Et delayed by IH with respect to the video signal E, and the demodulator 29 generates a difference signal Et delayed by IH with respect to the difference signal E.
.

(Fig. 5(d)) is generated.

This difference signal E is then supplied to the subtraction circuit 32.

The subtraction circuit 32 also receives a difference signal E6 from the subtraction circuit 31.
The difference signal Ea (=Ey
E@) (Fig. 5(-)) is generated at the output terminal 19. This difference signal E$ is a vertical contour correction signal, and by adding it to the video signal E from the output terminal "18," it is possible to obtain a video signal whose vertical contour has been corrected.

In this embodiment, the reference level of the difference signal E delayed by IHHI3 is zero level, and there is no deviation in the reference level due to IHH line extension, etc. , it is not necessary to take into account separate considerations for adjusting the reference levels of , and the requirements for the automatic gain control circuit 25 are accordingly relaxed. Further, in this embodiment, unlike the embodiment shown in FIG. 3, an addition circuit and a subtraction circuit are not used, but a subtraction circuit is used to generate the video signals E, Since the vertical contour correction signal is obtained from the subtraction circuit 17 in the embodiment shown in FIG. 3, there is no need for an additional circuit such as the input signal attenuation means 1 to be supplied to the subtraction circuit 17 in the embodiment shown in FIG.

As explained above, according to the present invention, two IH signals to be delayed are multiplexed and IH delayed.
It is possible to share the automatic gain control circuit for correcting level fluctuations caused by the IHH line extension and the IH slow death line for the two video signals, simplifying the configuration, and eliminating the drawbacks of the conventional technology. It is possible to provide a vertical contour correction circuit with a small size and low cost.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional vertical contour correction circuit, Figure 2 is a waveform diagram showing signals of each part in Figure 1, and Figure 3 is an embodiment of the vertical contour correction circuit according to the present invention. FIG. 4 is a block diagram showing another embodiment of the vertical contour correction circuit according to the present invention, and FIG. 5 is a waveform diagram showing signals at various parts in FIG. 4. l...input terminal, 16...addition circuit,
17... Subtraction circuit, 18.19... Output terminal, 20.21... Balance cost adjuster, 22...
...90 degree phase shifter, 24 ... IH delay line,
25... Automatic gain control circuit, 28.29...
...Demodulator, 30...90 degree phase shifter, 31.
32... Subtraction circuit. Figure 3 Figure 74 Figure 1 "l" 5 Figure

Claims (4)

[Claims] (1) Utilizing the vertical correlation of the image quality, a vertical contour correction signal is formed from the input video signal, and the input video signal is
H (H is horizontal scanning period) Add to the delayed signal 5Kt
, in the vertical contour correction circuit, a multiplexing circuit multiplexes a plurality of video signals and a multiplexed signal from the video multiplexing circuit. a delay line, a separation circuit that separates the respective video signals from the IH-delayed multiplexed signal, and a separation circuit that is supplied with the input video signal and each video signal from the separation circuit, and a vertical contour correction signal. A processing circuit for outputting IH1! is provided, one of the plurality of Eirin signals supplied to the multiplexing circuit is used as the input Eirin signal, and the other is connected to the slow line through the IH1! [By multiplexing as a signal based on the input Eirin signal, IH of 1 Confucian:! A vertical contour correction circuit characterized in that it is configured to be capable of delaying a plurality of video signal signals due to line extension. (2) The vertical contour correction circuit according to claim 1, wherein the multiplexing circuit is a quadrature two-phase balanced modulator. (3)! In claim 1 or 2, the processing circuit includes an addition circuit which receives as input signals the input Eirin signal and the Eirin signal obtained by 2H delaying the input signal, and the addition circuit which receives the input signal and the Eirin signal obtained by IH delaying the input signal. The vertical subtraction circuit is comprised of a subtraction circuit which receives an input signal as an output signal from the adder circuit, and is configured to be able to supply the signal obtained by IH-delaying the input signal to the multiplexing circuit. Contour correction circuit. (4)! In claim 1 or 2, the processing circuit includes a first subtraction circuit whose input signals are the input Eirin signal and the Eirin signal obtained by IH-delaying the input Eirin signal, and the first subtraction circuit. A second subtraction circuit that receives as input signals the output Eirin signal of the circuit and the Eirin signal obtained by delaying the same by IH, and is configured to be able to supply the output Eirin signal of the first subtraction circuit to the multiplexing circuit. A vertical contour correction circuit featuring: