JPS5866996A - Modulated signal generator for electronic musical instrument - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modulation signal generating device for vibrato or the like in an electronic musical instrument.

As a conventional technology for electronic musical instruments that digitally generates a modulation signal for vibrato, Japanese Patent Application Laid-Open No. 53-1
There is one disclosed in Publication No. 06023. In the conventional modulation signal generator shown therein, a voltage controlled oscillator (hereinafter referred to as VCO) oscillates a variable frequency clock pulse, and this clock pulse increments or decrements the contents of a counter by one. A digital modulation signal is generated based on the output of this counter. There, the vibrato frequency is controlled by variably adjusting the oscillation frequency of the VCO. Further, the vibrato depth is controlled by appropriately shifting the output signal of the counter in a shift circuit. By the way, in the conventional device as described above, since a VCO is required to variably adjust the vibrato frequency, there is a drawback that the circuit configuration becomes large-scale. Further, since the depth control must be performed using numerical software, there is a drawback that the configuration of the shift circuit must be complicated. This is because the number obtained by shifting a binary number is simply limited to 2 degrees of the original number, so a simple shift circuit can only perform simple depth control; This is because, in order to provide a wide range of control, it is necessary to use a complicated shift circuit that has a function of adding or subtracting various shifted numerical values. It is also conceivable to perform depth control using a multiplier instead of a shift circuit, but this would make the circuit configuration even more complicated.

The present invention has been made in view of the above points, and is a digital modulation signal generator for an electronic musical instrument that has a simple configuration but allows the frequency, depth, etc. of the modulation signal to be freely set. This is what we are trying to provide.

The modulation signal generator of the present invention repeatedly adds (or subtracts) numerical data to set the frequency of the modulation signal.
and a first arithmetic circuit that outputs an arithmetic timing control signal each time the calculation content reaches a predetermined value, and a first arithmetic circuit that adds or subtracts numerical data indicating a predetermined change range each time this arithmetic timing control signal is given. A second arithmetic circuit and addition/subtraction of the second arithmetic circuit are controlled according to a target value for setting the depth of the modulation signal, and the calculation content of the second arithmetic circuit increases or decreases within the range of the target value. and an arithmetic control circuit that repeats the process, and outputs the calculation contents of the second arithmetic circuit as a modulation signal.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Description of an Embodiment Showing the Basic Configuration of the Invention In FIG. 1, a frequency data generator 400 generates numerical data for setting the frequency of a modulation signal to be generated. The first arithmetic circuit 401 may repeatedly add or subtract the numerical data generated from the frequency data generator 400), and outputs an arithmetic timing control signal OTC every time the content of the calculation reaches a predetermined value. For example, the arithmetic circuit 401 includes an adder 402 and a delay circuit 4.
03, which repeatedly accumulates numerical data provided from the device 400 at regular one-hour intervals according to a predetermined clock pulse φ.

Every time the calculation content reaches a predetermined number of modules, the adder 402
A carry-out signal is generated from the carry-out output C8 of 3, and this carry-out signal is outputted as the calculation timing control signal OTC3.Therefore, the control signal OTC is output at time intervals corresponding to the value of the numerical data generated from the frequency data generator 400. occurs periodically.

Change width data generator 4oai, second arithmetic circuit 405
This generates numerical data indicating the range of change in numerical value in one calculation. The second arithmetic circuit 405 receives the arithmetic timing control signal OTC from the first arithmetic circuit 401.
Each time the numerical data is given from the change range data generator 404, it is added or subtracted. In this arithmetic circuit 405, an accumulator is configured by an adder/subtracter 407 and a delay circuit 408.
Each time the calculation timing control signal OTC is applied, the gate 406 is opened and the numerical data generated from the variation range data generator 404 is applied to the eight inputs of the adder/subtractor 407 . The adder/subtractor 407 can operate in either addition mode or subtraction mode, and when in the addition mode, the delay circuit 4
08 Force 1 Adds the change width numerical data given to the A input to the previous calculation result given to the B input, and when in subtraction mode, adds the change width given to the A input from the previous calculation result given to the B input. Subtract numerical data.

The arithmetic control circuit 409 controls switching of the arithmetic mode in the second arithmetic circuit 405 from addition mode to subtraction mode or vice versa, and controls target value data generation device 410.
and a comparator 411. The target value data generator 410 generates target value data for setting the depth of the modulation signal to be generated. Comparator 41
1 compares the output of the second arithmetic circuit 405 with target value data, and outputs a signal U/D for controlling the arithmetic mode of the adder/subtractor 407 according to the comparison result. A target value data generator 410 outputs one of the target value corresponding to the upper limit value and the target value corresponding to the lower limit value of the modulation signal to the output signal T of the comparator 411.
It occurs selectively depending on J/D.

For example, when the output signal U/D of the comparator 411 indicates the addition mode, the second arithmetic circuit 405 repeatedly adds numerical data indicating the change range every time the control signal OTC is generated, and as a result, The value of the output signal of the arithmetic circuit 405 gradually increases. At that time, the target value data generator 4
10 generates data indicating the upper limit target value. When the value of the output signal of the arithmetic circuit 405, which gradually increases, reaches the upper limit target value,
When the output signal U/D of the comparator 411 is reached, the output signal U/D of the comparator 411 switches to the content instructing the subtraction mode. As a result, the arithmetic circuit 40
5, the numerical data indicating the range of change is repeatedly subtracted every time the control signal OTC is generated, and the target value data generator 410 generates data indicating the lower limit target value. The value of the output signal of the arithmetic circuit 405 gradually decreases, and when the value eventually reaches the lower limit target value, the output signal U/D of the comparator 411 switches to the content instructing the addition mode. In this way, the calculation mode of the calculation circuit 405 is alternately switched, and the output signal of the calculation circuit 405 oscillates within the range of the upper limit target value and the lower limit target value.

The output signal of the second arithmetic circuit 405 is supplied as a digital modulation signal to a circuit (not shown) for modulating and controlling the pitch or volume of the musical tone.

As shown by the broken line, the target value data generated from the target value data generator 410 is supplied to the variation width data generator 404, and the target value data is shifted to the lower order by a predetermined bit to obtain a minute value. It is preferable to output this minute value as numerical data indicating the range of change. In this way, if the value of the target value changes, the value of the change width data will also change accordingly, and the value of the change width data will always have a constant ratio to the target value), and the modulation signal found by the calculation circuit 405 will be the upper limit target. The number of calculations required to reach the lower limit target value (or vice versa) is always constant. As a result, the oscillation period (frequency) of the modulation signal depends only on the seller interval of the calculation timing control signal OTC, making it easy to set the frequency of the modulation signal. Furthermore, the depth of the modulation signal can be freely set by changing the value of the target value generated by the target value data generator 410. Therefore, a complicated shift circuit for depth control is not required. For a modulation effect whose depth is constant over time (for example, a normal vibrato effect), a target value data generator 410 is used.
need only be configured to simply continuously generate constant target value data corresponding to the depth selected by the player. On the other hand, a modulation effect in which the depth changes over time (
For example, for the delay vibrato effect), the target value data generation device 410 may be configured to generate envelope-shaped target value data that changes over time.

In the detailed embodiment described below, the modulation signal generating device according to the present invention is included in the effect imparting circuit 20 (see FIGS. 2, 12, 13, and 14). , mainly a detailed example thereof is shown in FIG. Further, the part for setting the frequency and depth of the modulation signal is also related to the various effect setting operator group 15 and the A/D conversion section 17 (see FIGS. 2, 6, and 7).

1. Detailed Description of the Overall Structure of the Embodiment Next, a more specific embodiment of the electronic musical instrument to which the present invention is applied will be described with reference to FIG. 2 and subsequent figures. FIG. 2 is a block diagram of the overall configuration roughly showing the relationships among the detailed parts of the electronic musical instrument divided and shown from FIG. 3 onwards. The keyboard 10 includes a plurality of keys for selecting pitches (note names) of musical tones.

The touch sensor 11 detects the touch of each key and generates an output signal corresponding to the key touch. Key press detection unit 12
detects a key pressed on the keyboard 10 and provides information T indicating the pressed key
Output DM. This key press detection section 12 is designed to scan the key switch corresponding to each key, and the output of the counter 13 is used for this purpose. Sound assignment circuit (
The key assigner 14 is for assigning and generating a musical tone corresponding to a pressed key to one of a limited number of musical tone generation channels, and includes, as an example, a single note key assigner 14A and a multitone key assigner 14B, This electronic musical instrument can be selectively operated in either a single note mode or a multiple note mode.

For this purpose, a single note mode selection switch MONO-8W is provided in connection with the sound generation allocation circuit 14, and when the switch MONO-8W is on, a single note mode selection signal MONO-8W is provided.
"1" is applied as NO to the circuit 14 and other necessary circuits so that the electronic musical instrument operates in a single note mode. Slur effect selection switches 5L-8W are switches for selecting slur effects;
1 as slur-on signal 5LON when L-8W is on
” is applied to the pronunciation assignment circuit 14 to enable a slur effect. In this example, a slur effect is defined as a change in the pressed key in legato form when the electronic musical instrument is operating in single note mode (the old When a new pressed key is pressed before the pressed key is completely released, the pitch of the generated musical note changes smoothly from the pitch of the old pressed key to the pitch of the newly pressed key.

The various effect setting operator groups 15 each include variable operators for setting control amounts of control elements (time, speed, level, etc.) of various effects such as vibrato, initial touch control, and aftertouch control. There, the operator corresponding to the control element for touch control is adapted to adjust the sensitivity of the output signal of the touch sensor 11. To give an example of various effects, the pinch control-related effects include "vibrato,""TeiraiVibra-1,""attack pinch control,""aftertouchvibrato," and the aforementioned "slur," and the level control-related effects include " These include "initial touch level control", "f77 touch level control", and "envelope sustain time control". "Delay vibrato" is an effect that gradually adds vibrato after a period of time has elapsed from the start of sound generation of a musical tone, and "attack pitch control" is an effect that adds vibrato at the beginning of a musical tone. In this embodiment, the "attack pitch control" is controlled in response to a key touch (preferably in response to an initial touch).

"Aftertouch vibrato" controls vibrato in response to a key touch, particularly a key touch in a sustained suppression state. [Initial touch level control] is the initial touch of the key (
This is called the initial level) to control the level of the musical tone.

"Aftertouch level control" is to control the level of a musical tone in response to a key touch (this is called aftertouch) in a state of continuous suppression. Control according to initial touch and aftertouch can be performed not only on pitch and volume (level) but also on timbre and other musical sound elements.

In this embodiment, the setting data corresponding to each operator output from the operator group 15 is expressed as an analog voltage, and an analog voltage multiplexer 16 time-division multiplexes these analog voltages. Analog/digital conversion (
The unit 17 (hereinafter simply referred to as A/D conversion) is the A/D converter 1
8 and a control and storage unit 19, which converts the multiplexed analog voltage into A/D, stores and demultiplexes the digitally converted setting data of each operator. The output of the counter 16 is used for time division multiplexing in the multiplexer 16 and control in the A/D converter 17.

In this embodiment, initial touch and aftertouch are detected using a common touch sensor. That is, a touch sensor 11 capable of after-touch detection is used, the output signal of this touch sensor 11 is selected for initial touch detection for a predetermined period of time from the start of key pressing, and the touch sensor 11 is detected based on the selected touch sensor output signal. The initial touch is detected. For example, the peak value of the selected touch sensor output signal is held for a predetermined period of time from the start of key pressing, and this peak value is used as the initial touch detection signal. for that,
The sound generation assignment circuit 14 outputs an initial sensing signal Is for a predetermined period of time (for example, about 10 m5, which is almost negligible to human hearing) from the start of key pressing, and this signal Is causes the multiplexer 16 and A to be output.
/D converter 17 is controlled so that during this period, the above-mentioned initial touch detection is performed exclusively. At the same time, in the sound generation allocation circuit 14, the initial sensing signal Is
The start of musical tones is delayed while outputting. This is to prevent the start of sound generation before the initial touch is detected, and to perform initial touch control at the same time as the start of sound generation. Incidentally, as described above, in this embodiment, attack pitch control is also performed in accordance with the initial touch.

The effect applying circuit 20 is a circuit for applying various effects related to pitch control, and outputs a modulation signal VAL for modulating musical tone frequency for vibrato, delay vibrato, attack pitch control, and aftertouch vibrato. Regarding the slur effect, musical tone frequency information SKC to which the slur effect has been added is output.

Among the setting data of various effect setting operators output from the A/D converter 17, setting data related to pitch control is given to the effect applying circuit 20, and setting data related to level control is given to the musical tone signal generating section 21. . An attack pitch start signal As, a slur start signal SS, and a key code MKC indicating the pressed key in the single note mode are supplied from the sound generation assignment circuit 14 to the effect imparting circuit 20. Note that the single note key assigner 14A selects a single key (for example, the highest or lowest pressed key) from among the pressed keys and outputs it as a pressed key key code MKC for the single note mode.

Attack pitch data ROM (abbreviation for read only memory) 22 contains attack pitch control data APS corresponding to various tones to which active pitch control should be applied.
, APR, and APER are stored in advance. The active pitch control is designed to perform control in a manner suitable for each tone, for example, and is an effect particularly suited to wind instrument tones because it can express the pinch disturbance at the beginning of a wind instrument's blowing. Therefore, the tone selection switch 23
Control data AP that has values that can realize attack pitch control suitable for the tone selected in .
S, APR, APER are read from the ROM 22. 1. The elements that determine the attack pitch control mode are the initial depth of pitch deviation (at the beginning of the sound) and the time of the depth of pinch deviation. These are the envelope that shows the physical change and the repetition frequency of the pinch shift. The depth of the initial pitch deviation, ie, the initial value of the attack pitch, is set according to the above-mentioned initial touch detection data.

Specifically, the initial touch detection data is scaled by attack pitch initial value coefficient data APS corresponding to the timbre, thereby setting the attack pitch initial value according to the initial touch and the timbre. An envelope indicating a temporal change in the depth of pitch deviation is set by attack pitch envelope plate data APER. The repetition frequency of pinch deviation is set by attack pitch rate data APR.

The effect imparting circuit 20 receives an attack pitch start signal As
is given, it starts forming a modulation signal VAL for attack pitch control based on the above-mentioned data, and then forms a modulation signal VAL for normal vibrato, delay vibrato, or aftertouch vibrato. As described later, the modulation signal V
In order to form the AL, the effect imparting circuit 20 is designed to facilitate control of the modulation frequency and modulation depth. In addition, the effect imparting circuit 20 performs a process of smoothly changing the musical tone frequency information SKC of a pressed key for single note mode from a value corresponding to an old pressed key to a value corresponding to a newly pressed key when the slur start signal SS is given. Do this. The newly pressed keys are indicated by the single note mode pressed key code MKC given from the sound generation assignment circuit 14.

In the musical tone signal generation section 21, in the single tone mode, musical tone frequency information SK for the single tone mode given from the effect imparting circuit 20 is used.
A musical tone signal is generated based on C, and in the multitone mode, musical tone signals are generated in a plurality of channels based on a key code PKC indicating the pressed key assigned to each of the plurality of channels given from the sound generation assignment circuit 14 (multitone key assigner 14B). Occur. The frequency (pitch) of these musical tone signals is modulated according to the modulation signal VAL, and the volume level is controlled according to level control data from the A/D converter 17. Furthermore, the tone selected by the tone selection switch 23 is added to these musical tone signals, and the tone is sent to the sound system 24.

Next, detailed examples of each part in FIG. 2 will be explained.

Explanation of key press detection unit and single note key assigner FIG. 3 shows a detailed example of the key press detection unit 12 and the counter 13.
FIG. 4 shows a detailed example of the single note key assigner 14A. The counter 13 receives two-phase system clock pulses φ1. It includes a 16-stage/1-bit shift register 25 controlled by φ2, a 1-bit half adder 26, and a latch circuit 27 that periodically latches the contents of the shift register 25, and performs counting operation by serial operation. Let's do it. Serial calculations are used not only in this counter 13 but also elsewhere in the detailed example described below, contributing to saving in circuit configuration. The key press detection unit 12 includes a key switch matrix 28 in which key switches corresponding to each weight of the keyboard 10 are arranged in a matrix, a decoder 29 that supplies a scanning signal to input lines for every half octave in this matrix 28, and and a multiplexer 30 for multiplexing the output line signals corresponding to each of the six note names within each half-octave in matrix 28. The key switch matrix 28 is scanned in order from the treble side key switch, and the single note key assigner 14A selects the highest pressed key as the pressed key for the single note mode.

In other words, the scanning time for one key in the key switch matrix 28 is the processing time for one key in the single note key assigner 14A (this will be referred to as one key time).
As shown in the figure, it consists of 32 time slots. The length of one time slot is the system clock pulse φl, φ
2, and is, for example, 0.5 μs. Therefore, the length of one key time is 16 μs. Various processes are controlled in synchronization with each time slot or section within this one key time. To this end, various timing signals as shown in FIG. 5 are generated by a timing signal generation circuit (not shown) and supplied to various circuits. Each of the 32 time slots is repeated with a period of 16 μs. In order to distinguish the individual time slots within one key time, they will be referred to as 1st to 32nd time slots in order of occurrence. In order to make the generation timing, generation period, and pulse width of various timing signals clear at a glance, each timing signal is assigned a code according to the following rule. For example, when numbers are written before and after the letter fyj, such as r 1 y 8j, the former number indicates the time slot order in which the pulse occurs first in one key time, and the latter number indicates the time slot order in which the pulse occurs first. The period of repeated occurrence is indicated by the number of time slots. For example, signal 1y8 initially occurs in the first time slot, as shown in FIG.
, a pulse (1'1") force is generated in the 6th time slot, respectively.Next, in the case of "1y8S" with the letter "S" added to the end, the pulse width is not equal to the entire width of one time slot. This means that the clock pulses are generated in synchronization with the pulse width of nine clock pulses φ2 in the first half of one time slot. In addition, when numbers are written before and after the character ITJ, such as 1-IT8J, the pulse (“1”) is applied from the time slot order indicated by the former number to the time slot order indicated by the latter number. ) occurs continuously and its period is 32 time slots. For example, the signal IT8 has a pulse width of 8 time slots that continuously occurs from the first time slot to the eighth time slot, and has a pulse width of 32
Occurs repeatedly at the time slot period. Also, rlT
When the pulse width display 1'-IT6J is followed by the letter "y" and a number, such as 6y8J, the number written next to the letter ryJ indicates the repetition period in terms of the number of time slots. For example, in the signal 1T6y8, a pulse that is initially generated in a width of 6 time slots from the first time slot to the sixth time slot has a repetition period of 8 time slots, that is, from the 9th to the 14th time slot.
and the 17th to 22nd time slot machines, and the 25th time slot machine.
This means that pulses are generated in each section from the 30th time slot to the 30th time slot.

In FIG. 3, the output Q16 of the final stage of the shift register 25 is added to the input A of the adder 26, and the input C
A signal 17y32 is applied to i via an OR circuit 31. Therefore, l'' is added to the final stage output of the shift register 25 at the 17th time slot when the signal 17y32 becomes 1''. When inputs A and Ci are both 1" and a carry signal is generated, the carry output Co+t becomes "1" l time slot later than the calculation timing. c.

The symbol +1 added next to indicates a delay of one time slot. The carry output C6+ of the adder shown below
1 is assumed to be delayed by one time slot from the calculation timing. It is assumed that there is no delay in the addition output S. Carry field output co+1 is AND circuit 3
2 and the OR circuit 31 to the input Ci. Therefore, the carry signal can be added to the upper (ff) bit.

The signal of the output S of the adder 26 is input to the shift register 25 via the AND circuit 36, and is returned to the input A after a delay of 16 time slots. The signal Z1 applied to the other input of the AND circuit 33 is normally 1''. With the above configuration, a serial operation is performed in which the count is increased by 1 every key time (32 time slots) using the signal 17y32 as a count clock. Therefore, the signal output from the final stage of the shift register 25 in the 17th time slot is the least significant bit of the count value,
At this time, each stage holds count values of higher-order bits in order from the final stage to the first stage. Similarly, in the first time slot 16 times after the 17th time slot, the count values from the least significant bit to the most significant bit are arranged from the last stage to the first stage of the shift register 25. Therefore, by the signal 1y32S generated in the first half of the first time slot, the seventh stage output Q7 to the final stage output Q16 of the shift register 25 are transferred to the latch circuit 27.
A parallel binary count value of 10 bits is obtained by latching . It should be noted that the timing of the signal 1y16, that is, the AND circuit 3 at the first and 17th time slots.
2 is disabled in order to prevent the most significant bit's carry signal from being added to the least significant bit.

The count value of the lower 7 bits in the counter 16 is used for key scanning and multiplexing. Of these, the lower 4 bits are N4. N3. N2. Nl specifies the note name (note name within one octave) of the key, and the upper 3 bits B3. B2.
Bl specifies the octave to which the key belongs.

Bit B3 of the count value latched by the latch circuit 27. B2°B 1 and N4 are decoded by a decoder 29 and provide scanning signals to the input lines of every half octave in the key switch matrix 28. Also, lower pitch) N3. N2. Nl is applied to multiplexer 30, which time division multiplexes the signals of the six output lines within each half-octave in key switch matrix 28. In this way, the multiplexer 60 outputs time-division multiplexed key data TDM indicating the pressing or key release of each weight corresponding to the scanning of each weight. Time division multiplexing key data T
DM is "1" if the key currently being scanned is pressed, and is "0" if it is not pressed.

Since the key to be scanned changes every time the count values B3 to N1 latched in the latch circuit 27 change, the scanning time for one key is from the 1st time slot to the 32nd time slot as shown in FIG. 32 time slots,
During this time, key data TDM for one key is continuously output. As mentioned above, the time required for one key to scan one key is 1
6 μs, one scanning cycle, that is, the time for one round of the color sheet values B3 to N1 is approximately 2 ms (=: 16 μs
X27).

The keyswitch matrix 28 is designed to be scanned in the order of high notes. In other words, each weight is sequentially assigned according to a predetermined value such that the smaller the count value B3~ is, the higher the pitch is, and the larger the count value is, the lower the pitch is. The scanning is now shifted to the side. The count value of the lower 7 bits in the counter 16 (B3~-"Go") is a code signal representing the key currently being scanned, that is, the key corresponding to the time division multiplexed key data TDM, that is, the key code KC.
It is. However, the count value B3 of the counter 13 ~ tile 1
In the key code Y using as is, the treble key has a small value, and the bass key has a large value. When converting a key code into frequency information by repeatedly adding the lower two bits of the key code to the lower digits, there will be a problem if the value of the key code does not increase the higher the key. The key assigner 14A, 14 uses the inverted code Yτ as the official key code KC.
I am trying to use it in B. Official key code KC
For example, the relationship between and each weight is as shown in the table below. The key code KC is the upper 3 bits of the octave code B3. B
2. Bl and the lower 4 bits of the note code N4. N3. N
2. It consists of Nl.

Note that the indications written in the seventh to final stages of the shift register 25 indicate the weights of each stage at the first and seventeenth time slots. That is, at this time, the first
0 to the final stage (Q10 to Q16), 1 is entered in the lower 7 bits 1 to 1 of the count value as described above. Furthermore, the seventh to ninth stages (Q7 to Q9) contain bits with weights of approximately 8 ms, approximately 4 ms, and approximately 2 ms in time representation. These time table values indicate the time from when the counter 13 is reset until those bits are set to 1''.As will be described later, these time display bits are used when the counter 16 is used as a timer. These time display pits are latched in the latch circuit 27 together with the key codes B3 to Nl.

In FIG. 4, the single note key assigner 14A generates time-division multiplexed key data for 6 keys starting from the 9th time slot.
Therefore, the time division multiplexed key data TDM output from the multiplexer 30 in FIG. 3 is input to the launch circuit 34 in FIG. Therefore, the key data TDM delayed by 8 time slots is output from the launch circuit 34. On the other hand, at the first time slot, the final stage ( The least significant bit Nl of the key code KC output from Q16) is at the 8th stage (Q8) in the 9th time slot after 8 time slots.
).

Therefore, in order to synchronize with the delay of the key data TDM in the latch circuit 34 (FIG. 4), the shift register 25 is
The output of the eighth stage (Q8) in FIG. 3 is taken out as a serial key code KC (9-) and supplied to the single note key assigner 14A in FIG. 4. With this key code i, (9~) learn each bit in order from the lower pit between the 9th time slot and the 15th time slot] -9N2. N3. N4. Bl, B2. B3 is lined up. This key code i(9-) is inverted by the inverter 35 in FIG. 4, and the official key code KC as described above is output from the inverter 65 in serial format.

In Fig. 4, the single note key assigner 14A mainly uses the following three keys.
perform one function. One is to select the key code KC of the most pressed key, the other is to detect a new key press, and the other is to select the key code KC of the most pressed key. The purpose of the present invention is to prohibit processing related to continuously pressed keys for a certain period of time, and to enable detection of an initial touch during that period. A new key press is detected when a key is pressed for the first time after all keys have been released (
This is called any new key-on), and the case where the pressed key is changed to a new key in legato style (this is called legato new key-on). If any new key-on is detected, the flip-flop AKQ is set, and if any new key-on is detected, the flip-flop NKQ is set. 7 lip-flops AKQ or NKQ by new key-on detection
When is set, the counter 16 shown in FIG. 3 is operated as a timer and outputs the initial 7/7 ringing signal Is for a certain period of time (approximately 10 m5).

Processing related to the continuously pressed keys is prohibited, and when the predetermined time period ends, an attack pitch start signal AS or a slur start signal ss is generated to start attack pinch or slur control. The highest pressed key key code register 66 is for temporarily storing the key code XKC of the highest pressed key, and the single note key code register 37 is for storing the key code M of the pressed key that is sounded in the single note mode.
This is for memorizing KC. When the certain period of time has ended, the key code XKC of the register 36 is changed to the register 3.
7. Therefore, when a new key is pressed, the pressed key key code MKC for the single-note mode does not change immediately, but changes after the predetermined period of time.

Each flip frotsuno XKQ, MK1, MK2゜AKQ
, NKQ, and TM6 are loaded with input signals by timing signal 6V8 (see Figure 5) and loaded with input signals by timing signal 1y8 (see Figure 5).
Switch the output in synchronization with the figure).

Therefore, the loaded signal is continuously output for 8 time slots from the generation time slot (1st, 9th, 17th, or 25th time slot) of signal 1y8.

Flip-flop XKQ is only used to indicate that some pressed key has been detected in one scanning cycle. The key data TDM output from the latch circuit 34 is N
1'', N1'' is loaded into this 7-rip 70 ring XKQ via the AND circuit 68 and the OR circuit 40.

“1” of this flip-flop XKQ is an AND circuit 69
and is held via the OR circuit 40. When one scanning cycle is completed, the output of the inverter 41 becomes N0'', the AND circuit 39 becomes inoperable, and the 7 lip-flop XKQ is reset. )N3, π2.
Nl is input to the AND circuit 42, and the upper 4 bits B3,
12. Bl and N4 are input to an AND circuit 46.

The output signal N7 of the AND circuit 42 and the output signal 815' of the AND circuit 43 are input to the AND circuit 44 in FIG. At the end of one scanning cycle, the count value is 83 to N1.
All the pits in the signal become N1'', and both the signals N7 and B15 become N1'', and the condition of the AND circuit 44 is satisfied. A timing signal 9T16 (see FIG. 5) is input to the other input of the AND circuit 44. Therefore, the output of the AND circuit 44 becomes 1'' from the 9th time slot to the 16th time slot at the end of one scanning cycle. Now, this signal SCE is inverted. Therefore, when the next key is pressed, the flip 70 knob The output of is N1
”When no key is pressed, XKQ is always “0”.

The AND circuit 45 to which the signal obtained by inverting the output of the flip-flop XKQ and the key data TDM output from the latch circuit 64 are input is for detecting the highest pressed key. That is, due to the delay of 8 time slots between input and output in flip-flop XKQ, the key data TDM of the most pressed key is '1' initially in one scanning cycle
'', the output of the flip-flop XKQ is still ``θ'' during the 8 time slots of the rising edge of the key data TDM, that is, the 9th to 16th time slots, sb,
The inverted signal is Nl''. Therefore, the condition of the AND circuit 45 is satisfied only between the 9th to 16th time slots (8 time slots in total) at the rising edge of the key data TDM of the most pressed key, and The output signal XS becomes N1''. The AND circuit 46 is enabled by N1'' of the signal XS, and the key code KC of the most pressed key given from the inverter 65 is loaded into the register 36 via the AND circuit 46 and the OR circuit 47.

As mentioned above, the key code KC output from the inverter 35 and the key data TDM output from the latch circuit 64
Between the 9th and 16th time slots when the signal xs becomes 1llff, the key code KC of the most pressed key is loaded into the register 36 in order from the lower bit (all bins of the key code KC). Nl-B3 are loaded into register 36 between the 9th and 15th time slots;
In the 16th time slot, count data unrelated to the key code KC is entered. Therefore, a signal obtained by inverting the timing signal 16y32 is applied to the AND circuit 46, and in the 16th time slot, the signal is forcibly set to '0''.
is loaded.

Highest pressed key key code XK loaded into register 36
C is self-held via an AND circuit 48. A signal obtained by inverting the signal Xs by an inverter 49 is added to the other input of the AND circuit 48, enabling the AND circuit 46 and clearing the self-holding state when the key code KC is loaded into the register 66.

The register 66 and the register 37 to which the contents xKc of the register 36 are transferred are 8-stage/1-bit shift registers, and are shift-controlled by system clock pulses φ1 and φ2. Therefore, registers 66 and 67
The contents of are rotated every 8 time slots. In the figure, the weights of each stage of registers 36 and 37 at the 9th, 17th, 25th, or 1st time slot are shown.

Flip-flop MK1 is for indicating that some pressed key was detected in the previous scan cycle. When one cycle of scanning is completed, that is, when the scanning end signal SCE is "1", the flip 70
On the condition that '1' is stored in KQ, the AND circuit 50 outputs 1', and loads '1' into the flip 70 tube MK1 via the OR circuit 52. 1" of this flip-flop MK1 is the AND circuit 51 and the OR circuit 5.
2 for one scan cycle, and is reset by the scan end signal SCE.

Flip-flop MK2 is for indicating that some pressed key was detected in the scan cycle before the previous one. At the end of the scan end signal SCE, the output of the flip-flop MKI is loaded into the flip-flop MK2 via the AND circuit 56 and the OR circuit 55. The AND circuit 54 is for holding the memory of the flip-flop MK2 for one scan cycle, and becomes inoperable when the scan end signal SCE is generated to reset the slip-flop MK2. These three 7-linopflops XKQ
, MKl, and MK2 are useful for detecting key suppression and key release in single note mode without chattering.

The flip 70 knob AKQ is for indicating that the aforementioned any new key-on has been detected. The AND circuit 56 includes the output of the flip-flop 70 and the output of the flip-flop MK1. MK2゜AKQ, NKQ inverted output,
and a scan end signal SCE are given, and when the any new key is turned on, the condition is met and 1'' is output at the timing of the scan end signal SCE.In other words, the AND circuit 56
In , no key was pressed at all in the previous scan cycle and the scan cycle before the previous one (both MKl and MK2 were 'o'), and key press was detected for the first time in the current scan cycle (X
Any-key-on is detected on the condition that KQ is "1"). The inverted outputs of AKQ and NKQ are connected to the AND circuit 56.
The reason added to AKQ or NKQ is '1''
This is to prevent the condition of the AND circuit 56 from being satisfied when , and to prevent the timer described later from being reset to the start state many times. The output signal "1" of the AND circuit 56 passes through the OR circuit 58 and is loaded into the 7 lip-flop AKQ. 1" of this slip-flop AKQ is an AND circuit 57 and an OR circuit 58.
is held for a certain period of time.

The output signal "1" of the AND circuit 56, that is, the any new key-on detection signal is also used as a timer start signal. This output signal "'1" is passed through the OR circuit 59 to 2
It is input to the 7th lip flop 60°61 of the stage. These flip 70 knobs 60° 61 are 7 flip flops
Like KQ, it is controlled by timing signals 6y8.1y8. The outputs of both flip-flops 60 and 61 are applied to an OR circuit 62, further inverted by an inverter 63, and input as a signal z1 to an AND circuit 36 in FIG. ,
The any new key-on detection signal output from the AND circuit 56 is synchronized with the scan end signal SCE, and the any new key-on detection signal is
It remains "1" for 8 time slots up to the time slot. This is connected to flip-flops 60, 61 and OR circuit 6.
2, the width is expanded to 16 time slots, and the output signal Zl of the Inno Kuichi Taro 6 is set to OI+ during the 16 time slots. Otherwise, the signal z1 is always 1'', enabling counting operation in the counter 16 (FIG. 3). During the 16 time slots when the signal Z1 is 0'', the AND circuit 66 (FIG. 3) ) becomes inoperable and clears the contents of all 16 stages of the shift register 25 to 0''.In this way, the counter 16 has a count value of all 0''.
”, and the timer function starts.

Of the count value launched in the latch circuit 27 of FIG. 3, the bit with a weight of about 8 ms in time representation is input to the AND circuit 64, and the bits with weights of about 4 ms and about 2 ms are inverted, respectively, and the bit is inputted into the AND circuit 64. 64 other inputs. The output signal TM5 of this AND circuit 64 is applied to an AND circuit 65 in FIG. The AND circuit 65 receives signals N7 and B15 from the AND circuits 42 and 46 in FIG.
is input, and furthermore, the timing signal 9T16 and the OR circuit 6
6 outputs are added. The outputs of flip-flops AKQ and NKQ are added to the OR circuit 66. The output of the AND circuit 65 is used as a timer end signal QR. The reason why the output of the flip-flop AKQ or NKQ is input to the AND circuit 65 is to operate the timer function only when these seven flip-flops are set, that is, only when the new key is on.

The count value of the lower 10 bits of the counter 13 is “100”.
1111111", that is, when approximately 10 ms has passed since it was cleared by signal z1,
When all the conditions of the AND circuits 42, 43, and 64 (FIG. 3) are satisfied, the signal N7 is applied to the AND circuit 65 of FIG.
．． B15. TM5 becomes all 1". At this time, signal 9
Corresponding to T16, the output signal QR of the AND circuit 65 becomes "pi" during the 9th to 16th time slots. Note that the indications (9 to 16) placed next to the signal lines in the figure indicate that this signal is This means that it occurs from the 9th time slot to the 16th time slot.

This timer end signal QR is inverted by an inverter 67 and applied to an AND circuit 57. Therefore, flip-flop A
1" of KQ is the timer end signal. Approximately 1" until R occurs.
This timer end signal QR is shown in bold for 0m5.
Cleared when this occurs. For more information, see Timer end signal. When R falls at the 17th time slot, the output of the Noritsu flop AKQ also falls to "OI+".

When the timer end signal QR is generated, the flip-flop
On the condition that KQK is set to ``1'' (the key is being pressed), the output signal KS of the AND circuit 68 becomes 1''.
3. This signal KS enables the AND circuit 69 and sends the highest pressed key key code XKC (which indicates a new pressed key) of the register 36 to the register 37 via the AND circuit 69 and the OR circuit 70. Load into. The key code of the new highest pressed key loaded into the register 37 is output from the key assigner 14A as the pressed key key code MKC for the single note mode, and is circulated through the register 37 via the AND circuit 71.

When loading a new key code XKC by the signal KS, the AND circuit 71 becomes inoperable and the old key code MKC is cleared.

AND circuit 72, 73.74, OR circuit 75 and delay 7
The resource 70 tab 76 is for comparing the key codes XKC and MKC of the registers 36 and 37. The inverted signal of key code MKC and key code XKC are input to AND circuit 72, and the inverted signal of key code XKC and key code MKC are input to AND circuit 73. Key codes XKC and MKC have the same weight bits N1 to B3
are synchronously output from registers 36 and 37, respectively.
If the values of both key codes MKC, A signal obtained by inverting the self-held highest pressed key detection signal The memory of step 76 is cleared.

The flip-flop NKQ is for indicating that the aforementioned legato new keyo has been detected. The AND circuit 77 is for detecting legato 221 key-on, and includes the output signal NEQ of the flip-flop 76, the single note mode selection signal MONO, the flip-flop XKQ,
MK i, MK2 output signal, flip 70 tube AKQ
, a signal obtained by inverting the output of NKQ, and a scanning end signal S
CE is input. The single note mode selection signal MONO is input to enable detection of legato new key-on only in the single note mode. As mentioned above, register 6
When the key codes XKC and MKC of 6 and 67 are different, the output signal NEQ of the flip-flop 76 becomes 11pa.

"1" of this signal NEQ indicates that a new key has been pressed. If this new key press corresponds to any new key-on, the conditions of the AND circuit 56 are satisfied as described above, and the flip 70 knob AKQ is set, so its inverted signal becomes '0', and the AND circuit 77 condition does not hold.If this new key press corresponds to legato new key on, flip 70 knob AKQ
are set, each has 7 linog fronts XKQ,
The outputs of MKI and MK2 are 1", indicating that some key is being pressed continuously. Therefore, when the legato new key is on, the condition of the AND circuit 77 is satisfied at the timing of the scan end signal SCE. , '1' is loaded into the flip-flop NKQ via the OR circuit 79. 1'' of this flip-flop NKQ is an AND circuit 78
Self-maintained through .

On the other hand, the legato new key-on detection signal output from the AND circuit 77 is passed through the OR circuit 59 to the delay flip-flop 60, similarly to the any new key-on detection signal.
is used as a timer start signal. Therefore, based on legato new key-on detection, the counter 16 in FIG. 3 functions as a timer in the same manner as described above, and approximately
After 0m5, the timer end signal QR is output from the AND circuit 65 (FIG. 4). This timer end signal QR makes the AND circuit 78 inoperable, and the flip 70
KQ is reset. Therefore, the 7-lip flow soap NKQ bolds l'' for about 10 m5 from the time of legato new key-on detection.

Also, as mentioned above, the timer end signal. Based on R, the AND circuit 68 outputs a signal KS, and the new highest pressed key key code XKC stored in the register 36 is loaded into the register 67.

The flip 70 knob TM6 is used to indicate that the approximately 10 m5 time waiting period due to any new key-on has ended in order to form an attack pitch start signal in the double tone mode. The timer end signal QR is input to the flip-flop TM6 via the AND circuit 8o and the OR circuit 82, and when the waiting time of approximately 10 m5 for any new key-on is completed, the timer end signal QR determines that Flip 70 Tsubu TM6 to 6
1" is set. This flip 70 tube TM6 1
"1" is self-held via the AND circuit 81 and reset by the scan end signal SCE. Therefore, the "1" of the flip-flop TM6 is held for only one scan cycle. It should be noted that since legato new key-on is not detected in the double-note mode, even if the solve flop TM6 is set by the timer end signal QR based on the legato new key-on in the single-note mode, there is no effect.

AND circuits 83, 84, and 85 are for forming a key-off signal MKOF for single note mode. Each circuit 8
3, 84.85 is given a single note mode selection signal MONO, and is operable in the single note mode.The AND circuit 85 has a flip 70 knob MK 1 + MK
2 + N K Q inverted signal is input, 2
1'' is output on the condition that release of all keys is detected in consecutive scanning cycles.

The output 'I 1 I+ of this AND circuit 85 indicates a normal key-off. The reason why both MKl and MK2 are set to 0'' is to prevent chattering.The output of the flip-flop AKQ is input to the AND circuit 83, and the output of the flip-flop AKQ is input to the AND circuit 83.
II IHy is output during the waiting time of s. The output of the Noritsubu flop NKQ and a signal obtained by inverting the slur-on signal 5LON by an inverter 86 are added to the AND circuit 84, and on the condition that the slur effect is not selected, a waiting time of about 10m5 when detecting legato new key-on is applied. 9
Outputs 11″.

The outputs of the AND circuits 83, 84, and 85 are input to an OR circuit 87, and are used as a key-off signal MKOF for single note mode. This key-off signal MKOF is sent to the inverter 8.
The one reversed at 8 is the key-on signal MKO for single note mode.
It is N. The musical tone signal generating section 21 (FIG. 2) may control the amplitude envelope based on this key-on signal MKON when generating a musical tone signal corresponding to the pressed key code MKC for the single note mode.

When any new key-on is detected in single note mode or when no slur effect is selected.
- When a key-on is detected, attack pinch control is performed, and the above-mentioned fixed waiting time (approximately 1
0m5), output 1 of AND circuit 86 or 84
11. , N, the key is forcibly turned off. Then, in order to remove the sustain of the front sound during the forced key-off state during this waiting time,
The outputs of the AND circuits 83 and 84 are output from the key assigner 14A via an OR circuit 89 as a forced dump signal FDMP, and are applied to the musical tone signal generating section 21 (FIG. 2).

The output of the AND circuit 84 is also given to an OR circuit 90.

Also, the output of the flip-flop AKQ is output from the AND circuit 91.
is applied to the OR circuit 90 via. Note that the AND circuit 5B, 80 has only one input.

91 etc., the input signal simply passes through, and although it is not particularly necessary, it is included for convenience as shown in the figure. The output of the OR circuit 9° is used as an initial sensing signal IS for initial touch detection. This initial sensing signal I S l"t, single note% -g;hruiha double note mo~
If any new key is turned on regardless of the key, the signal will remain "1" for approximately 10 msO from the start of suppression of the new key based on the output of the flip-flop AKQ. Also, if there is a legato new key on when the slur effect is not selected in single note mode, the flip-flop NKQ
Approximately 10m5 from the start of pressing a new key based on the output of
The interval becomes "1". When the slur effect is selected in the single note mode, the initial sensing signal Is is not generated even if there is a legato 221 key-on.

The AND circuit 92 is for generating the active pitch start signal MAS for the single note mode, and the OR circuit 8
Key-off signal MKOF from 7, flip-flop XK
The output signal of Q and the timer end signal QR are input. During the waiting time of about 10m5 based on the new key-on detection, the key-off signal MKOF becomes 1" by the output signal of the AND circuit 83 or 84, and the AND circuit 92 becomes operational. When the waiting time ends, the key is pressed. (XKQ is “1”) Timer end signal QR
The output signal MAS of the AND circuit 92 becomes l'' during the 9th to 16th time slots corresponding to
is input to delay flip-flop 94 via OR circuit 96. This flip 70 tube 94 loads the input signal with the timing signal 13y32 and switches the output in synchronization with the signal 17T24. Therefore, Hen of the signal MAS generated in the 9th to 16th time slots is loaded into the 7th lip 70 tube 94 in the 13th time slot, and
1 from the time slot to the next 16th time slot
It is output as the attack pitch start signal As during the key time (32 time slots).

The AND circuit 95 is for generating the attack pitch start signal 'F:AS for the double note mode, and the inverter 96 inverts the output of the flip-flop TM6, the inverted signal of the output of the flip-flop XKQ, and the single note mode selection signal MONO. signal and key data TDM from the latch circuit 34 are input. In the double tone mode, the output 11xjy of the inverter 96 enables the AND circuit 95 to operate. As mentioned above, the output of the flip-flop TM (S) is "1" during one scanning cycle immediately after the end of the approximately 10m5 time wait based on any new key-on detection, and the key data T of the most pressed key in this cycle is
The condition of the AND circuit 95 is satisfied during the 9th to 16th time slots of the rising edge of DM. The output signal EAS of the AND circuit 95, which becomes II I II between the 9th and 16th time slots, is input to the slip 70 tube 94 via the OR circuit 93, and similarly to the above, from the 17th time slot to the next 16th time slot It is output as an attack pitch start signal As for one key time up to the time slot.

The AND circuit 97 is for generating the slur start signal SS, and outputs the timer end signal QR1, the output of the flip-flop XKQ, the single note mode selection signal MONO, the single note mode key-on signal MKON, and the signal NEQ indicating the mismatch of key codes. is input. registers 36 and 37
Key code XKC.

If MKC does not match (NEQ is 1"), the waiting time is in progress (AKQ or NKQ is "1"), and at this time the conditions of AND circuits 83 and 84 are not satisfied (MKON 1”), meaning that the slur effect was selected and legato new key on. Therefore, when the slur effect is selected and there is a legato new key-on, the key is currently being pressed (XKQ
is 1''), the output of the AND circuit 97 becomes ``1'' during the 9th to 16th time slots.

This output "'1" is input to the flip-flop 94,
As described above, the slur start signal SS is output for one key time from the 17th time slot to the next 16th time slot.

As described above, the attack pitch start signal AS and the slur start signal SS are generated after the waiting time of about 10 m5 has ended. The attack pitch start signal AS is generated when any new key is turned on in single note mode or when legato new key is turned on when slur is not selected, and is generated when any key is turned on in double note mode. Further, the slur start signal SS is generated when a legato 221 key is turned on when selecting a slur in the single note mode.

A detailed example of the analog voltage multiplexer and A/D converter various effect setting operator group 15 is shown in FIG. For convenience of illustration, the A/D converter 17 is the A/D converter 18.
The part shown in FIG. 6 is shown in FIG. 6, and the part of the control and storage section 19 is shown in FIG. 7. 3. In FIG. It has volumes v1 to Vi for setting with analog voltage. Vl is the vibrato speed (frequency), v2 is the vibrato speed (depth), v4 is the delay vibrato time, and v5 is the speed of pitch change in the slur effect (
(slur speed) and v7 are for setting the attenuation speed (sustain speed) of the sustain portion of the amplitude envelope, respectively. V3, V6, and V8 are volumes for adjusting the sensitivity of the output signal of the touch sensor 11.

V6 is for adjusting the sensitivity of the key touch detection signal for setting the depth of aftertouch vibrato, v6 is for adjusting the sensitivity of the key touch detection signal for setting the level of aftertouch level control, and v8 is for adjusting the sensitivity of the initial touch detection signal. It is something to be adjusted.

The initial touch detection signal whose sensitivity is adjusted by volume v8 is used for two purposes. One is for setting the initial value of the attack pitch control, and the other is for setting the level of the initial touch reple control.

As the touch sensor 11, an aftertouch sensor 11A common to each key is used. Aftertouch sensor 11A
The sensor may be of any type as long as it can detect a key touch while the key is being pressed, for example, it may detect a key touch in response to the pressing speed, the depth of depression, the pressing force or strength, etc. 3. The output signal of the aftertouch sensor 11A is applied to the initial touch sensitivity adjustment volume V8 via an amplifier 98, and is also applied to a low-pass filter 99. The output of the low-pass filter 99 is added to an aftertouch vibrato sensitivity adjustment volume v3 and an aftertouch level sensitivity adjustment volume V6. The low-pass filter 99 is for suppressing sudden fluctuations in the touch detection signal used for aftertouch control.

The aftertouch sensor 11A is used for both initial touch detection and aftertouch detection. For example, if the touch detection signal output from the aftertouch sensor 11A is as shown in FIG. 8(a), the initial sensing signal I
The peak value of this touch comparison signal is detected within about 10 m5 where s (FIG. 8(b)) is given, and this peak value is held and used as the initial touch detection signal.

As described above, sound generation starts after the initial sensing signal IS falls (after peak value detection is completed). Also,
The aftertouch sensor output signal when peak value detection is performed (when Is occurs) is not used as the aftertouch detection signal, but the sensor output signal at other times is used as the aftertouch detection signal. By doing so, there is no need to separately provide an initial touch sensor and an aftertouch sensor, which is economical and also simplifies the sensor device provided below the key.

The eight analog voltages set or adjusted by the volumes v1 to v8 are converted into digital data using one A/D converter 18. For this purpose, an analog voltage multiplexer 16 is provided for each volume v1.
The analog voltages of ~v8 are time-division multiplexed and sent to the A/D converter 18. Further, a control and storage unit 19 shown in FIG. 7 is provided in connection with the A/D converter 18, and the A/D converter 18
It controls the time-division A/D conversion operation in the D converter 18 and the demultiplexing operation of digital data obtained by this A/D conversion. This more advanced A/D conversion operation allows the circuit configuration to be considerably simplified.

The control and storage unit 19 shown in FIG.
~Registers 101 to 10 as storage means corresponding to v8
Contains 8. (Vl) to (v8) written near each register 101 to 108 are the corresponding volumes v
1 to V8.

These registers 101-108 store digital data obtained by digitally converting the output voltages of the corresponding volumes V1-V8, respectively.

These registers 101-108 receive system clock pulses φ1. It consists of an 8-stage 71-bit circular shift register whose shift is controlled by φ2. The numbers written in the blocks of each stage of each register 101 to 108 indicate, as an example, the weight of data in each stage at the 1st, 9th, 17th, and 25th time slots.

The unit of the weighting value in each register 101 to 108 is "H2" (frequency) or "cent" (pitch deviation) depending on the nature of each control element, as written near each output data display. Cent value indicating depth), “msJ
(time), dBJ (level). These weight indications are only shown as an example, and are not very important in terms of circuit operation. This is useful in clarifying the relationship with time slots.

The control and storage unit 19 in FIG. 7 includes each register 101 to
Multiplex and demultiplex control circuits 111 to 118 are provided corresponding to 108. circuit 112
117 have the same configuration, only the circuit 112 is shown in detail, and the circuits 113 to 117 are omitted. The multiplex and demultiplex control circuits 111 to 117
corresponds to the time division multiplexing operation in the analog voltage multiplexer 16 (FIG. 6).
7 is multiplexed and sent to the A/D converter 18 (FIG. 6) for use in time-division A/D conversion operations, and the resulting digital data is sent to the A/D converter 18 (FIG. 6). It has a function of inputting and demultiplexing the received signals from the registers, and loading them into the corresponding registers 101 to 107. However, the control circuit 118 corresponding to the register 108 for storing initial touch detection data does not have a multiplex function (a function of sending the data of the register 108 to the A/D converter 18).

In FIG. 6, the control input of the analog voltage multiplexer 16 includes eight output signals H from the decoder 29 of FIG.
O-H7 is applied, and an initial sensing signal Is is also applied from the OR circuit 90 of FIG. The decoder 29 outputs bit B2. of the count value of the counter 13 (FIG. 3). Bl.

The decoded value of N4 is output as signal HO-H7. Each of the signals HO to H7 sequentially becomes "1" in the order shown in FIG. 9(a). 1 signal) 10-H7 is 1"'1"
The duration of this is 8 key times, and each signal HO-H7 makes two rounds during one scanning cycle.

The multiplexer 16 normally samples the analog voltages of the volumes 1 to V7 in sequence according to the signals H1 to H7 as shown in FIG. 9(b), multiplexes them, and outputs them.

When the initial sensing signal Is is "1", sampling of v1 to v7 by the above-mentioned signals H1 to H7 is prohibited, and the analog voltage from the initial touch sensitivity adjustment volume 8 is continuously selected and output. The output voltage of multiplexer 16 is provided to input B of analog comparator 110 within A/D converter 18 . First, normal A
/D conversion will be explained, and then A/D conversion of the initial touch detection signal will be explained.

A/D converter f 8U, system clock pulse φl,
It includes a data register 100 consisting of an 8-stage/1-bit circular shift register whose shift is controlled by φ2. Normal A/D converter 18
The D conversion operation is performed in a time-division manner corresponding to the time-division sampling of each analog voltage by the multiplexer 16. Initially, digital data resulting from 111 A/D changes is taken into the data register 1006, and this previous data is converted into an analog voltage by a digital/analog conversion (hereinafter referred to as D/A conversion) circuit 119. is added to the input A of the comparator 110 and compared with the analog voltage from the multiplexer 16, and A/D conversion is performed by counting up or down the contents of the data register 100 according to the comparison result.

The digital data resulting from the previous A/D conversion is input into the data register 100 from one of the registers 101 to 107 in FIG. 7 immediately before the sampling timing. Therefore, the signal N7/25T32 is used as the third control signal.
The AND circuit 120 in the figure and each control circuit 111 in FIG.
The signal is input to AND circuits 121, 122, and 125 in 117. In FIG. 3, an AND circuit 120 is supplied with the output of the AND circuit 42 and a timing signal 25T32. The AND circuit 42 is the lower three of the count value of the counter 16.
Bit N3. N2. The condition is satisfied when Nl is 111''. This indicates the last one key time in each of the sampling signals HO to H7.

Signal 25T32 is the 25th to 3rd signal in one key time.
It is "1n" during the 8 time slots up to the 2nd time slot. Therefore, the signal N7.25T32 is set to 1" in the last 8 time slots from 0 to n7.

In FIG. 7, the control circuits 111 to 117 are supplied with the output signal HO-H7 of the decoder 29 (FIG. 3), and based on this signal HO-H7 and the signals N7 and 25T32, the multiplexer and demultiplexer control at the same time. Each of the control circuits 111 to 117 includes a multiplexer AND circuit 124, 125, a demultiplex AND circuit 126, 127, and a hold AND circuit 128.
Contains ゜129. In the last 8 time slots of the sampling timing, the data stored in the register (one of 101 to 107) corresponding to the next sampling timing is transferred to the multiplexer AND circuit 1.
24, 125 and is supplied to the data register 100' (FIG. 6) of the A/D converter 18, and at the same time, the data A/D converted at the sampling timing is sent to the demultiplexing AND circuit 126. ,1
27, and is taken into a register (one of 101 to 107) corresponding to the sampling timing.

Such demultiplexing and multiplexing control for the registers 101 to 107 is performed at times other than the approximately 10 ms waiting time for initial touch detection. For this purpose, an initial sensing signal ISO inversion signal IS is applied from an inverter 130 to each AND circuit 121, 122, 123 in the control circuits 111 to 117, and is enabled when Is is ffOI+. There is. Moreover, each AND circuit 121, 122 .
123, the signal N7-25T32 is commonly input.

Each AND circuit 121, 122, 123 has signals HO, H.
1 and H2 are input separately, and each control circuit 113 to 1 is inputted separately.
An AND circuit equivalent to the AND circuit 123 of No. 17 has a signal H.
3 to H7 are input separately.

When the signal HO is 1", the analog voltage multiplexer 16 (FIG. 6) selects which volume v1, as shown in FIG.
The voltage of ~v8 is also not sampled. Therefore, at this time, the A/D converter 18 does not perform A/D conversion operation ≧ Signal N in the last 8 time slots of signal HO
When 7.25T32 becomes 1", the condition of the AND circuit 121 (FIG. 7) is satisfied, and the AND circuit 121 gives "1" to the AND circuit 124 and the OR circuit 131. Therefore, the OR circuit 161 The output signal TiM is generated as shown in FIG. 10). FIG. is each control circuit 11
The outputs of AND circuits 122 and 123, which are equivalent to AND circuit 121 in 1 to 117, are provided, respectively. In addition, the 1st O
In the figure and other timing charts, numbers such as "25 to 32" written in the pulses indicate the order of the time slots.

Serial 8-bit digital data output from the final stage of register 101 is applied to the other input of AND circuit 124. This serial digital data is arranged sequentially from the least significant bit (hereinafter referred to as LSB) to the most significant bit (hereinafter referred to as MSB) between the 25th to 32nd time slots. AND circuit 12
The 8-bit digital data stored in register 101 by being enabled during the same 8 time slots as signal TiM shown in FIG.
The signal is sampled by an AND circuit 124 in synchronization with , and is provided to an OR circuit 132 . Output 0DD of OR circuit 132
(Old digital data) is supplied to the A/D converter 18 in FIG. 6, and loaded into the data register 100 via the OR circuit 133 and the adder 134. Therefore,
When the next sampling signal H1 rises to 1'', the data in the register 101 (indicated by VER) has been transferred to the data register 100. Incidentally, the outputs of the multiple register circuits 124 and 125 of the respective control circuits 111 to 117 are applied to the OR circuit 132 (FIG. 7). VBR data of each register 101 to 107
, VBD, KVBD, DYER (or DEL), SR
Assuming that M, SRE, ATL, and STR are shown, the data output from the data register 100 at the beginning of each sampling timing is as shown in FIG. 9(C). That is, as shown in FIG. 9(b), the digital conversion results of the analog voltages of the sampled volumes v1 to v7 at the previous sampling timing are transferred from the data register 100 corresponding to the current sampling timing of the same volumes V1 to v7. Output.

On the other hand, the signal Ti output from the OR circuit 131 in FIG.
M is applied to A/D converter 18 in FIG. This signal TiM is inverted by an inverter 135, and the AND circuit 13
6 is rendered inoperable. The AND circuit 136 is for holding the data in the data register 100, and inhibits the holding of the register 100 by the signal TiM when loading the old data ODD. The signal TiM is input to a three-stage delay flip-flop (shift register) 137. This flip-flop 167 loads the input signal with the timing signal 6y8 and switches the output in synchronization with the signal ly8. Therefore, the output signal TiM1 of the first stage becomes '1' between the first to eighth time slots of the rising edge of the sea urchin signal H1, as shown in FIG. 10(C).
The signal TiM2+3 obtained by combining the second and third stage outputs by the OR circuit 168 is converted into a signal T as shown in FIG. 10(d).
1'' between the 9th and 24th time slots after the falling value of iM1.

In FIG. 6, the data register 100 constitutes an 8-bit serial counter together with a 1-bit full adder 134. The launch circuit 169 is for latching the outputs (ie, count values) of each stage of the register 100 in parallel at the timing of the signal 1y8S. 2
The first signal I V8S is generated. 9th. 17th. 25th
In the time slot, data from MSB to LSB is sequentially arranged in the first to eighth stages of register 100, and is latched by latch circuit 169. As shown in FIG. 10(e), in the 8th time slot of the rise of signal H1, the contents of launch circuit 139 indicate data VBR of register 101 (FIG. 7). The contents of this latch circuit 169 change every eight time slots in accordance with changes in the count value (the contents of register 100).

The output of the latch circuit 169 is given to the D/A conversion circuit 119 and converted into an analog voltage. Comparator 110 compares inputs A and B, and when B≧A, that is, when the value of the analog voltage applied to input B from multiplexer 16 is the same as or greater than the value of the data in data register 100, the 6-bit Output. The output of this comparator 110 is applied to a delay flop 140, and is output after being delayed by 8 time slots in synchronization with the signal 1y8. The output of the flip-flop 140 is inverted at an inverter 141 and applied to an AND circuit 142 for down-counting.The output of the flip-flop 140 is also inverted by an AND circuit 142 for up-counting when an initial touch is detected.
46. The AND circuit 144 is a normal A/
This is for up-counting during D conversion operation.

An inverted signal T1 of the initial sensing signal Is is sent from the inverter 130 in FIG. 7 to the A/D converter 18 in FIG.
is given. This signal ■ is applied to AND circuits 142 and 144, and these circuits 14 are applied at times other than initial touch detection, that is, during normal A/D conversion operation.
2,144 operational. Signal Is to inverter 1
The signal Is inverted at 45 is applied to an AND circuit 143, enabling this circuit 143 at the time of initial touch detection.

During normal A/D conversion operation, the contents of the data register 100 are amplified by one count at the timing of the signal TiM1, regardless of the comparison result of the comparator 110. That is,
The signal TiM1 and the signal iys are input to the AND circuit 144, and the output of the AND circuit 144 becomes "1" at the first time slot when the signal TiM1 rises. The output "'1" of the AND circuit 144 is applied to the input A of the adder 134 via the OR circuit 146. Signal TiM1 is “1”
”, the signal TiM is 0, and the data register 10
The output of 0 is applied to the input B of the adder 164 via the AND circuit 166 and the OR circuit 136. At the timing of signal ly8, the least significant bit of data VBH loaded into register 100 is added to input B of adder 134. Therefore, 1" is added to the least significant bit. If there is a carry out signal, Bi is output from the carry out output C6+1 with a delay of one time slot and is added to the input C1 via the AND circuit 147. At the timing of the least significant bit. To prevent the carry signal from being added, the AND circuit 147 is disabled by the signal 1ys.

In this way, 1 is added to the previous data VBH in the section TiMl shown in FIG. 10(f). This calculation result 4 result 1
“VBR+IJ is latch circuit 1 during the next TiM2 interval.
69 (FIG. 1O(e)).

In the section jiM2 in FIG. 10(f), the data “vBR
The comparator 110 compares the analog voltage (A) of “+1” with the current analog voltage (B) of
≧A” is established, no addition or subtraction is performed and “VB
R+jJ is held in register 100. On the other hand, 1B≧A
'' does not hold, then p l'-A)BJ (7), then f-ta ``subtract 1 from VBR+IJ. [A
:> When BJ, the output of the delay flip-flop 140 is "0", and the output from the inverter 141 to the AND circuit 1
42 is given a value of 1". This AND circuit 142 is given a signal TiM2+3 from the OR circuit 168, and becomes operational during the intervals T i M 2 and TiM3 (see FIG. 10(f)). When the condition of the AND circuit 142 is satisfied in the interval TiM2, the output of the AND circuit 142 becomes 1'' during the interval 'piM2 (during 8 time slots). The output "1" of the AND circuit 142 is applied to the input A of the adder 164 via the OR circuit 146. Therefore, "1" is added to all bits of the data FVBR+IJ in the register 100, effectively counting down by one. It is done.

Therefore, by calculating the interval T iM2, register 100
The value of the data obtained is “VBR+IJ” or “VB
R(=VBR+1-1)J, and this data is latched by the latch circuit 139 in the interval TiM3 (see FIG. 10(e)).

In the section 'I'iM3, the data of the latch circuit 169 [VB
The comparator 110 compares R+1ji or [VBRJ with the current analog voltage of the volume v1, and if "B≧A" is established, the current value "VBR+1" or "V B RJ is held. On the other hand, when [>BJ, the AND circuit 14 is held as described above.
1" is output from 2, and 1 is subtracted from the data in the register 100. By this second subtraction, the data in the register 100 becomes rvBR-1 (=VBR+1-"1-1).When the J section TiM3 is Irf, the signal TiM2+3 falls,
Ant circuit 142 becomes inoperable.

Therefore, subsequent counting operations are stopped. In this way, A
The /D conversion operation is performed in 3 sections T i M 1 - T i M3 (24 time slots) at the rising edge of the sangrifugal signal H1.
It is carried out only between.

The value of data VBR (A
) and the setting value of the volume v1 sampled this time (
If B) matches, the contents of the register 100 become rVBR+IJ by l addition in the interval TiMl, so A)B is established in the comparison in the interval TiM2, and 1 is subtracted and the contents of the register 100 become rVBR
Becomes BRJ. In the comparison in the interval T i M 3, A=B holds true, and the subtraction of 1 is not performed. Therefore, the same data rVBRJ as last time is ultimately held in the data register 100.

The data VBRQ value (A
), if the setting value (-B) of the currently sampled volume ■1 is larger than
Even so, the comparator 110 only holds that either B=A or B)A holds true. Therefore, no subtraction is performed in 10 sections TiM2 and TiM3, and finally rVBR+
IJ is held in register 100.

The data VBRO value (A
) If the setting value (B) of the volume v1 sampled this time is smaller, the intervals T i M 2 and T
In iM3, A)B always holds true.

Therefore, 1 subtraction is performed twice after 1 addition, and finally rVBR-IJ is held in register 100.

As mentioned above, the maximum amount of change in digital data in one sampling period (approximately 1 m5) is limited to ±1. This is done in order to prevent sudden changes in the analog setting values by volumes v1 to v7, since responding as they are will cause unpleasant noises such as clicks, and to prevent the analog setting values from changing due to noise etc. This is for reasons such as not reacting to sudden, temporary changes. The maximum amount of change in digital data in the I/Pling cycle is limited to ±IK, and in short, it is sufficient as long as smooth A/D conversion can be performed.

In addition, in one A/D conversion operation, three sections TiM
l, TiM2. The TiM3 is used to perform addition and subtraction, which is useful for preventing digital data from fluctuating wildly when the output of the comparator 110 is unstable due to noise or the like. For example, if B-A holds true in interval TiM2 but does not hold in interval TiM3,
Ultimately, the digital data does not change due to "+l" in the interval T iMl and "-1" in the interval TiM3.

Same, AND circuit 1 in which all outputs of latch circuit 169 are manually generated
48 and NOR circuit 149 (FIG. 6) are for detecting the maximum count value and the minimum count value, respectively. When the maximum count value is reached, the output of the AND circuit 148 disables the AND circuits 146 and 144 and prohibits up-counting. When the minimum count value is reached, the output of the NOR circuit 149 disables the AND circuit 142 and prohibits down counting.

Returning to the explanation when the sampling signal H,1 is generated, after the end of the interval TiM3, the digital data that is the A/D conversion result is sent to the AND circuit 166, the OR circuit 133,
It is circulated and held in the data register 100 via the input B of the adder 134.

The data in this register 100 is used as new digital data NDD by the AND circuit 126 for demultiplexing each of the control circuits 111 to 117 in FIG. .

127. When the signal H1 is "1", the AND circuit 122 of the control circuit 111 can operate, but while the signal N7.2'5T32 is 0', the condition is not satisfied, and the output of the AND circuit 122 is "θ".

The output "0" of the AND circuit 122 is inverted by an inverter 150 and provided to an AND circuit 128 for holding.

The data VBR of the register 101 is processed by this AND circuit 128.
and is cyclically held via the OR circuit 151.

In the last eight time slots of signal H1, signal N7-
- When 25T32 becomes "L", the condition of AND circuit 122 is satisfied, and from this AND circuit 122
“1” is given to 6. At the same time, AND circuit 122
The output "l" is applied to the multiplexing AND circuit 125 of the control circuit 112 corresponding to the next sampling signal H2, and also to the OR circuit 161. In the control circuit 111, the hold AND circuit 128 becomes inoperable due to the output "11" of the AND circuit 122, and the AND circuit 126 becomes operable. Therefore, the setting of the A/D converted volume V1 is performed at the timing of the signal H1. New digital data NDD indicating the value is selected by the AND circuit 126 and loaded into the register 101 via the OR circuit 151.The AND circuit 13122 outputs "l#" from the 25th to the 32nd time slot; The data NDD output from the data register 100 (FIG. 6) is exactly 8 bits from the least significant bit to the most significant bit arranged in serial order. Therefore, the second digital data NDD will be loaded into register 01 in order from the 25th time slot to the 32nd time slot, and the weight of each stage of register 01 in the first time slot will be as shown in the figure. The first stage is the most significant bit (-Hz), and as the stages progress, it moves to the lower pits, and the 8' stage is the most significant bit (-Hz).
It is Hz3.

On the other hand, the OR circuit 131 outputs a signal TiM in response to the output "l" of the AND circuit 122, and the AND circuit 1
25 and the OR circuit 132, the data VBD of the register 02 is sent to A/D as the old-gauge digital data ODD.
D converter 18 (FIG. 6'). and 1
．． When the sampling signal is switched to Hz, A/D conversion regarding the volume v2 is performed in the same procedure as described above. Hereinafter, control circuits 112 to 112 correspond to signals H2 to H7.
117 operates in the same manner as described above, and each volume V 3''~
A/D conversion regarding v7 is performed sequentially. thus,
Each register 101 to 107 contains each volume lb V
Digital data corresponding to the outputs of 1 to v7 are stored, respectively.

Similarly, the data display of the register 104 corresponding to the delay pib is DVER and DE.
The reason why there are two types of L is that the volume V4 is used both for setting the delay vibrato start time and for enveloping the delay vibrato depth change. DVER is delay vibrato envelope plate "data" for setting the rate of temporal change in depth in the delay vibrato, and its weight is indicated at the bottom in each stage block of register 104.

The reason why the unit of this weight is (Hz) is that the envelope change rate is expressed as a speed converted into a frequency. That is, - The time from the start to the end of the envelope corresponds to one cycle of the frequency display. DEL is delay vibrato start time data, and its weight is shown above in each stage block of register 104. Of course, the truth values of these two data DVER and DEL are not different, but only the weighting on the user side is different.

The reason why there are two types of data display in the register 105 corresponding to the slur speed (volume V51), SRM and SRE, is that 8-bit data is divided into a mantissa part and an exponent part and used in order to widen the dynamic range. The least significant bit is not used, and the lower 2nd to 5th bits are used as the mantissa part M1.M2.M3.M4, and the higher 3 bits are used as the exponent part E1.E2.E5.SRM uses the slur rate mantissa part. This is a data display, and SRE is a data display of the exponent part of the slur rate.

The initial sensing signal IS output from the OR circuit 90 in FIG. 4 is input to the delay flip-flop 152 in FIG. The two-stage delay flip-flop 152 is loaded with an input signal by the signal 6y8 and switches its output state in synchronization with the signal ly8. delay flip 70
The output of the first stage of knob 152 is applied to AND circuit 156 and then to 154. The output of the second stage is applied to AND circuit 154, inverted by inverter 130, and applied to AND circuit 153. The output of this inverter 130 is applied as a signal to the A/D converter 18 in FIG. The circuit 154 outputs a pulse with a width of 8 time slots in response to the fall of the signal IS.The outputs of the AND circuits 153 and 154 are applied to the OR circuit 161, and the outputs of the AND circuits 153 and 154 are applied to the A/D converter 18 in FIG. 6 as the signal TiM. The states of the signals TiM and ■s generated in response to the signal IS are shown in FIG.

In FIG. 6, the signal T
During the eight time slots in which iM is "1", AND circuit 166 is disabled and all bits of data register 100 are cleared to "0".

Further, when the signal IS becomes "θ", each of the control circuits 111 to 117 shown in FIG. 7 is rendered inoperable, and each of the registers 101 to 107 holds the stored data in circulation. Also, AND circuits 142 and 144 in FIG. 6 become inoperable, and AND circuit 146 becomes operable. AND circuit 1
46 is enabled for the first 8 time slots, the signal T i M is delayed by 8 time slots from the signal T i M
1 is l', and the output "0" of the inverter 156 inhibits the operation of the AND circuit 146. This is because the signal I
This is to wait for the state of each signal to become stable at the rising edge of s, but this processing does not need to be performed in particular. The signal ly8 and the output of the delay flip-flop 140 are applied to other inputs of the AND circuit 146. Therefore, if "B≧A" is established in the comparator 110, "1" is output from the AND circuit 146 at the timing of the signal ly8, and is applied to the input A of the adder 164 via the OR circuit 146.

As described above, the timing of this signal ly8 is the timing of the least significant bit of the data in the data register 100. Therefore, each time one pulse is applied from the AND circuit 146 at the timing of the signal -1y8 (approximately every 4 μs), the contents of the data register 100 are counted up by l.

While the initialization/song signal IS is being generated, the multiplexer 16 continues to select the analog voltage of the volume v8. Therefore, volume ■8
The touch detection signal whose sensitivity has been adjusted is exclusively applied to input B of the comparator 1100.

Since the data register 100 is initially cleared to all "θ", rB,<AJ is initially established in the comparator 110. The contents of data register 100 are rapidly counted up each time signal ly8 is generated until the value of data register 100 matches the value of the touch detection signal. When the count value of the data register 1000 matches the value of the touch detection signal, rB=AJ holds true in the comparator 110. Based on this, the contents of register 100 are further increased by lcount/'t-, and rB<AJ is established in comparator 110, and AND circuit 143 is disabled and counting is stopped. Thereafter, even if the level of the touch detection signal decreases, the data register 100 is not down/counted, so the peak value is held. Furthermore, when the touch detection signal power becomes larger than the value of the booster register 100, "B≧A" is established in the comparator 110, and an additional count-up is performed. In this way, the digital data corresponding to the peak value of the touch detection signal while the initial sensing signal IS is being generated is held in the second register 100. The peak value data held in the data register 100 is applied to the AND circuit 157 in the %l13 control circuit 118 in FIG. 7 via the data NDD line.

When the initial sensing signal Is falls after approximately 1 oms has elapsed from the start of the key press, the AND circuit 154 in FIG.
The output of 8 is synchronous with the 25th to 32nd time slot.
The interval between time slots is °l''. This AND circuit 154
The output "l" of is applied to the AND circuit 158. The output XKQS of the flip-flop XKQ shown in FIG. This delay flip-flop 159 is for synchronizing the output timing of the delay flip-flop 152.AND circuit 158
outputs "1" for 8 time slots on the condition that a key is pressed (XKQS is "B") at the end of the initial touch detection time.

The AND circuit 157 becomes operable by the output "l" of the AND circuit 158, and the data register 100 (sixth
The peak value data (NDD) of the touch detection signal held in FIG. Further, the peak value data held in the data register 100 is cleared by the signal TjM applied from the OR circuit 131 to the inverter 165 in FIG. Loading of the peak value data corresponding to the register 108 (FIG. 7) is completed during the 8 time slots when the output becomes l#, and the AND circuit 154
When the output of "0#" falls, the AND circuit 161 becomes operable instead of the AND circuit 157. The peak value data of the touch detection signal loaded into the register 108 is thereafter held via this AND circuit 161. In this way, the initial touch detection data is held in the register 108.

Note that the data display of the register 108 is divided into two types: API and ITL.
The reason for this is that the same initial touch detection data is used for the M side of attack pitch control and initial touch level control. The API is attack pitch initial value setting data, and its weight is written above in each stage block of the register 108.

The lower three bits are truncated and the upper five bits correspond to a pitch shift of about 1.2 cents to about 19 cents. ITL
is initial touch level control data.

Among the data stored in each register 101 to 108 in FIG. 7, pitch control related data, vibrato rate data VBR, vibrato depth data vB
D1 Aftertouch vibrato depth data KVBD, daylay vibrato envelope rate data DVE
R, delay vibrato start time data D E L,
Slur rate low part data SRM, slur rate exponent part data SRE.

The attack pitch initial value setting data API is supplied to the effect applying circuit 20 (the part shown in FIG. 12). Data related to level control, that is, aftertouch level control data ATL, sustain rate data STR, and initial touch level control data ITL are provided by the musical tone signal generator 2.
1 (Figure 2).

Explanation of Effect Adding Circuit For convenience of illustration, a detailed example of the effect adding circuit 20 is divided into three parts and shown in FIGS. 12, 13, and 14. Combine as shown in the block. The effect applying circuit 20 performs processing to form modulation signals for attack pitch control, delay vibrato, aftertouch vibrato, and normal vibrato, respectively, and processing to modulate the pressed key code MKC in single note mode for slur effect. , execute.

Note that the slur effect is not directly related to this invention, and circuits related to the slur effect are mostly omitted in FIGS. 12 to 14. First, a portion that forms modulation signals for attack pitch and vibrato will be explained.

The effect imparting circuit 20 includes four arithmetic units CU shown in FIG.
L1. CUL2. CUL3. Contains CUL4. Each arithmetic unit CUL1 to CUL4 has 16 stages/l that are shift-controlled by system clock pulses φ□ and φ2.
Bit serial shift registers 162, 163, 164 .
165 and 1-bit full adder 166.167.16
8,169, and a logic circuit 17 for arithmetic and storage operation control.
0 to 196 (AND circuits) and 197 to 204 (OR circuits), respectively, and perform serial calculations.

Arithmetic unit CUL2 receives data VAL indicating the instantaneous value of the modulation signal.
It is something that counts! The arithmetic unit CUL1 repeatedly calculates data indicating the frequency of the modulated signal and generates a signal indicating the calculation timing in the arithmetic unit CUL2.

Arithmetic unit CUL3 calculates modulated ENV. This data ENV is shifted by a predetermined bit and used as a minute value ΔENV indicating the width of change in the modulation signal. Arithmetic unit CUL
In step 2, this change width ΔENVf: Data VAL indicating the instantaneous value of the modulation signal is obtained by repeatedly calculating according to the timing signal from the arithmetic unit CULI. The computing unit CUL4 is used for multiple purposes as described later.

FIG. 15(a) shows examples of modulation signals and their envelopes (depths) in attack pitch, delay vibrato, and normal vibrato. An outline of a method for forming a modulated signal will be explained with reference to this figure. Figure 15 (
In a), the horizontal axis shows time, and the vertical axis shows the pitch deviation from the normal frequency (0 cents) in cent values.

The initial value of the attack pitch is a negative value (pitch deviation on the bass side of the normal frequency) r-APiSJ. The absolute value r AP i S J of this attack pinch initial value is the attack pitch initial value corresponding to the tone given from the ROM 22 (Fig. 2) to the attack pitch initial value setting data API given from the register 108 (Fig. 7). It is multiplied by the number of cases APS.

As mentioned above, since the data API corresponds to the initial touch of the key, the initial attack pitch value APi3
will be controlled according to the initial touch. The initial value of the envelope at the attack pitch is also the same as the attack pitch initial value APiS. Arithmetic unit CUL3
(Fig. 13), APiS is preset as the initial value of the envelope instantaneous value ENV, and from now on, this initial value APiS
Minute value △AP with n bits added to the lower digits (2” times)
iS, attack pitch envelope plate data AP corresponding to the tone given from ROM22 (2nd-)
By repeatedly subtracting at time intervals corresponding to ER, the instantaneous value ENV of the gradually attenuating envelope is obtained. The above envelope plate data AP is calculated using the calculator CUL4.
ER is accumulated regularly, and the repetition time interval of the above-mentioned subtraction in the arithmetic unit CUL3 is determined by the generation timing of a carry signal from the most significant bit. Since ΔAPiS corresponds to the initial touch, the attack pitch envelope is also controlled according to the initial touch. On the other hand, the computing unit CUL
2, r-AP is used as the initial value of the modulation signal instantaneous value VAL.
Preset iSJ and set the envelope instantaneous value ENV to F.
Minute value △ENV shifted by n bits (2-n times)
The instantaneous value VAL of the modulation signal is obtained by repeatedly adding or subtracting , at time intervals corresponding to the attack pitch rate data APR corresponding to the timbre given from the ROM 22 (FIG. 2). The initial value of VAL is a negative value r-A
Since it is PiSJ, addition is performed at first and VAL is gradually increased. Switch to subtraction when value VAL reaches value ENV. Thereafter, addition and subtraction are performed again, so that the value VAL repeatedly turns around within the range of the envelope value ENV. The rate data APR is accumulated in the arithmetic unit CUL1 in a manner similar to that shown in FIG. Attack pitch control ends when the envelope value ENV becomes 0 cents.

When the attack pitch or slur ends, arithmetic unit C
The time until delay vibrato starts is counted at UL4. When this count time matches the delay vibrato start time DEL stored in register 104 (FIG. 7), delay vibrato starts.

The envelope (depth) in delay vibrato is 0
Starting from cents, give λ from register 102 (Figure 7).
The vibrato depth data VBD gradually increases to a cent value corresponding to the vibrato depth data VBD. The arithmetic unit CUL3 repeatedly adds the minute value ΔVBD obtained by shifting the depth data VBD by n bits to the lower digits at time intervals corresponding to the delay vibrato envelope data DVER given from the register 104 (FIG. 7). , find the gradually increasing envelope instantaneous value ENV. The value corresponding to the envelope plate data DYER is accelerated and rated in the arithmetic unit CUL4, and the calculation time interval in the arithmetic unit CUL3 is set by its carry signal. On the other hand, the arithmetic unit CUL2 modulates by repeatedly adding or subtracting a minute value △ENV obtained by 7 feet from the envelope instantaneous value ENV according to the vibrato rate data VBR given from the register 101 (Fig. 7) and at time intervals. Find the instantaneous value VAL of the signal. Above rate data VB
R is accumulated in the arithmetic unit CUL1, and the calculation time interval in the arithmetic units C and UL2 is set by its carry signal.

When the instantaneous envelope value ENV of the arithmetic unit CUL3 reaches the cent value corresponding to the depth data VBD, the delay vibrato ends and shifts to normal vibrato. In normal vibrato, the computing unit CUL3 holds a constant envelope value ENV corresponding to the depth data VBD, and the computing units CUL1. In CUL2, the same processing as in the case of the delay vibrato described in L is performed. Although not shown in Figure 15(a), in aftertouch vibrato,
The envelope value ENV of the arithmetic unit CUL3 is stored in register 10.
The value corresponds to the aftertouch vibrato depth data KVBD given from CUL1.3 (FIG. 7), and the calculation unit CUL1. Operate CUL2. Similarly, in this embodiment, when the player selects normal vibrato or aftertouch vibrato, delay vibrato is not applied. Furthermore, in this example, as shown in FIG. 15(a), the depth of the pitch shift during delay vibrato, normal vibrato, and aftertouch vibrato is asymmetric between the high-pitched and low-pitched tones. There is. In other words, the depth V on the treble side
The depth of the bass side is one compared to BD! -VBD. Such an asymmetric depth setting results in a favorable vibrato, close to that of a natural instrument.

In each of the arithmetic units CULI to CUL4 in FIG. 13, serial arithmetic is performed between the first to 16th time slots. The 16-bit data in each register 62-165 is output in order from the most significant bit between the first to 16th time slots. The serial operation results of each bit are sent to adders 166 to 1 between the 1st to 16th time slots.
69 and taken into each register 162-165. Thus, the data in registers 162-165 is cycled every 16 time slots. In order to prevent the carry signal from the most significant bit operation in the 16th time slot from being added to the least significant bit data present in the 17th time slot, an adder 166 is used.
~169 carry field output C6+1 is input C! AND circuits 170, 175, 183, 191 to give
A signal 17y32 is added to. This signal 17y3
2 is an inverted signal of the signal 17y32, which is "1" in the 17th time slot and 60H1 and other time slots.

In FIG. 13, the numbers written in each stage of each shift register 162 to 165 indicate the weight of data in each stage at the first time slot and the 17th time slot.

The unit of each weight display is set by the register 162 as “H, z,
”, 166 and 164 are “cents”, and the upper part of 165 is “
Hz”, and the lower side is rmsJ. The weight display above the register 162 indicates the weight when the arithmetic unit CULI is used to accumulate the attack pitch rate data APR. For example, "l" in the seventh stage indicates the IHz weight. The weight display on the lower side of the register 162 is the arithmetic unit CUL1.
This shows the market value when used for accumulating vibrato rate data VBH. For example, 7th stage r4/3
J indicates 4/3H,L. The reason why the weights are different for attack pitch and vibrato is that the aforementioned asymmetric depth setting is performed for vibrato. The weight display on the upper side of the register 165 indicates that the calculation unit CUL4 is the envelope plate data, APER, DVER (5L in ¥).
It shows the purity when used for accumulation of R). The weight display on the lower side shows the weight when using the calculator CUL4 to count the delay vibrato start time. register 1
Since the instantaneous value VAL of No. 66 can also be a negative value, a sign (pi) S exists to distinguish between positive and negative. Note that negative values are expressed as two's complement numbers. Next, details of each control will be explained.

(1) 7f' tip pitch control In order to control the operation of each arithmetic unit C'ULI to CUL4 in FIG. 13, delay flip-flops 222 to 2 are shown in FIG.
27 are provided. These flip-flops 22
2 to 227 take in the long sword signal at the timing of the signal IT8 (FIG. 5) and switch the output state at the timing of 17T24 (FIG. 5). Of these flip-flops, 222, 223, and 225 operate when the flip-flops are in the active control mode.

As described above, when the conditions for performing attack pinote control are met, the attack pitch start signal As is output from the single note key assigner 14A (FIG. 4) in response to the fall of the initial sensing signal Is. This attack pitch start signal AS is applied to AND circuit 211 in FIG. 14 and is inverted by inverter 214. The output of the inverter 214 is the AND circuit 205-2
Join 09°212. As shown in FIG. 16, the initial sensing MIS falls at the 16th time slot, and the attack pitch start signal As falls at the 16th time slot immediately after that.
It is 1' for 32 time slots from the 7th time slot to the 16th time slot. In response to the signal AS, the output of the AND circuit 211 becomes "1" and is applied to the OR circuits 1, 4, 6, and 7. The output of OR circuit 4 is given to flip-flop 225. After 32 time slots from the rise of signal As, flip-flop 2
The output of the AND circuit 210 rises to "1", and the output of the AND circuit 210 rises to "1".
and is self-maintained via the OR circuit 4.

The state of this flip-flop 225 is indicated by the symbol APQ. The output of the OR circuit 4 corresponds to the APQ signal. AP
When the Q signal is “L”, the effect imparting circuit 20 (12th to 1st
Each circuit in Figure 4) is instructed to execute attack pitch control.

The output of the OR circuit 1 is delayed by 32 time slots by a flip-flop 222 and output as a USET (upset) signal. The output of the OR circuit 7 is the inverter 228
The signal is inverted and used as a SET signal, and is delayed by 32 time slots in a delay flip-flop 223. The output of this flip-flop 223 is the inverter 2
It is inverted at 29 and used as a 5ETD signal. Further, the output of the AND circuit 211 is used as an APSET signal.

Therefore, the signals APQ, %USET, and SET are generated based on the attack pinch start signal As.

The states of 5ETD and APSET are as shown in FIG.

Further, FIG. 15(b) shows the states of each of the above-mentioned signals according to the time scale of FIG. 15(a).

The SET signal is the AND circuit 174.177~1 in Figure 13.
80, 182, 184 to 187, 190, and 196 to clear old data of each arithmetic unit CUIL1 to CUIL4. The USET signal is OR circuit 2 in Figure 13.
60 to delay flip-flop 231. This flip-flop 231 receives signals IT8, 17T2 similarly to the flip-flops '222 to 227 in FIG.
Controlled by 4.

The contents of this flip-flop 231 are the AND circuit 262
or self-retained via 236. Initially, the AND circuit 232 is enabled, and the "1" taken into the flip-flop 231 by the USET signal is held by the flip-flop 261. The signal UPQ held in this flip-flop 231 is sent to the arithmetic unit CU.
This indicates the addition/subtraction direction of L2, and UPQ is “1”.
'', it instructs up-counting (U), and when it is 0'', it instructs down-counting (CD).

The 5ETD signal is input to the output AND circuits 234 and 235 of the comparator C0M1 in FIG. 13 and the output AND circuits 236 and 237 of the comparator C0M2 in FIG. The state switching of each flip-flop 224 to 227 in FIG. 14 is a comparator COMI.

This is because the comparison output is prohibited when l'' has just been set in these flip-flops 224 to 227 since it is controlled by C0M2.

APQ signal u i 4 y-nd circuit 240.244 in Fig.
and AND circuits 171, 184, 185°1 in FIG.
86.194,217. In the case of active pitch, these AND circuits to which this APQ signal is input operate the arithmetic units CUL1 to CUL4 and the comparator C0M.
1. C0M2 is controlled.

The APSET signal is connected to the AND circuit 176°181 in Figure 13.
．． 188 makes people look bad. This (7) APSET signal is for loading the attack pitch initial value into the arithmetic units CUL'2 and CUL3. Similarly, all the outputs of the AND circuits 205 to 213 are input to the OR circuit 6 in FIG. 14, and it is always "1" while processing the attack pitch, delay vibrato, or slur.
Output. The output signal ANYQ of this OR circuit 6 is the first
It is input to the AND circuit 190 in Fig. 3, and the arithmetic unit CU
This enables calculation of time-varying data ENV in L3.

As described above, the register 108 in FIG. 7 loads the initial touch detection data between the 25th to 32nd time slots immediately after the fall of the initial sensing signal Is. The attack pitch initial value setting data API is taken out from the fifth stage of this register 108, and the twelfth stage
It is applied to AND circuit 248 in the figure. By enabling AND circuit 248 at the timing of signal 1T5y8, only 5 bits (see FIG. 7, 108) with weights of 1.2 cents to 19 cents are selected. This data API is delayed by two time slots using a two-stage delay flip-flop 249 and inputted into an AND circuit 250 , delayed by l time slots is inputted into an AND circuit 251 , and the undelayed data is inputted into an AND circuit 252 . input. ROM22
(The coefficient data APS given from Fig. 2 is 2 pits)
APS1°APS2, which are latched into the latch circuit 256 in synchronization with the 17th time slot. The 2-bit output of the latch circuit 256 is given to each AND circuit 250 to 252 in the form of decoding the value "11" 4 or "10" or O1, and data A in three states is given to each AND circuit 250-252.
Select one of the PIs. In this way, data APJ becomes coefficient data APS1. Shifted according to APS2,
Attack pitch initial value data A via OR circuit 254
PiS is obtained.

As shown in FIGS. 1 and 6, this data APiS has a valid value in seven time slots between the first to seventh time slots, for example, between the first to eighth time slots. As mentioned above, the coefficient data APS (APS□, A
PS2) corresponds to tone color. Therefore, by scaling the data API using the APS, the degree of attack pitch control can be controlled in accordance with the selected timbre. If a tone with no attack pitch is selected, APSl, APS
2 is “00” and the AND circuit 250.251.25
2 are all disabled, the initial value data APiS becomes all 102, and attack pitches are prohibited.

Initial value data APiS is applied to AND circuit 188 in FIG. 13, inverted by inverter 255, and input to AND circuits 181 and 185. AND circuit 18
8 passes through the data APiS at the timing of the signal 9T16 (FIG. 5) when the APSET signal is generated, and is output to the OR circuit 203.
and shift register 16 via input B of adder 168
Load into 4.

Therefore, register 164 in the 17th time slot
The weights of each stage are as shown in the figure.

The SET signal rises in place of the fall of the APSET signal, and the initial value APiS of the register 164 is held via the AND circuit 190. In this way, the attack pitch initial value AP is used as the envelope instantaneous value data ENV.
iS is preset in the arithmetic unit CUL,5 (register 164).

The AND circuit 181 outputs a signal 9T1 when the APSET signal is generated.
The inverted data ARiS is passed through at timing 6, and is applied to the input B of the adder 167 via the OR circuit 200. AP
When the SET signal is generated, l'' is output from the AND circuit 176 at the timing of the signal 9y32, and is applied to the input C1 of the adder 167 via the OR circuit 198.The signal 9y3
2 indicates the timing of the least significant bit of the inverted data APiS selected at the timing of the signal 9T16,
The adder 167 adds "l" to the inverted data APiS to calculate the two's complement of the initial value data AP i S. In this way, the negative initial value data r-Apts expressed in two's complement is preset in the arithmetic unit CUL2 (register 166) as the modulation signal instantaneous value VAL.

In the arithmetic unit CUL4, the attack pitch envelope plate data APER given in the ROM22 (Fig. 2) is
is input to the AND circuit 194.

This data APER is from the 17th time slot to the 1st time slot.
It is assumed that the data is given in real time in synchronization with one cycle of serial operation of six time slots.

While the APQ signal is being generated, this data APER is repeatedly applied to the input A of the adder 169 via the AND circuit 194 and the OR circuit 204. Furthermore, the output ERDT of the shift register 165, which is the output S of the adder 169 delayed by 16 time slots, is always output to the AND circuit 1 while the SET signal is being generated.
96 to input B of adder 169. Therefore, the data APER is repeatedly added by the arithmetic unit CUL4.

The modulo number of the 16-pit arithmetic unit CUL4 is 216, and a carry signal is generated from the most significant bit every time 2''/APER additions are performed.

Carry output C8+1 of adder 169 is input to latch circuit 256. The latch circuit 256 receives the signal 17y
It is latch controlled by 32s. Since the operation timing for the most significant bit is the 16th time slot, the carry-out signal for the most significant bit is output from the output C8+1 at the 17th time slot delayed by 1 time slot.

Therefore, the signal 17y3 generated in the 17th time slot
19, latch circuit 2 for latch control by 2s
At 56, the carry-out signal of the most significant bit of the arithmetic unit CUL4 is held for 32 time slots.

Similarly, the serial calculation timing of the calculation units CUL1 to CUL4 is as shown in FIG. 17(a). Each register 1
Numerical operations from the least significant bit (LSB) to the most significant bit (MSB) of the 16-bit data stored in bits 62 to 165 are sequentially performed in the first to 16th time slots. No calculation is performed in the next 17th to 32nd time slots, and the calculation results are held in circulation. Signal 9T1
The above-mentioned initial value “-APIS” selected at timing 6
”, rAPiSJ is shown in Figure 17 (b).
In the 16th time slot, each arithmetic unit CUL2. This means that it has been loaded into CUL3.

The carry signal expanded to 32 time slot width by the latch circuit 256 is sent to the AND circuit 18 of the arithmetic unit CUL3.
4,185.186 is input.

These AND circuits 184, 185, 186 are enabled by the APQ signal and the SET signal. The AND circuit 185 converts the inverted data APiS of the attack pitch initial value APiS provided from the inverter 255 into a signal IT8.
is selected at the timing of , and applied to the input A of the adder 168 via the child circuit 202 (see FIG. 17(e)). AND circuit 184 outputs OR circuit 2 at the timing of signal 1y32.
01 to the input Ci of the adder 168 (see FIG. 17(C)). As a result, the least significant bit (
1 is added to the timing of the first time slot), and A
Find the two's complement of PiS, i.e. -APiS (17th
(See figure (C)). The AND circuit 186 applies "1" to the input A of the adder 168 via the OR circuit 202 at the timing of the signal 9T16 (FIG. 17(C)). As a result, all "l" are added in the 9th to 16th time slots to r-APiSJ in the 1st to 8th time slots, and APiS is shifted 8 bits lower (multiplied by 2-8) to a small value. The two's complement of △APiS "-△APiSJ" is found.

The above minute value [-△APiSJ is added to the data ENV of the shift register 164 circulating through the AND circuit 190, the OR circuit 203, and the input B of the adder 168.
(ΔAPiS is subtracted).

This addition is performed once every time a carry signal is generated from the most significant bit of the arithmetic unit CUL4. Initially, the attack pitch initial value APiS is preset as the data ENV.

Therefore, the current value of the data ENV is obtained by subtracting ΔAPjS from APiS to the I+@th order each time the carry signal of the arithmetic unit CUL4 is generated. △APiS 1
The time interval for subtraction is determined according to the data APERQ value accumulated by the arithmetic unit CUL4. As mentioned above,
Since the carry signal is latched into the launch circuit 256 every time the calculation unit CUL4 performs 216/APER additions, the time interval for subtracting ΔAPiS once by the calculation unit CULF is r 16tls x 216/APERJ.
It is. For example, if the data APERO value is expressed in Hz,
A carry signal is generated from the arithmetic unit CUL4 in CUL4, and the calculation period of ΔAPiS is [16μs×64(H
z)/APER(H, 1,)]. In the above manner, the envelope data BNV, which gradually decreases -f, as shown in the attack pitch portion of FIG. 15(a), is determined by the computing unit CUL3.

On the other hand, the AND circuit 171 of the arithmetic unit CULI has ROM2
2 Attack pitch rate data APR from (Figure 2)
is given, and while the APQ signal is being generated, this data A
PR is always applied to adder 1660 input A. Similar to the data APER described above, this data APR also has the 17th
It is given serially in synchronization with one cycle of serial operation of the 16th to 16th time slots. Also, SE
While the T signal is being generated, the output of the shift register 162, which is the output S of the adder 166 delayed by 16 time slots, is always applied to the input B of the adder 166 via the AND circuit 174. Therefore, the data APR is 16μ in the arithmetic unit CULI.
It is accumulated every 5 (32 time slots). The most significant bit carry signal generated by this accumulation is latched by the latch circuit 257 at the timing of the signal 17y32S, and is expanded to a width of 32 time slots. The time interval at which the carry signal is generated from the most significant bit of the arithmetic unit CUL1 is "16" as described above.
psX2”/APRJ. If APR is replaced with Hz display, the modulo number of 2160 Hz display becomes 128 (=2
x1〒'')Hz [16μs×128(Hz)/
It can be expressed as APR (Hz) J.

The output of latch circuit 257 is given to AND circuits 177-180 of arithmetic unit CUL2. These AND circuits 17
7-180 are enabled by the SET signal. AND circuits 177 to 179 are for down counting (subtraction), and are supplied with a signal obtained by inverting the UPQ signal by an inverter 258. The AND circuit 180 is for up-counting,
A UPQ signal is provided. As mentioned above, initially USET
The UPQ signal is set to 'l' by the signal,
AND circuit 180 is now operational.

The AND circuit 180 is supplied with the ninth stage output ΔENV of the shift register 164, which is used as the signal 1'
It is selected at timing I'8 and applied to input A of adder 167 via OR circuit 199.

``At the first time slot, the weights of each stage of the register 164 are as shown in the figure, so the signal IT
By selecting the output ΔENV of the 9th stage of the register 164 between the 1st and 8th time slots using 8, the weight data from the 8th bit to the 15th bit of data ENV is shifted to the lower 7 bits. You can choose something. That is, the data ΔEN selected by the AND circuit 180 between the first to eighth time slots
V is a minute value obtained by shifting the envelope data ENV of the arithmetic unit CUL3 to the lower part by 7 bits (multiplying it by 2-7).

This shift state is illustrated in FIG. 17(d). That is, in the arithmetic unit CUL3, the upper 8 bits of the data ENV having weights that are serially calculated at the timings of the 8th to 15th time slots are 7. By taking out the time slot early, the calculation timing of the first to eighth time slots, which are 7 bits lower, is shifted by 7, resulting in minute value data ΔENV.

The data VAL of the arithmetic unit CUL2 is supplied to the AND circuit 182,
It circulates through the OR circuit 200, the input B of the adder 167, and the shift register 166, and ENV is added to the above-mentioned minute value with respect to this data VAL. This addition is performed once every time a carry signal is generated from the most significant bit of the arithmetic unit CUL1. Initially, the data VAL is a negative attack pitch initial value "-Ap".
i3" is preset. Therefore, this “-AP
ΔENV is sequentially added to ``iS'', and as shown in FIG. 15 (I
As shown in the attack pitch portion of L), the value of data VAL gradually increases. The time interval for repeatedly calculating △ENV is the generation interval of the carry signal of the calculation unit CUL1 [16μs×2”/APRj, and the rate data AP
Determined by R.

Data VAL is applied to input A of comparator C0M1 via AND circuit 215 at the timing of signal IT16.

When the arithmetic unit CUL2 is up-counting, the AND circuit 216 is enabled by 1' of the UPQ signal. The AND circuit 216 selects the envelope data ENV at the timing of the signal lT16, and the OR circuit 221
is applied to the input B of the comparator C0M1. A, I can smell one/t condition, VAL7! l'-ENV)], that is, when the modulation signal instantaneous value VAL is rising toward the rope instantaneous value ENV, the ratio Y.

In the device COMI, rA<BJ holds, and the AND circuit 265
An output 11'' is given to the AND circuit 264, and an output '' is given to the AND circuit 264.
``0'' is given. Note that the 5ETD signal given to the other inputs of the AND circuits 234 and 235 is normally "L". The output ``0'' of the AND circuit 264 is
9, and l'' is applied to the AND circuit 262.

In the up-counting state, the output of the delay flip-flop 231 is l", and this output "1" is sent to the AND circuit 23.
2. Flip 70 knob 261° via OR circuit 230
is being held. When VAL reaches ENV and FA>BJ is established in comparator C0M1, AND circuit 23
1" is output from 4, and the output of inno(-ta 259"'
0'' disables the AND circuit 232. This resets the flip 70 knob 931, and the UPQ
The signal becomes @0'', and the arithmetic unit CUL2 enters the down-count mode.
The output state of C0M2) in the figure is changed in synchronization with the signal 17y32.

In the down count mode, the output of the inverter 258 which inverts the UPQ signal is "l", and the AND circuit 1
77.178. i79 becomes operational. These NAND circuits 177, 178, 179 function to convert the addend ΔENV used by the arithmetic unit CUL2 into a two's complement number.

The data △ENV is inverted by the inverter 260 (△
ENV) is applied to the AND circuit 179, and is applied to the input A of the adder 167 at the timing of the signal IT8. As described above, the signal IT8 contributes to obtaining the minute value ΔENV, which is obtained by shifting the data ENV by 7 bits.

The AND circuit 177 supplies the input CiK''1'' to the adder 167 at the timing of the signal 1y32, and outputs the inverted data △EN.
This is for adding 1 to the least significant bit of V. The AND circuit 178 is for providing 1'' for 8 time slots to the input A of the adder 1670 at the timing of the signal 9T16''.

In this way, the two's complement [-△ENVJ] of the minute value △ENV is obtained in the 1st to 16th time slots.
(See Figure 7(e)).

In the down-count mode, every time the carry signal of the most significant bit of the arithmetic unit CULI is generated, the arithmetic unit CUL2 adds [-ΔENVJ to the data VAL, thereby effectively subtracting ΔENV from VAL. Therefore, as shown in FIG. 15(a), the data V
After AL reaches the peak corresponding to the envelope data ENV, it gradually falls at the same rate as when it rose.

In the down count mode, the AND circuit 216 becomes inoperable and the AND circuits 217, 218 and 219 become operable. In the case of attack pitch, AND circuit 217
, 218, 219, only 217 are enabled by the APQ signal.

The envelope data ENV output from the register 164 of the arithmetic unit CUL3 passes through the AND circuit 217 at the timing of the signal 1'l'16, and is applied to the 10's complement circuit 261 via the OR circuit 220. When the modulation signal instantaneous value VAL is falling, this VAL folds back in the negative region, so this complement circuit 261 is provided to convert the envelope data ENV into a negative value. Complement circuit 261
is the envelope data FJNV sent at the timing of the signal IT16 (1st to 16th time slot).
The two's complement of is determined and applied to the input B of the comparator C0M1 via the OR circuit 221. While data VAL is falling, rVAL>-ENVJ, so comparator C0M1 [
A<BJ is not established, and the down count mode is maintained. Data VAL is a negative value of data ENV (-ENV)
When reaching , rA<BJ is established in the comparator C0M1, and l" is given to the AND circuit 265. The output "1" of this AND circuit 265 is given to the AND circuit 266. In the down count mode, the delay The AND circuit 263 is enabled by the output "I" of the inverter 262 which is the inversion of the output "0" of the flip-flop 261. Therefore, when rA<BJ is established in the comparator C0M1, the AND circuit 266 outputs "1". and loaded into the flip-flop 231. Also, “A” of comparator C0M1
〉B'' output becomes 0'', and 1'' is given from the inverter 259 to the AND circuit 262. Therefore, the output "1" of the flip-flop 231 is self-held via the AND circuit 262. In this way, the UPQ signal becomes '1',
The arithmetic unit CUL2 is switched to annopcauto mode.

As described above, the data VAL repeatedly rises and falls within the envelope range indicated by the data W, and a modulation signal (VAL) that gradually attenuates as shown in the attack pitch part of FIG. 15 (al) is obtained. It will be done.

On the other hand, the computing unit CUL! Envelope data ENV of 1 is supplied to AND circuits 268 and 240 in FIG.

240 and 24 of the AND circuits for control of comparator C0M2
The APQ signal is applied to 1, and the data ENV is applied to input A via an AND circuit 240 and an OR circuit 246. A timing signal 8y32 is applied to the other input of the AND circuit 244, and 1'' is applied to the input B of the comparator C0M2 every eighth time slot.

As is clear from the register 1640 weight display shown in FIG. 13, the weight of the eighth time slot in the envelope data ENV is 0.6 cents.

Therefore, inputting lII corresponding to the eighth time slot means inputting data indicating 0.6 cents to input B of comparator C0M2.

Therefore, the comparator C0M2 compares the data EN'l input A) indicating the current cent value of the envelope with 0.6 cents (input B, ). Note that since the weight of the least significant bit of the data APiS initially loaded into the register 164 (FIG. 13) is 1.2 cents, 0.6 cents effectively means 0 cents in this circuit.

When data ENV has not yet reached 0.6 cents, rA>Bj holds true in comparator C0M2, and "A≦B".
The output of is 'O'. This output 'o' is the AND circuit 2
67 to the inverter 266, and the inverter 26
The AND circuit 210 is enabled by the output "l" of 6, and the APQ signal is held.

Data ENV is less than or equal to 0.6 cents (i.e. 0 cents)
Then, "A≦B" is established in the comparator C0M2, and the output of the AND circuit 237 becomes l''.

This means that the depth setting mechanism/velope for the attack pitch has become 0 cents, ie, the attack pitch has ended. Output of AND circuit 267''
``l'' causes the output of the inverter 266 to become 0'', and the AND circuit 210 becomes inoperable. Therefore, the APQ signal becomes 0" and attack pitch control ends. Since the data ENV is the value △APiS obtained by shifting the initial value APiS by 8 bits to the lower side from this initial value APiS, it is calculated 28 times. When subtracted, it becomes exactly 0.

(2) The output of the delay vibrato AND circuit 267 is also given to the AND circuit 208. The AND circuit 208 is enabled during attack pitch control by the output (APQ) of the flip-flop 225, and when the attack pitch ends, the AND circuit 208
When the output of 7 becomes 61'', the condition is met and 1 is output.The output ``lII'' of this AND circuit 208 is input to the OR circuit 6.6.7. Output of OR circuit 6 ``1''
lI+ is loaded into flip-flop 226 by . 1" of this flip-flop 226 is an AND circuit 2
07, held via the OR circuit 3. The state of this flip-flop 226 is indicated by the symbol DELQ. The output of OR circuit B is the DELQ signal. When the DELQ signal is 1'', the delay vibrato start time is counted.

This DELQ signal is shown in FIG. 15(b) on a time scale corresponding to FIG. 15(a).

Since the output of the AND circuit 208 is given to the OR circuit 7, similar to the rise of the APQ signal described above (the first
6), the SET signal becomes "0" in the 32nd time slot at the rise of the DELQ signal, and the 5ETD signal becomes "0" in the next 32 time slots.

Note that the outputs of the aftertouch vibrato selection switch KVBS and the normal vibrato selection switch NVBS are latched into the launch circuit 265 via the OR circuit 264.
The output is inverted by an inverter 266 and +N is applied to AND circuits 205 to 209 for delay vibrato. Therefore, when aftertouch vibrato or normal vibrato is selected, the signal X becomes "θ", all AND circuits 205 to 209 are disabled, and delay vibrato is prohibited.

Further, although not explained in detail, when the slur control is completed, the condition of the AND circuit 209 is satisfied, and the DELQ signal is set in exactly the same way as when the condition of the AND circuit 208 is satisfied. That is, the DELQ signal is set at the end of the attack pitch and at the end of the slur.

The DELQ signal is input to the AND circuit 196 of the arithmetic unit CUL4 in FIG. The old data in the register 165 of CUL4 is cleared in advance by the SET signal 0''.While the DELQ signal is being generated, the arithmetic unit CUL4 functions as a timer.

That is, the weight of each stage of the register 165 is 512! as shown below. It corresponds to times such as ms, 256m5, etc. The other input of the AND circuit 196 is the signal 1y3.
2 is given, and based on this signal 1y32, the first
1 is added repeatedly (every 16 μS) in the time slot. Therefore, the first time slot or the 17th
In the time slot, the weight of the data output from the 16th stage of the register 165 is 16 μs, and the weight of the data coming to the 10th stage is about 1 m5 (more specifically, 1024 μs). In this way, in response to the passage of time from the rising edge of the DELQ signal, the arithmetic unit CUL4
The content of ERDT increases sequentially. The count data ERDT of this arithmetic unit CUL4 is calculated by the AND circuit 269 in FIG.
is input. The AND circuit 269 selects the data ERDT at the timing of the signal 1T16 while the DELQ signal is being generated, and supplies it to the comparator C0M2O input A.

On the other hand, the delay vibrato start time data DEL taken out from the eighth stage of the register 104 in FIG.
AND circuit 2 in Figure 14 via Figures 12 and 13
43. The AND circuit 246 selects the data DEL at the timing of the signal 9T16 while the DELQ signal is being generated, and supplies it to the input B of the comparator C0M2. 8-bit data DEI.

are selected at the 9th to 16th time slots of higher weight among the calculation timings of the 16 time slots, these data DEL are stored in the register 104 in FIG.
It will have a large weight as shown in . Data E
If the value of RDT is smaller than the data DEL, rA<Bj holds true in comparator C0M2, and the output of "A2B" is "
0'', and from the AND circuit 266
'0'' is applied to the inverter 267, and the output 61'' of the inverter 267 is applied to the AND circuit 207. Therefore, the DELQ signal of flip-flop 226 is held via AND circuit 207.

When the start time set by data DEL arrives, ERDT≧DEL and comparator c.

"A2B" of M2 is established, and the AND circuit 266 '1
The output of the inverter 267 becomes 0, the AND circuit 207 becomes inoperable, and the DELQ signal falls. In this way, the waiting time until the start of delay vibrato ends.

The output of AND circuit 266 is given to AND circuit 206. The AND circuit 206 is enabled during the above-mentioned time waiting by the output (DELQ) of the flip-flop 226, and outputs 1 in response to the output "1" of the AND circuit 266 at the end of the above-mentioned time waiting. circuit 20
The output of 6 is input to OR circuits 1.2 and 6.7. 1" to the flip-flop 227 based on the output of the OR circuit 2.
is loaded. “1” of this flip-flop 227
is held via the AND circuit 205 and the OR circuit 2. The state of this flip-flop 227 is indicated by the symbol DVBQ. The output of the OR circuit 2 is the DVBQ signal.

When the DVBQ signal is 1", a modulation signal for delay vibrato is formed. This DVBQ signal is shown in FIG. 15 (bl) on a time scale corresponding to FIG. 15(a).

Since the output of the AND circuit 206 is applied to the OR circuits 1 and 7, the SET signal becomes 0'' in the 32nd time slot of the rise of the DVBQ signal, similar to the rise of the APQ signal described above (see FIG. 16). and the next 3
5ETD signal becomes 0'' in 2 time slots,
And the USET signal becomes '1'. '1' of the USET signal
'', the 7 lip-flop 231 (UPQ
signal) is set to 1''. Therefore, the arithmetic unit CUL2
is initially set to up-count mode. Also, S
Each arithmetic unit CUL1 to C in FIG. 13 is activated by the ET signal "0".
U'L4 is cleared.

The procedure for forming modulation signal data VAL in delay vibrato is performed in substantially the same manner as in the case of attack pitch. The data used for the calculation is different from that for the attack pitch.

An arithmetic unit CUL4 that sets a calculation time interval for envelope data (ENV) calculation accumulates delayed vibrato envelope plate data DvER' given to an AND circuit 192. This data DVE
R' is formed by the circuit shown in FIG. 12 based on the data DVER output from the first stage of the register 104 shown in FIG.

In FIG. 12, data DVER is inverter 268
The signal is inverted at , and input to a launch circuit 269 and an AND circuit 270 . Output of AND circuit 270 and signal 9y32
are synthesized by the OR circuit 271 and the data DVER'
is obtained. These circuits 268 to 271 are connected to data D
This is to create data DVER' with characteristics opposite to VER.

In this embodiment, the delay vibrato start time (
DEL) and delay vibrato envelope plate (D
VER). Therefore,
If the setting value of volume v4 is used as is, the start time (DEL) will be long (indeed, the slope of the envelope will become steeper, and the delay 1 vibrato clock will become shorter. This is contrary to natural delay vibrato. Therefore, Delay vibrato start time data DEL is volume V4
The settings of the envelope plate data DVER' are used as they are, but the envelope plate data DVER' is converted from the settings of volume v4 (DVER) with inverse characteristics, and the start time (DEL) is long (I see, the slope of the envelope is made gentler and the delay vibrato is The period will be long.

Data DVER is retrieved from the first stage of register 04 in FIG.
The weight of this data DVER in the time slot is as shown in FIG. That is, the most significant bit (weight of 1/IHz) is cleared in the first time slot, and the second to eighth timeslots (-) are cleared. This corresponds to the weight display in FIG. 18 &± the weight display below the register 04 in FIG. In FIG. 12, the latch circuit 269 is launch-controlled by the so-called 1y32s,
The inverted signal of the data generated in the first time slot is latched. The output of this latch circuit 269 is AND circuit 2
given to 70. AND circuit 270 is latch circuit 2
When 1” is latched in 69, that is, data DVE
Enabled when RΩ most significant bit is 60”, signal 2T
Inverted data DYER of data DVER at timing 8
Among them, data from the least significant bit (weight of 115□2 Hz) to the seventh bit (weight of 1/8 Hz) is selected (see FIG. 18). The data selected by the AND circuit 270 is output via the OR circuit 271. OR circuit 27
1, next to the data selected by the AND circuit 270 (
1" is added based on the signal 9y32 in the 9th time slot (see Figure 18). In this way, the data arranged in order from the least significant bit to the most significant bit between the 2nd to 9th time slots is DVER' is obtained.

When 0'' is latched in the latch circuit 269, that is, when the most significant binotocap of data DVER is 1'', the AND circuit 270 becomes inoperable, and the data DVER' in the second to eighth time slots are all ``'θ''. becomes. In this case, since 1" is only given at the timing of signal 9y32, data DVER' is always 10000000" no matter what value data DVFJR is.
(See Figure 18).

Data DV corresponding to changes in data DVER (DEL)
The status of ER and DVER' is shown in the table below for the upper 3 bits.

Table 2 As is clear from the table above, when the most significant bit of data DVER is 60'', data DVER' exhibits the inverse characteristics of DYER, but when the most significant bit is ``l'' (in other words, ) data D V E R' holds a constant value (minimum value).
The value of V ER' is illustrated.

When 0VER' is all I+, ++, the delay vibrato envelope plate is approximately 17zH2,
1/4 when DVER' is 10000000"
i(z. In other words, the envelope plate of the delay vibrato is controllable (settable) in the range of about '/2 Hz to 1 /4 H7. The delay vibrato period with the envelope plate of about '/2 Hz is about 0.
5 seconds, and the delay vibrato period with the '74Hz envelope plate is 1 second.

Through the above control, the relationship between the set values of volume IJ, -v4, delay vibrato start time data DEL and delay vibrato envelope plate data DYER',
The relationship between the setting value of the volume V4 and the actual start time based on the data DEL and the actual delay vibrato period based on the data DV and ER' is as shown in FIG. The horizontal axis shows the set value of the volume v4, the left vertical axis force-data DEL, the value of DVER', and the right vertical axis shows the time length. "DEL" curve is volume v4
The curve of "DEL time" shows the relationship between the set value of V4 and the value of data DE.
Based on L (represents the relationship between actual start times, both curves have the same characteristics. Curve of "DvERI".

shows the relationship between the setting value of the volume V4 and the value of the data DVER', and the curve Gi of "DVER'time" shows the relationship between the setting value of the volume v4 and the actual delay vibrato period based on the data DV'FJR'.

Vibrato depth data VBD &! , is added to the AND circuit 272 in FIG. 12, is selected by the AND circuit 272 at the timing of the signal lT6 y8 (see FIG. 5), and is added to the AND circuit 187 in FIG. 13 via a line 276. AND circuit 272)-! , 6 of the weight from 1, 2 cents) to 38 cents, which is the valid value of this data VBD.
Bit data (see register 102 in Figure 7 □)
This is to select only 2 bits and block unnecessary 2 bits. The AND circuit 187 in FIG. 13 is enabled by the DVBQ signal and the SET signal, and the arithmetic unit CUL4
When the carry-out signal is latched by the launch circuit 256, the data VI31) is selected at the timing of the signal IT8 and is applied to the A input of the adder 168. data VBD
are selected in the first to eighth time slots, which are the lower calculation timings, and used for calculation, so the calculation unit C
In UL3, a small value ΔVBD corresponding to the weight of the lower 6 bits is actually added. In other words, the weight display (1, 2) of the data VBD in the register 102 in FIG.
As a small value △VBD shifted 8 bits lower (multiplied by 2-8) compared to
Used in UL3. This data △VBD is the arithmetic unit CU
Every time a carry signal is generated from the most significant bit of L4, the arithmetic unit CUL'! It is added repeatedly with .

As mentioned above, the adder 169 of the arithmetic unit CUL4 receives the data DVER' inputs 1, 2nd through 9th through the AND circuit 192.
(1 is given in the time slot.

For the calculation unit cUL, 4, it is 1/41 (zka et al. 11
8-pit data D corresponding to weights up to 512H2
Acquire VER' every 32 time slots (16 μs). Incidentally, the most significant bit of this arithmetic unit CUL4 has a weight of 32H2, as is clear from the upper weight display power of the register 165. This computing unit CUL4
Based on the carry signal, the arithmetic unit CUL3 accumulates the data ΔVBD at a period corresponding to the data DVER', ie, DVER. Thus, the 15th
The envelope data ENV gradually increases, as shown in the delay differential part of the figure (ILI).

The vibrato rate data VBR1' which is also derived from the fourth stationary register 101 in FIG. 7! , is applied to AND circuit 274 in FIG. The add/do circuit 274 selects data VBR between the 5th and 12th time slots based on the signal 5T12 (see FIG. 5), and selects the data VBR on the line 27.
5 to the AND circuit 172 in FIG. 7th
The weight display in the picture frame 101 is for the first time slot, and at the fifth time slot, the lowest r-gHzJ weight data is output from the fourth stage.

Therefore, line 275 is provided with 8-bit data VBR arranged in order from the least significant bit in the fifth to twelfth time slots.

The AND circuit 172 is enabled during delay vibrato by the DVBQ signal, and the f-VBR is enabled by the DVBQ signal.
2, is applied to input A of the Calo calculator 166 via the OR circuit 197. Adder 166 at the fifth time slot
The weight r-Hzj given to the shift register 162 from
(The 17th (and 4th) time slot contains the 4th bit of the register 162.)
Shifted up to 2 stages. Therefore, when the vibrato rate data VBR is accumulated, the weight of the data in the shift register 162 becomes as shown below in each stage block. In the arithmetic unit CULI, data VB
R is accumulated every 32 time slots (16 μs), and the carry signal of the most significant focus is latched into the latch circuit 257. If the data VBR is expressed in Hz, the carry-out 51 starts from the most significant bit of the arithmetic unit CUL1.
2 1 - The period at which the gt signal is generated is "16μBX abe Hz"V
It can be expressed as BR<1 nail. Sanki (=216x a s a
) Hz is H corresponding to the modulo number 216 of CULl
2 display.

When 1" is latched in the latch circuit 257, the AND circuits 177 to 180 are enabled as in the case of attack pitch. In the up count mode, the AND circuit 18 is enabled.
The data ΔENV is selected via 0, and the data ΔENV is added to the content VAL of the arithmetic unit CUL2. In the case of delay vibrato, the up count mode is initially set and the content (VAL) of the arithmetic unit CUL2 is set, so the data VAL increases from θ cents in the positive direction. The width of one change in this data VAL is data △ENV obtained by shifting the envelope data ENV by 7 bits, and the time interval of the change is data △ENV.
The cycle of repeatedly adding NV by the arithmetic unit CUL2 corresponds to the vibrato rate data VBR.

The control for switching the arithmetic unit CUL2 to up-count mode or down-count mode while data VAL is rising is as follows:
This is done in the same way as for the attack pitch. That is,
Data vAL and ENV are input to inputs A and B of comparator C0M1 through AND circuits 215 and 216, respectively, and
When "A>B" is established, that is, when VAL reaches ENV, the UPQ signal of the flip-flop 261 is reset.

When the UPQ signal becomes θ'', the AND circuits 177, 178, 179 of the arithmetic unit CUL2 become enabled, and as in the case of attack pitch, every time the carry signal of the arithmetic unit CUL1 is latched by the latch circuit '257, the signal becomes '△ ENV
Subtract J (add the two's complement of ΔENV). Along with this, the data value VAL gradually decreases. The change width and time interval of data VAL during falling are determined by ΔENV and VBR, as in the rising.

In the delayed vibrato count mode, the AND circuit 218 is enabled by the DVBQ signal and the output of the inverter 258. This AND circuit 218 is connected to the output TEN of the 15th stage of the shift register 64.
V is given, and 1 of the data HENV is selected at the timing of the signal lT16. This data TENV is the negative value of the envelope data NNV output from the 16th stage of the register 64 at the same timing of the signal IT16 (first to 16th time slots). In this way, the envelope data (i.e. vibrato depth) on the low frequency side (negative cent value) is converted to the data ENV of 1 on the high frequency side! −
ENV is used2. As a result, as shown in the delay vibrato portion of FIG. 15(a), the vibrato depth on the high frequency side and the vibrato depth on the low frequency side can be made asymmetrical (2 vs. l).

, 1 The 1-TENV selected by the AND circuit 218 is converted into a 2's complement number by the complement circuit 261, and becomes a negative value. The comparator C0M1 compares the falling data VAL (A input) with the data r-HENVj (B input), and when rA<Bl is established, the state UPQ of the flip-flop 231 is switched to the up-count mode.

As described above, the data VAI repeats rising and falling within the envelope range indicated by the data ENV and [--ENVJ, and the depth gradually increases as shown in the delay vibrato part of FIG. 15(a). modulation signal (V
AL) is obtained.

On the other hand, the input A of the comparator C0M2 in FIG.
Envelope data ENV is provided at the timing of signal IT16 via an AND circuit 268 enabled by the signal. Further, the vibrato depth data VBD on line 276 (FIGS. 12 and 13) is applied to input B at the timing of signal 9T16 via AND circuit 242 enabled by the DVBQ signal. In this case, the comparator C0M2 compares the data ENV and VBD with the same weight. As mentioned above, data ENV is °data VBD
Since ENV is obtained by repeatedly adding the value △VBD obtained by shifting 8 pins lower, ENV matches VBD when .

When data ENV has not yet reached the value of data VBD, rA<BJ holds true in comparator C0M2, and “A2
The output of "B" is 0". This output "0" is given from the AND circuit 266 to the inverter 267, and the inverter 2
The AND circuit 20Er is enabled by the output "1" of the output signal 67, and the DVBQ signal is held.

When the data ENV matches the value of the data VBD, "A2B" of the comparator C0M2 is established, and the output of the AND circuit 266 becomes 'l'. As a result, the output of the inverter 267 becomes 0", and the DVBQ signal is reset. Ru. In this way, the delay vibrato ends.

After delay vibrato ends, it automatically shifts to normal vibrato.

(3) Normal vibrato There are two ways to round the normal vibrato. One is to automatically shift after the delay vibrato ends, and the other is to actively switch to normal vibrato by using the switch NVBS (Fig. m14). This is a case where only normal vibrato is performed without delay vibrato.

Normal vibrato and aftertouch vibrato, which will be described later, are long strokes when the output signal ANYQ of the OR circuit I@6 inputting all the outputs of the AND circuits 205 to 216 in FIG. 14 is @0#. This ANYQ signal is applied to the AND circuit 190 in FIG. 13 and is inverted by the inverter 276.
A] AND circuits 175, 189, 21 as NYQ signals
9 is input.

In Figure 14, 1, delay vibrato end 1 temple (・
As mentioned above, 1" is output from the AND circuit 266', but this output acts only to take and divide the DVBQff1 signal. Therefore, when the υVBQ signal falls to "0", the 1" is output. The ANYQ double number becomes “o” and the first
As shown in FIG. 5(b), the ANYQ signal rises. Therefore, after the delay vibrato ends, it automatically shifts to normal vibrato. Switch NVBS (or KVBS)
When normal vibrato (or aftertouch vibrato) is actively selected, the AND circuits 205 to 209 of the delay vibrato opening are always disabled by '0' of the K0N multiplier. ,
When the attack pitch (or slur) ends, the AND circuit 208 (or 209) does not operate, and the ANYQ signal rises at the same time as the APQ signal (or the 5LQW signal to be described later) falls. Therefore, in that case, the attack pitch (slur)
Immediately transition to normal vibrato after finishing. Always ANY if there is no attack pitch or slur
The Q signal is @0", the ANYIW signal is "1", and normal vibrato is performed from the beginning.

Normal vibrato (and aftertouch vibrato)
are the arithmetic units CUL1 and CUL2 in FIG.

Processed using CUL3. Since the SET signal does not become 10' when the ANYQ signal rises, the arithmetic unit CUL
1 and CUL2 are not cleared, and the modulation signal instantaneous value data VALr and the previous values are erased. Also, USETS
Since no ET signal is received, the state U P Q i of the 7 lip-flop 261 remains unchanged until then. Therefore,
When changing from delay vibrato to normal vibrato, the modulated mouth blemish from delay vibrato smoothly transitions to normal vibrato.

In the arithmetic unit CULI, AND, P! is enabled behind the ANYQ signal. Vibrato rate data VBR on line 275 is received by adder 166 via circuit 176, and as in the case of delayed vibrato, the data VBR'!
Accumulates every 1-32 time slots (16 μs), and at 2, the AND circuits 177-180 are enabled by the SET signal, and just like the delay vibrato, the arithmetic unit CUL1 The carry signal is generated from the most significant bit of
Data l-s E given by arithmetic unit CU i, 6
"ISJ V is added or subtracted in 0 arithmetic unit CUL3, 'o' t= of ANYQ signal
Therefore, the AND circuit 190 is rendered inoperable, and the register 16
Circulation of data ENV 4 is prohibited. On the other hand, ANYQ
The constant vibrato depth data provided by the OR circuit 277 is selected via the AND circuit 189 enabled behind the signal, and this data is passed through the JJ146168k and constantly input into the register 164. The output of the aftertouch vibrato selection switch ICV HS shown in FIG. join. When aftertouch vibrato is not selected, that is, when it is normal vibrato, the signal KVB
SS is always "0", the AND circuit 278 has an operation rate i, and 279 is possible. The AND circuit 279 is
Vibrato depth data vBD on line 276 to signal 9T
It is selected at the timing of 16y16 (reference 51) and is applied to the AND circuit 189 via the OR circuit 277.

The AND circuit 272 in FIG. 12 uses the valid bits (6 bits from the 1, 27-cent weight to the 38-cent weight) of the vibrato depth data VBI from the register 102 (FIG. 7).
bit) from the 1st to the 6th and 9th to 14th and the culvert 17
Gravels are selected in the valley sections of the 22nd, 25th, and 30th time slots and are applied to line 276. The AND circuit 279 in FIG. 13 uses the data VBv on this line 276.
The selection is made in the trough sections of the k'-49 to 16th and 25th to all'g32 time slots (that is, the time slots of the upper 8 bits of the calculation timing of the 16 time slot 1 synchronization shown in FIG. 17(a)). Therefore, the data VBυ of the register 102 in FIG. 7 is transferred to the shift register 16 in the operator C[J'
4 is loaded repeatedly. As a result, the envelope data ENV of the arithmetic unit CUL3 is in the same state as maintaining the constant depth data Vd1). Therefore, the data △12Nv given to the arithmetic unit CUT, 6 and CUL2 is the data △VBD obtained by shifting the depth data VBD to 7 pits (multiplying it by 2-7).
It is.

As mentioned above, in normal vibrato, the envelope data ENV is always a constant VBD, so the amount of change ΔENV per 1# calculation time interval of data VAL is Δ
VBD, and a modulation signal (VAL) of a constant depth is obtained as shown in the normal vibrato portion of FIG. 15(a). Note that the envelope data on the low frequency side is data TENV, that is, TVBD, as in - and 11 for delay vibrato, and the depths on the high frequency side and the low frequency side are asymmetric. That is, ANY
The AND circuit 219 is enabled by the QI signal, and the output of the 15th stage of the register 64 -! -ENV is selected in the down count mode, during the period of the signal IT16, and is applied to the comparator C0M1 via the complement circuit 261t. Therefore, when data VAL is rising, VAL
When VBD reaches the depth data (that is, ENV), it turns downward (to down count mode) and VAL
While falling, when VAL reaches 1-zWNV, it turns back upward (to up-count mode).

(4) Aftertouch Vibrato Aftertouch vibrato is processed in much the same way as the above-mentioned normal vibrato. The difference is that not only constant depth data VBD but also aftertouch vibrato depth data KVBD is taken into account as envelope data ENV. In the 71st district, data KVBD is retrieved from the sixth stage of register 106 to co-work with data VBD. This data KV B f is applied to the AND circuit 281 in FIG. 12, and the valid bits (6 bits from the weight of 1 and 2 cents to the weight of 387 cents) are selected at the timing of the signal IT61 and sent to the adder. 282 input B. The input A of the adder 282 is supplied with data (VBI) from the ANDRO path 272, and the output signal C for a one time slot delay.

+1 is applied to input Ci.

Therefore, in this adder 282, the vibrato depth data V
BD and aftertouch vibrato depth data KVBD are added serially. Its addition output rVBD+KV
BDJ:j is given to the 77-do circuit 278 in FIG.

As mentioned above, when aftertouch vibrato is selected, the signal KVBSS is 11", and the AND circuit 2
78 is enabled and 279 is disabled. Depth data with aftertouch full force rVBD 10VBD J
is selected by the AND circuit 278 at the M No. 9 T tb y ib (') timing (summer calculation timing of the upper 8 bits), and the OR circuit 277 and the AND circuit 189
．． It is repeatedly loaded into shift register 164 through adder 168. In this way, the envelope data ENV becomes one shift in which the aftertouch vibrato depth data KVBDft is added to the constant vibrato depth data VBD.
The vibrato depth will be controlled according to the key touch.

(5) Supplementary explanation of attack pitch and vibrato As mentioned above, in attack pitch. The temporally changing envelope data ENV is obtained by sequentially subtracting the initial value Apist minus the value ΔApts shifted to the lower order by 8 bits from the initial value APiS. Therefore, the initial f[APiS
Even if it is a 1st shift where the power is unstable, the calculation unit CUL6 can calculate △AP.
When iS is subtracted 28-256 times, data]l! ;NV
1 dead body. Therefore, 1 Samurai 1 until the envelope data ENV changes from the initial 1 direct APiS to 0.
The river, that is, the attack pitch is power, 5 o'clock 1 H 1, well.
It is unrelated to the initial 1st shift APiS, and the operation, =! 1cUL
The synchronization of the highest pit carry signal of No. 4 is determined by the attack pitch envelope plate data APER. If there are 100 warriors, Gator APEt (is constant (
If the attack is correct (corresponding to the selected color), the same attack pitch will be applied for a certain period of time regardless of the initial touch number. And the depth of the attack pitch (initial value)
In response to the initial touch, the degree (depth) of the attack pitch is controlled as soon as the selected tone is selected. A similar phenomenon can be seen in the wave number K'kd at the start of sound in natural instruments, so by controlling the attack pitch of the body as described above, it is possible to increase the effectiveness of natural instruments. When the data APER is the same, three different initial states of envelope data ENV applied to APiS2 and APiS3, respectively, are shown in FIG. 820 (a).

Envelope data ENv in delay vibrato
The same thing can be said about the change in . In this case, the target value to be reached is the vibrato depth data VBD, and the value ΔVB is 77 points lower than the target value VBD by 8 bits.
The data KNV is obtained by sequentially adding I). Therefore, no matter what value the target i direct VBD is, the arithmetic unit C
When 71D is calculated ΔVBDt=2=256 times in UL3, the data ENV reaches the target value VB[). Therefore,
The time it takes for delay vibrato is the target 1 shift VBI)
is unrelated to the magnitude of the delay vibrato envelope plate data L) VER (DV E R
) determined by 凇る. When the data IJvER is the same, the three target values of 14 (VBI) 1, VBD2
, VBD3DZ, respectively, are schematically shown in FIG. 20(b). Therefore, it is necessary to make special calculation adjustments to keep the delay vibrato time constant as the vibrato depth changes, which is set using volume V4 (461). The delay vibrato for 11 is always realized, and the 11 is much easier to use.

There are the following characteristics in the modulation 100 formation in the normal Hifrado (and the aftertouch vibrato, delay vibrato, and attack pitch are also the same). This is possible by accumulating digital data in the arithmetic unit CUL1 without using an analog I!21 command such as a 4-voltage "d1" wholesale oscillator to set the frequency of the glv top and f network signal (VAL) variably. The point is that the data (APR, VBR) accumulated by the arithmetic unit CUL1 is
ζni Snake, Ji! , a carry-out signal (Ill signal) is generated based on a hunch, and the arithmetic unit CUL2 outputs I' during the time period corresponding to this carry-out signal.
lff Pheasant's reward data △ENV is repeatedly increased or decreased, and each time it reaches the target value (h; NV), the direction of addition and subtraction is changed, and the data (APR) accumulated by the arithmetic unit CULI is , Vf3k) is processed by the arithmetic unit CUI2. Second, it is easy to control the frequency and depth. In other words, the change width data ΔE N
Since the envelope data ENVt-7 bits F, which is the target value (turning point of VAL) than Vk, has been shifted, no matter what value the target value, that is, the envelope data ENV (or depth data VBD), △
When ENV'&2'=128 times, data VAL becomes O.
When ΔENV is subtracted 128 times, data VAL changes from ENV to 0. When ΔENV is subtracted 64 times, VAL changes from 0 to -TEN.
When the value changes to V and ΔENV is added to the ash 64 times, VAL
jyoichi! - Varies from ENV to O. Therefore, the repetition period of the K-tone signal VAL is independent of the vibrato depth VBI) (envelope ENV), and is determined by the period of the carry signal generated from the arithmetic unit CUL1, that is, the rate data VBH.

Two different depth data (VBL) when the rate data VBR is the same.
The state of t0 is schematically shown in Section 20 (e).It can also be seen from this figure that as long as the rate data VBkc is constant, the frequency becomes constant in a deep envelope). Therefore, there is no need to mutually adjust the same wave number and depth, and both can be independently controlled, making it easier to perform the same wave number and depth.

(6) Slur In FIGS. 12 to 14, detailed circuits for controlling the slurr effect are omitted, so slurr control will be briefly explained below.

In FIG. 14, the system clock pulse 81 s
The 32-stage/1-bit serial shift register 283, which is shift-controlled by e, is used to store 1s and 1sKc of the strings to be sounded in the single note mode. The slur value calculation control unit 284 uses all lines of calculation to smoothly change this information N5KCt from the value corresponding to the previous press birth to the value corresponding to the new press by Z.1 during slur control. The register 67 of the single note key assigner 14A shown in FIG. This frequency information converter 601
outputs frequency information MKCLt- expressed in frequency all logarithm format corresponding to key code MKC. In FIG. 14, the Fritzno flop 224, the OR circuit 5, the AND circuits 212, 213, 241, 245, and the circuits 619 to 6
26 is for executing slur control. As shown in FIG. 4, when the slur start signal is applied, the flip-flop 224 is set and the SLQ signal becomes l#.

In the slur calculation control unit 284, this SLQ
When the number reaches 11, calculation for adding a slur effect is started. In other words, a difference KCD (not shown) is obtained between the seed wave ridge information SKC of the previous pressing stored in the register 286 and the frequency information MKCL of the pressed key given from the converter 601, and The minute value ΔKCD corresponding to this difference KCD
(not shown) t-determine. Then, by repeatedly adding or calculating the ΔKCD to the frequency information S K CK of the previous press birth, this SKC is set as the new frequency VI.
Information gradually approaches MKCL and finally SKC=MKC
When L is reached, all slur control ends. This △KCIJ
The timing I of the repeated calculation is determined by the calculation unit CU in FIG.
It is set by the carry signal CUT given from L4. Arithmetic unit CUL4 accumulates slur rate data SLRt- applied from slur rate data computing section 606 in FIG. 12 via AND circuit 195. In m= section 606, slur rate data 5
LRt is obtained based on the slur rate exponent data SRE output from the fourth stage of the register 105 in FIG. 7, and the mantissa data SRM and V output from the eighth stage.

As mentioned above, in the register 67 of FIG. 4, new suppression 9. , the key code XKC is loaded.

Therefore, the output 1 of the register 67 switches in synchronization with the 17th time slot. The state of the key code MKC output from this register 67 at each time slot is as shown in FIG. That is, during the 32 time slots from the 17th time slot to the next 16th time slot, bits N1 to B3 are set to 4 bits every 8 time slots.
go around This key code IVIKc is added to the AND circuits 602 and 604 in FIG.
8 (see FIG. 5), the lower bits N1 and N2 of the key code MKC are selected via the AND circuit 604 enabled in the 17th and 18th time slots Vζ,
OR circuit 616t - 2-stage 7 lip-flop 61
4 is input. The two bits N1 and N2, each delayed by two time slots in the flip-flop 614, are input to the flip-flop 514 via an AND circuit 605 that is enabled from the 19th to the 16th time slot. (See Figure 21 314Q). This flip flop 6
The output of 14 is selected between the 25th and 8th time slots via the AND circuit 606 enabled by the old-q25T8 (Figure 5), and the MK output is selected via the OR circuit 615.
Output as CL.

In the subsequent 9th to 16th time slots, the AND circuit 302't- is enabled by the signal 9T16.
All 8 bits of the key code MKC are selected through the OR circuit 615t and output as lut KCL. Therefore, the frequency information 1vlKCL is 24-bit data from the 25th time slot to the next 16th time slot, as shown in the N2t diagram, and the upper 8
Bit (16th time slot to 9th time slot)
is OII and key code MKC octave code B3
．． B2. Bl and note code N4, N3, N2,
The lower 16 bits are the lower 2 of the note code.
Bits N2, N1t - are added repeatedly. Frequency information with such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 56-74.
298, etc., and expresses the frequency of the musical tone corresponding to the key code MKC as a logarithm (cent value) with the base of 2.

When the SKC of the register 283 matches IVIKcI, the SLQ signal becomes "0" and the slur control ends. After the slur control is completed, the frequency information MKCL corresponding to the key code MKC passes through the arithmetic control section 284 and is input to the register 286 as is. Therefore, in the steady state, the information SKC output from the register 283 is the same as the information MKCL, which is delayed by one time slot. As shown in FIG. 21, MKCL occurs between the 25th time slot and the 16th time slot, so the weight of the data held in each stage of the register 283 in the 17th time slot is as shown in the figure. become. Lower 2 bits of note code) N2
．． The weight of the portion where Nl repeats is expressed as a cent value. In other words, when the key code is converted to frequency information in logarithmic representation with base 2, the lowest bit N1 of the original note code has a weight of 75 cents. (9th stage of register 283) is approximately 38 cents, plus 1
The lower bit has a weight of approximately 19 cents.

Figure 22 shows a detailed example of the musical tone signal generator 21 (Figure 2);
In particular, the frequency signal changing circuit 21 included in the generating section 21
This shows the details of A. Frequency information change circuit 21
A is the register 166 of the effect adding circuit 20 (FIG. 13)
The same wave number information t of the musical tone to be generated is changed according to the change given from:, 11 signal instantaneous value data VAL, and pitch-controlled simple wave number information @ is output in full.

The frequency information changing circuit 21A is shared between the single note mode and the ventral dorsal mode, and the circuit function changes somewhat depending on which mode is selected.

When the single tone mode is selected, the frequency information changing circuit 21A uses the calculator CUL in FIG. 13 for the single tone river wave number information SKC given from the register 286 in FIG.
All the modulated signal instantaneous value data VAL given from the register 166 in Z are added. As mentioned above, the frequency information SKC
is in logarithmic representation (.

cent value), and the data VAL is also expressed in cent values. Therefore, add (or subtract) both data
By doing this, frequency information 1og in logarithmic form (cent display) is obtained by increasing the cent value of C to the single note frequency information S to the higher or lower range side by the cent value corresponding to the data VAL.
F is obtained.

The single tone frequency information SKC consists of the upper 7 bits of the key code part (83 to Nl) and the lower ones from Ascent to 1.
It is used in calculations separately from the data portion corresponding to the weight of 2 cents. To this end, the information SKC is taken from the eighth stage of the register 286 of the fourteenth garden via line 625, and from the fourteenth stage the information SKC is taken from the line 32.
Information SKC is taken out via 6'ft. In FIG. 22, information SKC on line 625 is input to an 8-stage/1-bit shift register 629 and is sequentially shifted in accordance with system clock pulses φ1 and φ2. The outputs of the second to eighth stages (7 bits in total) of the shift register 629 are given to the latch circuit 360, and the outputs of the register 6
The contents of 2 and 9 are latched in parallel by the latch circuit 360. Shift register 28 in the 17th time slot
The weight of each stage of 6 is as shown in FIG. , N2, N3,
N4, B11B2, B3, and PA0# appear sequentially on line 625 and are sequentially loaded into shift register 629 of FIG. Therefore, in the next 25th time slot, the weight t of each stage of the shift register 329 becomes as shown in the figure, and the signal 2 generated at this time becomes
5y32, the latch circuit 630 has the upper 7 of SKC.
The key code portions B3-N1 of the bits are latched. In this way, the latch circuit 660 always outputs the key code portions B3 to Nl of the single tone frequency information SKC.

The output of latch circuit 630 is input to selector 3610B input. Single sound mode selection switch IVION No-8W
Single note mode selection signal MONO outputted from (Figure 2)
is applied to the B selection control input SH of the selector 661, and in the single note mode, the selector 661 selects data B3 to Nl applied to the B input from the latch circuit 630.

On the other hand, information SKC on line 626 is provided to AND circuit 662. The AND circuit 662 is supplied with the single note mode selection signal MONO and the timing signal -Q17T22, and selects the data on the line 626 in the section from the 17th to the 22nd time slot on the condition that the mode is the single note mode. Shift register 28 in 1% 17 time slots
The weights of each stage of 6 are as shown in FIG. 14, so in the 17th to 22nd time slots (total 6 time slots), the 6-bit data portion of the information SKC has a weight of 1.2 cents to 38 cents. appear sequentially on line 626, and these serial 6-bit data SKC (38
~1.2) is selected by the AND circuit 362 and the adder 36
6 (see FIG. 23).

The KPA multiplication signal TAL stored in register 166 in FIG. 13 is taken out from the eighth stage via line 627 and from the ninth stage via line 628. In FIG. 22, modulated signal data VkL on line 627 is applied to an AND circuit 364, and selected in the 17th to 24th time slot section by timing signal 17T24 (FIG. 5). Since the weight of each stage of the shift register 166 in the 17th time slot is as shown in FIG.
In the time slots (8 time slots in total), data V
The data with weights of 1.2 cents to 75 cents of the upper 8 bits of AL and the sign bit (S) are on line 62.
7 appear sequentially, and these are selected by an AND circuit 634. The output of the AND circuit 334 is applied to the input A of the adder 633 via an OR circuit 665. Therefore, the input A of the adder 666 receives the upper 8 bits (1st and 2nd cents to 7th cent) of the data VAL in the i17th to 24th time slots.
7 sign bits with a weight of 5 cents) are serially input as shown in the 23rd factor.

As is clear from FIG. 2.3, in the adder 666, the lower 6 bits of data SKC (32 to 1.2) of the information SKC are
A serial operation is executed by adding the data VAL and the data VAL with the same weight. The carry signal generated by the addition of the bits with the weights is output from the carry output C0+1 in the next time slot,
Ci large input is given and added to the data one bit higher. Note that since the data VAL may be expressed as a negative value (two's complement number), in that case, the adder 666 essentially performs subtraction.

The output of the adder 6°66 is input to an 8-stage/1-bit shift register 666, and the clock pulses ν3, φ3,
It is sequentially shifted according to φ2. shift register 666
Similarly to the shift register 629 and latch circuit 667, the latch circuit 637 is for replacing the serial addition output with all parallel data. Addition I! on the bits with weights of 1 and 2 cents output from adder 633 in the 17th time slot! The result is transferred to shift register 6 in the 25th time slot eight time slots later.
It is shifted to the 8th stage of 66. Therefore, at the 25th time slot, the ffl'% of each stage of the shift register 666 corresponds to 1.27 to 75 cents and the sign bit (S), as shown in the figure, and these differences This data is the timing signal 2.
5y32, it is latched in parallel by the latch circuit 667.

1 or 2 cents to 75 latched in the latch circuit 667
8-bit data corresponding to the cent weight and sign bits are applied to input A of an 8-bit parallel adder 668. The upper 2 bits of input B of the 7IOS device 668 contain the lower 2 bits N of the key code output from the selector 631.
l and N2 are respectively input. Also, additional $4. vessel 668
Data NNI and NN2 are input to the input B of the lower 6 bits, and these are always '0#' in the single note mode. Therefore, the adder 668 adds the least significant bit N1 of the key code portion of the information SKC to the addition result of the weight of 75 cents given from the latch circuit 367, and adds N2 of the key code portion is added to the addition result. The reason for this is that the adder 666 essentially only adds the bits with a weight of 38 cents to 1.2 cents of the information SKC and the bits of the corresponding weight of the data AL; SKC and data V
This is because addition regarding bits with a weight of 75 cents or more has not yet been performed regarding the operation with AL.

Therefore, adders 668 and 669 perform addition for bits with a weight of 75 cents or more.

The most significant bit carryout output Co of the adder 668
is the carry-in force Ci of the least significant bit of the adder 669
given to. This adder 669 is a 5-bit parallel adder, and of the key code part of the information SKC output from the selector 661, the upper 5 bits B3, B2, B1,
N4, N3 power; given to each input B. In the logarithmic frequency information SKC as described above, the lowest bit of the key code part is equivalent to the weight t of 75 cents.
Bit N2 above it corresponds to a weight of 150 cents.

Therefore, in the adder 668, the output of the latch circuit 667 of 75 cents and the weight one bit above it and the bit Nl
, with N2? Add each. Then, an adder 639 performs addition for bits of higher weight.

By the way, in calculations using this complement, the sign bit must be extended to the highest order. Therefore,
The latch circuit 667 includes an extra latch position it for the expanded sign bit signal PS, and the output of the adder 666 is input to this latch position. line 628
data VAL is applied to the AND circuit 640.

As shown in FIG. 23, the sign bit (
S) appears on line 628 one time slot later at the 25th time slot. In the AND circuit 640, this one time slot delayed sign bit (S) k
Sampled by timing 1g number 25y32,
It is applied to adder 6330 input A via OR circuit m365. The addition output corresponding to the delayed sign bit CF3') is latched by the ratchet circuit 667 and used as the expanded sign bit signal PS. This signal PS is applied to each input A of adder 369. Thus, the extended sine bit (oats L/“1” or all 60
”) is added to the top five bits) 83 to N3 of the information SKC.

With the above configuration, when the single tone mode is selected, the frequency information changing circuit 21A adds the modulation signal data VAL to the single tone frequency information SKC with the weights of both sides being matched. Then, when the data VAL is a negative value (two's complement), a substantial subtraction is performed. In this way, the frequency information 1 og
is output from the Calo calculator 669.668. The weight of each bit output from the adders 669 and 368 is as shown by ζ in the figure. If there is no pitch shift at all, the truth value of each bit of the weight is the lower two bits N2 of the key code part, as shown in parentheses at the weights of 38 cents to 1.2 cents. , Nl are repeated.

The pitch-controlled logarithmic frequency information logF outputted from the frequency information changing circuit 21A is input to the logarithmic/linear conversion circuit 21B, and is converted into linear frequency information F. This frequency information Fi musical tone generation circuit 2
1C, and a musical tone signal having a frequency corresponding to the information F is generated from the circuit 2IC. This musical tone generation circuit 21
The musical tone generation method in C may be any method such as a frequency modulation method, a harmonic synthesis method, a waveform memory reading method, etc., and the details thereof will not be particularly explained.

When the multitone mode is selected, the frequency information changing circuit 21A changes the key code P of the pressed key in the multitone mode.
Logarithmic frequency information similar to that described above is formed based on KC, and modulated signal instantaneous value data V is generated for this frequency information.
Add AL. In the case of the multitone mode, a plurality of key codes PKC indicating the pressed keys assigned to the plurality of tone generation channels are output from the multitone key assigner 14B (FIG. 2) in a time-division manner for each channel, and the frequency information conversion circuit 2
1A is given. The key code PKC is B3 as mentioned above.
~Nl consists of 7 bits.

Each bit 83 to Nl of this key code PKC is given to the A input of selector 661. Single note mode selection signal MO
NO is I On, and the inverter 64 inverts this.
The A selection control input is enabled by the 10 output "'l", and the key code PKC for the double tone mode is selected.

Furthermore, the AND circuits 642 and 343 are enabled by the output 11'' of the inno(-taro 41), and the lower two bits N2 and Nl of the key code PKC are selected and the data NN2 and Nl are selected.
It is alternately inputted to input B of the lower 6 bits of adder 668 as N1. In this way, the key code PKC is the lower two bits) N2, N1t - which is repeatedly added to the lower order (that is, it is converted to frequency information in logarithmic form).
.

On the other hand, the AND circuit 662 is disabled by the signal MONO 10#, and the adder 666 outputs the modulated signal data VALt as is. Therefore, the latch circuit 667 latches the data VAL as is and its sign bit extension IMWPS. Therefore, adder 668.
In 669, data VAL is added to the logarithmic frequency information corresponding to the key code PKC by matching the weights of both (subtracted when VAL is negative), and pitch-controlled logarithmic wave number information l is obtained. Output ogF. The musical tone generation circuit 21C includes a plurality of musical tone generation channels, and generates musical tones in each channel based on frequency information of each channel provided in a time-sharing manner.

Of course, the musical tone generation circuit 21C is configured to be able to generate musical tone signals corresponding to both the single tone mode and the multiple tone mode. generation channel).

A single-note mode selection signal MONO, a single-note key-on signal MKON output from the single-note key assigner 14A (FIG. 4), and a double-note key-on signal KON output from the multiple-note key assigner 14B are supplied to the musical tone generating circuit 21C. . If single note mode is selected (MON
When O is @l''), the musical tone generation circuit 21C forms the amplitude envelope of the musical tone based on the single-note key-on signal MKON, and uses the single-note musical tone generation channel to generate the musical tone signal in accordance with this amplitude envelope. Controls pronunciation.If double note mode is selected (MONO is @0)
In the case of #), an amplitude envelope of musical tones is formed for each valley channel based on the key-on signal KON for multiple notes, and the sound generation of musical tones of each channel is controlled by this amplitude envelope. Further, aftertouch level data ATL, sustain speed data STR, and initial touch level data ITL are given to the musical tone generation circuit 21C from registers 106, 107, and 108 in FIG.
Based on these data, the volume of the musical tone and the sustain time of the amplitude envelope are controlled.

Note that the 13th tooth arithmetic unit CUL2 uses data ΔENV obtained by shifting the envelope data ENV (achieved target value) obtained by the arithmetic unit CUL6 to a lower position by a predetermined bit as the change width data, but this is not limited to this, and other appropriate data may be used. Data generated by change width data generation means? It may also be used for calculations. Furthermore, the present invention is not limited to those that perform serial calculations such as the calculation units CULI to CU L4), and parallel calculation units may be used.

Further, in the embodiment, the change width data ΔE is calculated by the arithmetic unit CUL2.
The timing for calculating NV is the output timing of the carry signal of the most significant bit of the calculating unit CUL1, but the timing is not limited to this, and the calculation is performed in the calculating unit CUL2 when the contents of the calculating unit CULI reach a predetermined value. It may also be done.

To do this, for example, a comparator may be provided to detect that the content of the arithmetic unit CUL1 has reached a predetermined value, and the calculation timing of the arithmetic unit C: U L2 may be controlled based on the output of this comparator. It is also possible to change the latch timing of the latch circuit 257.

Although the above embodiment describes a modulation signal generation device for vibrato (pitch modulation [1]), a similar modulation signal generation device may be used to modulate volume and other elements.

As explained above, according to the present invention, the numerical data corresponding to the frequency of the modulation signal is repeatedly calculated by the first calculation means, and the calculation timing of the second calculation means is determined according to the output of the first calculation means. Since the frequency of the modulation signal can be set by setting , a complicated transmission-controlled oscillator is not required, and the circuit configuration is simplified. Also, the second
The calculation means is configured to add or subtract change width data of an arbitrary value at the calculation timing set by the first calculation means, so by controlling the calculation operation in this second calculation means, the depth of the modulation signal can be adjusted. This makes it possible to perform control, eliminates the need for a complicated shift circuit for depth control, and simplifies the circuit configuration in this respect as well.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention, FIG. 2 is a block diagram illustrating the overall configuration of an electronic musical instrument embodying the present invention, and FIG. 4 is a circuit diagram showing a detailed example of the single note key assigner shown in FIG. 2, FIG. 5 is a timing chart showing an example of the timing signals used in each part of FIG. The touch sensor shown in Figure 2, various effect setting controls,
FIG. 7 is a circuit diagram showing a detailed example of the analog voltage multiplexer and A/DT converter portion, FIG. 7 is a circuit diagram showing a detailed example of the control and storage section in the A/D converter section of FIG.
A signal waveform diagram to show that both initial touch and aftertouch are detected based on the output of the aftertouch sensor shown in the figure. Figure 9 is a signal waveform diagram for analog/digital conversion by the circuits of Figures 6 and 7. FIG. 10 is a timing chart showing the normal operation of the A/D converter in FIG. 6 (when the initial touch is detected outside the board); FIG. Timing chart showing the generation state of main signals at the time of initial touch detection in Fig. 7, Fig. 12 and Fig. 13
14 and 14 are circuit diagrams each showing a detailed example of the effect imparting circuit in FIG. 2 divided into three parts, and FIG. 15(a) shows an example of the modulation signal and its envelope at attack pitch, delay vibrato, and normal vibrato. Figure 15 (b) is a timing chart showing the states of various control signals in Figures 13 and 14, corresponding to Figure (a), and Figure 16 is the timing chart shown in Figure 12 at the start of attack pitch control. 14 is a timing chart showing various signal states, FIG. 17 is a timing chart for explaining serial calculation in the arithmetic unit of FIG. 13,
Fig. 18 is a timing chart for explaining the conversion process of the delay vibrato envelope plate data in Fig. 12, and Fig. 19 is a timing chart for explaining the delay vibrato envelope plate data conversion process.
] Graph showing the relationship between the control data setting volume, delay vibrato start time data and delay vibrato envelope plate data, and the relationship between the delay vibrato start time and delay vibrato period determined by these data 1ζ, FIG. 20 (11) Figure 3 shows the changes in the envelope data of the modulation signal in attack pitch control 1 corresponding to three different initial values, and Figure 3 shows the changes in the envelope data of the modulation signal in delay vibrato (2) and (b). Figure (C) shows the changes in the modulation signal in vibrato, f!, corresponding to two different target values. : Figures shown corresponding to two different depths (envelope instantaneous values), Figure 21 is the first
Figure 4 is a timing chart showing the operation of converting the pressed key code in single note mode into logarithmic frequency information in the frequency information converter, and Figure 22 is a detailed example of the musical tone signal generator in Figure 2, especially when frequency information is changed. The circuit diagram shown in FIG. 23 is a timing chart showing the arithmetic unit combining of the lower bits of the single tone frequency information and the modulation signal instantaneous value data in FIG. 22. 400... Frequency data generator, 401... First
calculation circuit 1, 404...change width data generator, 4
05...Second arithmetic circuit, 409...Arithmetic control circuit, 410...Target value data generator, 411...
Comparator, V 1 - Volume for setting vibrato speed (frequency), v 2 - Volume for setting vibrato speed (depth), CULI - First computing unit, CU I, 281. Second arithmetic unit, COMI, C0M2... comparator, 215 to 2
21.230 to 235.258.259.261.2
62...Circuit for fully controlling the addition/subtraction mode of the second arithmetic unit, CUL3...Third arithmetic unit for generating time-varying depth data, ΔENV...Second arithmetic operation Data showing the range of change in the vessel. Patent applicant: Nippon Musical Instruments Manufacturing Co., Ltd. ``'1A''3''c [Knee 2 Figure 1

Claims (1)

[Claims] 1. A first numerical information generating means that generates a first numerical value for setting the frequency of a modulated signal, and a means for repeatedly adding or subtracting the first numerical value so that the content of the calculation is predetermined. a first calculating means that outputs a control signal each time a value is reached; a second numerical information generating means that generates a second numerical value indicating the range of change; a second arithmetic means for adding or subtracting the numerical value of the second arithmetic means; and a control means for controlling the arithmetic operation in the second arithmetic means according to a target value for setting the depth of the modulation signal; A modulation signal generating device for an electronic musical instrument, wherein the output of the calculation means is used as the modulation signal for modulating musical tones. 2. The modulation of the electronic musical instrument according to claim 1, wherein the second numerical information generating means sets the second numerical value by shifting the target value downward by a predetermined number of digits. Signal generator. 3. The control means compares the target value generation means that generates a take indicating the target value with the output of the second calculation means indicated by mJ, and according to the result of this comparison, the second and a comparison means for switching the calculation means from an addition mode to a subtraction mode or vice versa, so that the calculation content of the second calculation means repeats increases and decreases within the range of the target value. A modulation signal generating device for an electronic musical instrument according to scope 2. 4. The target value generation means outputs an upper limit target value when the second calculation means is in an addition mode, and outputs a lower limit target value when the second calculation means is in a subtraction mode. A modulation signal generation device for an electronic musical instrument according to claim 3. 5. The target value generation means includes a third arithmetic means that repeatedly adds or subtracts a numerical value corresponding to the maximum depth shifted lower by a predetermined digit, and the calculation content of the third arithmetic means is 5. The modulation signal generating device for an electronic musical instrument according to claim 4, wherein the data indicates a target value and the depth of the modulation signal is changed over time. 6. The modulation signal generation device for an electronic musical instrument according to claim 5, wherein the lower limit target value is the upper limit target value shifted lower by a predetermined number of digits.