JPS586683A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To perform efficient image pickup operation by providing an electrode which capacity couples with a photodetector and making the bias voltage of this electrode in a photodetection period different from bias voltage in a signal charge readout period. CONSTITUTION:A transfer electrode 13 is supplied with a binary-level clock which contains a vertical transfer clock. Then, an overflow control electrode 21 is applied with a bias voltage which has two levels, namely, having a high level during photodetection and at a low level during the reading of signal charge. In this case, the bias voltage of the electrode 21 drops during the reading of signal carge, so the potential of an element part 1 capacity-coupled with the electrode 21 also drops. Therefore, the level of the bias voltage applied to the electrode 21 is selected adequately to read the signal charge out of the element part 1 to a transfer part 2 through a gate part 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device constructed using a charge transfer element, and in particular, a light receiving section is formed of a photodiode type photoelectric conversion element, and a signal charge obtained in the light receiving section is The present invention relates to an improvement of a solid-state imaging device in which images are read out and transferred.

A solid-state imaging device using a charge transfer device, for example, a charge-coupled device (charge-coupled device)
It's called OD. ) CCD imaging devices configured using CCD imaging devices can be roughly classified into frame transfer type and interline/transfer type, and each type is used depending on the need, taking into consideration the advantages and disadvantages of each. One of the characteristic differences between the two is the difference in the photosensitive area. Frame transfer type C
In a CD imaging device, a photosensitive section is composed of a CCD group, and signal charges obtained in the photosensitive section CCD group are transferred to a storage section composed of another CCD group. On the other hand, in an in-line transfer type CCD imaging device, the photosensitive section is configured by an array of photodiode type light receiving element sections, and the signal charge obtained in each light receiving element section is transferred to the CCD via a readout gate section. The data is read out to a vertical transfer unit configured in groups. When the photosensitive area is composed of a photodiode type light receiving element, signal charges are accumulated using the PN junction capacitance between each photosensitive element and the semiconductor substrate. This is smaller than that in the case of a CCD group, and one of the challenges is to increase this charge storage capacity, that is, the maximum amount of charge that can be handled.

'An example of an interline transfer type CCD imaging device in which the photosensitive section is composed of an array of photodiode-type light-receiving elements; as shown in FIG. A light receiving/vertical transfer section 3 comprising a plurality of photodiode type light receiving element sections/ and a vertical transfer section 2 formed of a plurality of CCD groups arranged along the vertical rows of the light receiving element sections/. , a horizontal transfer section coupled to the light receiving/vertical transfer section 3, and an output section 5, from which a signal output terminal 5a is led out. A predetermined vertical transfer lock signal and horizontal transfer lock signal are respectively supplied to the vertical transfer section 1 and the horizontal transfer section 3, and a charge transfer operation is performed. Then, for example, the signal charge obtained in each light-receiving element section by light reception within the l-field period is read out to the vertical transfer section 2, and is transferred to each horizontal retrace period by the charge transfer operation of the vertical transfer section 2. The data is sequentially vertically transferred to the horizontal transfer unit q for each corresponding period. Signal charges are sequentially transferred to the horizontal transfer section for each signal charge obtained in 1 horizontal rows of the light receiving element section 1, and then horizontally transferred to the output section during a period corresponding to each horizontal video period. An imaging output signal is obtained at a.

More specifically, as shown in FIG. 2A, in the light receiving/vertical transfer section 3, a readout gate section t is formed between each vertical column of the light receiving element section l and each vertical transfer section 1, and the light receiving element An overflow control gate section 7 is formed adjacent to each vertical column of sections/, and an overflow drain g is formed adjacent thereto. A channel stopper 9 and an IO are formed on the opposite side of the vertical transfer section 2 from the read gate section 6 and between each light receiving element section 1. Figure 2B
2B shows a cross section taken along line 2B-2B in Figure A, in which the above-mentioned parts are formed on one surface side of the P-type semiconductor substrate //, and the insulating layer 1
2, a common transfer electrode 13 is placed above the vertical transfer section λ and the read gate section; -, yo7)o
- Separate overflow control cases on the channel stopper 9, channel stopper 9,
) electrode 1t' and channel stopper electrode/S,
They are arranged respectively.

In such an interline transfer mccD imaging device,
For example, as an example of field readout, the transfer electrode /3 is supplied with a clock signal φA/ as shown in FIG. 3, and the overflow control gate electrode /F and channel stopper electrode IS are supplied with A predetermined bias voltage V, respectively. and Vc/ are applied. Considering the accumulation and readout of signal charges in this case, when the clock signal φA/ applied to the transfer section %13 is at the high level V/ which is the readout section, the potential of the readout gate section B is at the high level V/. The electric charge in the light-receiving element part is transferred to the vertical transfer part via the readout gate part 6, and the potential of the light-receiving element part becomes the corresponding high potential (deep potential) V/. is defined as a potential vl that is equal to the potential of . Next, when the clock signal φA/ of the transfer electrode 13 reaches the transfer lock ψ7 between the low level v2 and v3, the potential of the read gate part B becomes a low potential (shallow potential), that is, transfer V2 and v3 correspond to the higher level v2 and lower level v3 of the lock ψV, but the light receiving element l is in an electrically floating state and the high potential V/
and form a potential well. When light is received in this state, signal charges corresponding to the amount of incident light are accumulated in the light receiving element portion l. At this time, the accumulated signal charge is applied to the overflow control gate electrode /4' at a voltage V
.

The potential V of the overflow control gate section 7 is defined as follows. When the potential barrier is exceeded, the excess charge is discharged to the overflow drain/g via the overflow control gate section 7. Next, when the clock signal φA/ of the transfer electrode 13 reaches the high level V/ of the readout portion again, the potential of the readout gate portion B becomes V/, and the signal charge accumulated in the light receiving element portion L is read out. It is transferred to the vertical transfer section via the gate section 6. That is, signal charges are read out. Then, when the clock φA/ of the transfer electrode /3 becomes the low level transfer lock ψV again, a potential well is formed in the light receiving element l, and a new signal charge starts to be accumulated according to the amount of incident light. At the same time, the signal charges read to the vertical transfer section 2 are vertically transferred according to the transfer lock ψV.

Here, the storage capacity of the signal charge in the light-receiving element part l, that is, the saturation charge amount Qm is the potential of the light-receiving element part at the time of charge accumulation, R, and the readout 'I'-t part at the time of reading out the signal charge. A's t
The difference v, -v between the potential V t and the potential vo of the overflow Φ co/trol gate section 7.

Q m
= Cs (V IV o ). In the end, the maximum amount of charge handled by the light receiving element section / is the potential V/ of the readout gate section 6 at the time of signal charge readout and the potential ■ of the overflow control gate section 7. Potential barrier created by v, -yo
It will be stipulated by.

FIG. 9 schematically shows the configuration of another example of an innotar line transfer type CCD imaging device having a photodiode type light receiving element section. This example, similar to the device shown in FIG. a light receiving/vertical transfer section 3' including a vertical transfer section 2';
It has a horizontal transfer section 5a', an output section ter', and a signal output terminal 5a' similar to those in the device shown in the figure, and furthermore, it has a light receiving and
It has a storage section /6 arranged between the vertical transfer section 3' and the horizontal transfer section V'. One end of each vertical transfer section 2' is connected to the storage section 1B to form horizontal rows 17 of storage/transfer sections as many as the horizontal rows of light receiving element sections 1'. A predetermined vertical transfer lock signal is supplied to the vertical transfer section 2' and the storage section lB, respectively, and the horizontal transfer section q'
A predetermined horizontal transfer lock signal is supplied to perform a charge transfer operation. For example, the signal charge obtained in each light receiving element section /' by light reception within the l field period is
The signal charge is read out to the vertical transfer section 2', and is vertically transferred from the vertical transfer section 2' to the storage section 16 at high speed, and the signal charges obtained in each horizontal column of the light receiving element section l' are stored and transferred in the storage section 16. are moved to each horizontal column/7 of the section. The signal charges transferred to the storage section 16 are sequentially transferred to the horizontal transfer section V' by l horizontal columns 17 every period corresponding to each horizontal retrace period, and this is transferred to the output section V' during a period corresponding to each horizontal video period. The signal is horizontally transferred to S', and an imaging output signal is obtained at signal output terminal &a'.

More specifically, as shown in FIG. A channel stopper/g is formed on the opposite side of the light receiving element section l' from the readout gate section 6' side and between each light receiving element section 71. FIG. 5B shows a cross section of MB-4B in FIG. A common transfer electrode /9 is disposed on the vertical transfer section 2' and the read gate section 2' via the insulating layer 72', and a channel stopper electrode 20 is disposed on the channel stopper 1g. ing.

A clock signal φA2 having a waveform as shown in FIG. 6 is supplied to the transfer electrode /9 of the CCD 1 imager array configured in this manner, for example, as a field readout signal 11, and a clock signal φA2 having a waveform as shown in FIG. A predetermined bias voltage vc2 is applied to the stopper electrode 20. First, when the clock signal φA2 is at the highest level v, /, the potential of the read gate section 6' is a high potential vl' corresponding to v, /.
Then, the charge in the light receiving element section /' is transferred to the vertical transfer section λ' via the readout gate, and as a result, the charge in the light receiving element section /' is transferred to the vertical transfer section λ'.
The potential becomes a high potential V/'.

Next, when the clock signal φA2 reaches the vertical transfer lock 97' where the low level v2/ is on the high level side, the potential of the read gate section 6' decreases, but the light receiving element section/'
is electrically in a floating state and maintains the potential V/ to form a potential well. At this time, the charges transferred to the vertical transfer section 2' are transferred to the storage section/by the vertical transfer lock ψV'.
6 is transferred at high speed. Next, the clock signal φA2 is set to V
, / becomes a much lower level VZ, and this state continues until the end of the light receiving period that has already begun. At this time, the potential of the readout gate section 6' becomes the potential vtI corresponding to vp, the light receiving element section l' accumulates signal charges corresponding to the amount of incident light, and this accumulated signal charge is caused by the potential VF of the readout gate section 6'. When the potential barrier is exceeded, the excess charge is discharged to the vertical transfer section 2' via the read gate section 6'. That is, in this case, the successive gate section 6' functions as an overflow control gate section and the vertical transfer section 2' functions as an overflow drain. Thereafter, the clock signal φA2 becomes part of the sweep transfer lock ψS similar to the vertical transfer lock ψV', and the charge in the vertical transfer block KO' is accumulated, for example, by the sweep transfer lock ψS. It is transferred in the opposite direction to the direction toward the section 16, swept out, and discharged.

Next, the clock signal φA2 returns to the readout portion of the highest level vil again, and at this time, the potential of the readout gate portion 6' becomes the highest potential vl', and the signal charge of the light receiving element portion /' is transferred to the readout gate portion 6'. The charge is read out to the empty vertical transfer section 2' through the sweep transfer, and the potential of the light receiving element section l' becomes vl'. This read signal charge is vertically transferred at high speed to the storage section /6 at the subsequent vertical transfer lock ψV' portion of the clock signal φA2, and the light receiving element section /' again accumulates the signal charge. start. Thereafter, the above-described operation is repeated.

Accumulation, readout, and high-speed vertical transfer of signal charges are performed in this manner, and the saturated charge amount Qm in the light receiving element section /' in this case is equal to the potential of the light receiving element section l' at the time of light reception, that is,
Difference v, /-V4 between the potential vl' of the readout gate section 6' during signal charge readout and the potential vp of the readout gate section 6' during light reception
It is determined by the product of z and the unit capacitance C8' of the light receiving element section /',
Qm=Cs'(V/'-V@).

After all, in the example of FIG. 3, the maximum amount of charge handled by the light receiving element portion l' is the potential v of the readout gate portion 6' at the time of signal charge readout.
It is defined by the potential barrier v,/-VII created by l' and the potential Vu of the read gate section 6' at the time of light reception.

The present invention provides a solid-state imaging device having a diode-type light-receiving element as described above, by improving the electrode structure and bias voltage supply, thereby reducing the maximum amount of charge that the light-receiving element can handle. Provided is a solid-state imaging device capable of increasing or decreasing the signal charge, and further, reading out signal charges from a light receiving element section to a vertical transfer section and vertically transferring the signal charges using a clock signal at the λ value level. It is something to do. Embodiments of the present invention will be described below with reference to FIG. 7 and subsequent drawings.

FIG. 7 shows an example of a solid-state imaging device according to the present invention in a cross section similar to that shown in FIG. 2B. This example 1C corresponds to an improvement of the solid-state imaging device shown in FIGS. 1 and 2, and the parts in FIG. 7 that correspond to those shown in FIG. 2B are given the same reference numerals. However, I will omit the detailed explanation of them.
In this example, an improved overflow control gate electrode is disposed on the overflow control middle gate section 7. This overflow control gate electrode 21 is connected to the light receiving element portion l.
The side end 2/a protrudes above the end of the light receiving element portion l and is capacitively coupled to the end of the light receiving element portion l.

As a result, when there is a change in the voltage applied to the overflow control gate electrode 21, the potential of the light receiving element section is changed accordingly.
3 Here, the transfer electrodes 13 provided on the vertical transfer section 6 and the read gate section 6 are supplied with a clock signal φA/similar to that shown in FIG. 3, for example, as shown in FIG. is supplied, and accumulation of signal charges by light reception, readout of accumulated signal charges, and vertical transfer operations are performed in the same manner as described for the solid-state imaging device of FIG. 2. At this time, the overflow control gate electrode For example, as shown by the solid line in FIG. A bias voltage "OX" which takes a level vO' lower by va than VO' is applied.As a result, the potential at the overflow control gate part is lower than VO' when reading signal charges, and corresponds to V. Low potential V.'(v0' is)
(Potential V corresponding to Iasumi pressure bell vO. Potential difference Va corresponding to voltage difference va is lower than that, that is, vo-Vo
'=Va), and when receiving light,
The potential V corresponding to o. Therefore, the bias potential V applied to the overflow control gate electrode 2/. The potential of the light-receiving element section l, whose potential changes in accordance with the change in X, is, at the time of light reception, Va. y' - the capacitance between the electrode 21 and the light receiving element part l) becomes higher (deeper)3.
Therefore, the effective potential barrier formed at the light receiving element in this case is (V/-Vo) 10 Va・-ζ- and Cs+
Cc, the level of the bias voltage applied to the overflow controller gate electrode is constant at vo.
Compared to the solid-state imaging device shown in the figure, the maximum handling charge 1rcqm increases by C811va-080cc.

In addition, overflow conotrol Kate electrode 21
As shown by the dotted line in FIG.
The level V is higher by a'. ', contrary to the above, the maximum amount of charge that can be handled in the light receiving element portion l decreases.

FIG. 9 shows another example of the solid-state imaging device according to the present invention in a cross section similar to that shown in FIG. This example corresponds to an improvement of the solid-state imaging device shown in FIG. 9 and FIG. Although I will omit the detailed explanation of them,
In this example, an improved channel stopper electrode 22 is disposed on the channel stopper 1g. This channel stopper electrode 22 has an end 22a on the side of the light-receiving element part l' extending over the end of the light-receiving element part /', and is capacitively coupled with the end part of the light-receiving element part l'. . As a result, when the voltage applied to the channel/channel stopper electrode 22 changes, the potential of the light receiving element portion l' changes accordingly. Here, the transfer electrode 19 provided on the vertical transfer section 2' and the read gate section 2' is supplied with a clock signal φA2 similar to that shown in FIG. 6, as shown in FIG.
is supplied, and the same signal charge accumulation by light reception as described for the solid-state imaging device of FIG. 5, sweeping transfer of the vertical transfer section -', reading of the accumulated signal charge, and vertical transfer operation are performed. At this time, the channel stopper electrode 22
For example, as shown in FIG. 10B, the level vc is lowered when receiving light, and the level vb is lower than vc when reading the signal charge.
The bias voltage V takes a level vC' lower by . X is applied. As a result, the potential of the channel stock and knee tg is set to a low level (earth voltage v) when reading signal charges.
, low potential V corresponding to /. '. This vc' is)
(Potential ■ corresponding to the Iasumi pressure bell vc. Lower by the potential difference vb corresponding to the voltage difference vb, vc-Vc'=
=Vb. Then, when receiving light, the potential vc corresponding to the Iasumi pressure vc rises again.
The potential of the light-receiving element portion l', whose potential is changed according to the change in the bias voltage VCX applied to the channel/output electrode 22, is equal to the potential vl of the readout gate portion 6' when reading signal charges when receiving light. 'YoC' Suvb・-rl-Ding (However, 00′ is the channel・Cs
+C.

The capacitance between the stopper electrode here and the light receiving element portion l' becomes higher (deeper). Therefore, in this case, the light receiving element portion l
The effective potential barrier formed is (V/'-Vs)+v
b・-410-, and in this case, Cs +Cc is also the maximum charge amount that can be handled compared to the solid-state imaging device shown in Fig. Qm is further increased by the bias voltage V applied to the channel bias voltage (-electrode 22). When the level is set to vc', the maximum amount of charge handled in the light receiving element section /' decreases, contrary to the above.

As described above, in the solid-state imaging device according to the present invention, an increase in the maximum amount of charge handled in the light receiving element section, or
In addition, the solid-state imaging device according to the present invention can reduce the accumulation of signal charges in the light receiving element section.
Reading of signal charges from the light-receiving element section to the vertical transfer section, transfer of signal charges in the vertical transfer section, etc. can be performed by supplying a clock signal and a bias voltage at the λ value level.

For example, in the embodiment of the present invention shown in FIG. ', and the overflow control gate electrode 2/ is supplied with a high level V when receiving light, as shown in FIG. 1/B. d and takes a low level vod' when reading the signal charge.
Apply OX'. In this case, when reading the signal charge, overflow control/'7) electrode 2
/ (D /<Iasumi pressure VOX' falls from level V.d to vod', so the potential of the light receiving element / which is capacitively coupled with the overflow control gate electrode 2 / becomes low (shallow). ).This means that
This corresponds to the fact that the potential of the readout gate section B has become higher (deeper) when the light receiving element section I is used as a reference. Therefore, overflow control - the level V of the bias voltage applied to the gate electrode 21. By appropriately selecting d', the signal charges accumulated in the light receiving element section l can be read out to the vertical transfer section λ via the readout gate section 6. The read signal charge is applied to the clock signal φA/' when receiving light.
In another embodiment of the present invention shown in FIG. 9, in which the high level side is set to level v2 and the low level side is set to level v3, the transfer electrode 79 is set to have the level v2 and the low level side is set to level v3. A binary level clock signal φA2' including a vertical transfer lock 97' and a sweep transfer lock ψS as shown in FIG.
As shown in FIG. 12B, the high level Wed at the time of light reception
When reading signal charges, a bias voltage vcx' at a low level vcd' is applied. Also in this case, when reading signal charges, the bias voltage vcx' of the channel stopper electrode 22 drops from the level Wed to the level Wed', and the potential of the light receiving element part /' capacitively coupled to the channel stopper electrode 22 also decreases. It becomes lower (shallower) accordingly. As a result, the potential of the read gate portion 6' becomes relatively high (deep), and signal charges are read from the light receiving element portion l' to the vertical transfer portion 2'. Furthermore, the vertical transfer section is controlled by the sweep transfer lock ψS and the vertical transfer lock 97', in which the high level side of the clock signal φ^2' supplied to the transfer electrode 19 is set to v2/, and the low level side is set to v3'. Sweep transfer at λ' and vertical transfer of signal charges are performed.

As described above, in the solid-state imaging device according to the present invention, even if it has a photodiode type light receiving element section, the solid-state imaging device according to the present invention does not use a ternary level or gray level clock signal. Accumulation, readout, vertical transfer, etc. of signal charges can be performed using a clock signal of the same value level.

As described above with reference to the embodiments, in the solid-state imaging device according to the present invention, an independent electrode capacitively coupled to the photodiode type light receiving element is disposed, and the bias voltage of this electrode is determined depending on the light receiving period. By making the period different from the signal charge readout period, an increase in the maximum amount of charge that can be handled in the light receiving element section can be effectively achieved, and an efficient imaging operation can be obtained.

In addition, it is possible to easily not only increase the maximum amount of charge that can be handled in the light-receiving element section, but also reduce it, so that it is provided with a function to adjust the amount of charge that can be handled, which is extremely convenient for use. Furthermore, accumulation of signal charges in the light receiving element section, readout of the signal charges from the light receiving element section via the readout gate section to the vertical transfer section, and transfer of the signal charges in the vertical transfer section are performed using a binary level clock signal. Since this can be performed using a bias voltage, there is also the advantage that the drive circuit system can be simplified.

It should be noted that the present invention is not limited to the scope of the above-described embodiments, and it goes without saying that various configurations may be adopted without departing from the scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a conceptual plan view showing an example of an interline transfer type CCD imaging device, FIGS. 2 and 3 are diagrams used to explain the configuration and operation of the imaging device shown in FIG. 1, and FIG. 1 is a conceptual plan view showing another example of the Innotarai/transfer type CCD imaging device, FIGS. S and 6 are diagrams used to explain the configuration and operation of the imaging device shown in FIG. μ, and FIG. A third cross-sectional view showing an example of a solid-state imaging device according to the present invention.
9 is a waveform diagram showing an example of the clock signal and bias voltage supplied to the solid-state imaging device shown in FIG. 7; FIG. 9 is a sectional view showing another example of the solid-state imaging device according to the present invention;
Figure O is a waveform diagram showing an example of the clock signal and bias voltage supplied to the solid-state imaging device shown in Figure 9;
The figure is a waveform diagram showing other levels of the clock signal and bias voltage supplied to the solid-state imaging device shown in FIG.
2(4) is a waveform diagram showing another example of the clock signal and bias voltage supplied to the solid-state imaging device shown in FIG. Vertical transfer section, Da and Da' are horizontal transfer sections, S and 5' are output sections, 6
and 6' is a read gate section, 7 is an overflow control gate section, g is an overflow drain/, 9
, lO and 1g are channel stoppers, ll and 1
1 / is a semiconductor substrate, 13 and 19 are transfer electrodes, lt
1 and 21 are overflow m-control gate electrodes, /j, λθ and 22 are channel/channel stopper electrodes, and /6 is a storage section. 3s 7WA Figure 1 Figure 12 - Procedural amendment 1930, month g day 1, case description 1982 patent application No. 103243-2, title of invention solid-state imaging device 3, person making amendment case Relationship with Patent Applicant 4, Agent 〒150 (1) In the specification, the phrase ``constant'' from page 7 to line g of @/ta is replaced with ``constant,'' meaning that the overflow control gate electrode and photodetector "There is no capacity between the two parts." It says "Cc' (V t' V, 0 +V a)
Correct to J. (3), page 17, line 2θ, “is constant” is replaced with “
It is corrected to ``with no capacitance between the channel stopper electrode and the light receiving element section''. rcc'・(V/-V tl +V 1))
Correct to J. that's all

Claims (1)

[Claims] A light receiving element section, a readout gate section formed adjacent to one end of the light receiving element section, a vertical transfer section formed adjacent to the readout gate section, a horizontal transfer section, and an output section. The signal charges obtained in the light receiving element section during the light receiving period are read out to the vertical transfer section via the readout gate section, and the signal charges are transferred to the other end of the light receiving element section. What is claimed is: 1. A solid-state imaging device, characterized in that an electrode capacitively coupled to a light-receiving element portion is disposed, and different bias voltages are supplied to the electrode during the light-receiving period and during the signal charge read-out period.