JPS586644A - Circuit control system of information processor - Google Patents

Abstract

PURPOSE:To reduce a quantity of the hardware in an information processor, and to reduce the size of the processor, by connecting plural terminal equipments to respective circuit control parts through a terminal switching part, and providing a common terminal control part which sends a switching signal to the switching part. CONSTITUTION:A CPU1 is connected to a bus line 3, and interruption lines IRQ from respective circuit control parts 111-11n and a timer part 9 are connected through wired OR. The control parts 111-11n convert parallel data from the CPU1 into series data to send out transmitted data TXD by a transmission clock from a clock selector 15; and received data EXD are converted into parallel data, which are sent out to the CPU1 through the interruption lines IRQ. Under the command of the CPU1, a terminal controller 12 applies clock selection signals A and B to the selector 15 and clock from a clock frequency division part 14 is sent out to the control parts 111-11n. Thus, the quantity of the hardware of the information processor is reduced, data are trasmitted at an optional speed among terminal equipments 41-42n, and the size of the device is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line control system in an information processing apparatus in which a plurality of terminal devices are connected to a central processing unit via a line control unit.

Conventionally, for example, ECR (Electronic Ca5h
The one shown in FIG. 1 is known as one of the information processing apparatuses that is used for applications such as registers and includes a plurality of terminal devices. The device in the figure includes a central processing unit 1, a memory 2, a path line 3, terminal devices 41+42+..., 41 line interfaces 5, line control units 61e62+..., 6n1 clocks having a keypad and a display, for example. It includes a generating section 7, a clock setting section 8, a timer section 9, and the like.

In the information processing apparatus shown in FIG. 1, the central processing unit 1 scans each line control unit 61+62; Performs processing related to the terminal device connected to the line control unit that has received the request.

In this case, the received data RXD from the terminal device is input to the central processing unit 1 or the memory 2 via the line interface 5, the line control unit, and the path line 3.
Transmission data TXD from the other terminals is conversely transmitted to the terminal device via the path line 3, the line control unit, and the line interface 5. Each line control section 61.

62,...+6n has the function of converting the serial format received data RXD from the terminal device into parallel format, and also converts the parallel format data from the central processing unit 1 etc. into serial format transmission data TXD. have Furthermore, the clock signal for each transmission speed generated by the clock generating section 7 is fixedly inputted to each line control section via a clock setting section which may be composed of, for example, a terminal board and a strap wire.

By the way, in the conventional example described above, one line control unit i is provided for one line terminal device, so when there are many terminal devices, there are as many line control units as there are terminal devices. This method requires a large amount of hardware, increases the amount of node hardware in the information processing device, and has the disadvantage that information processing cannot be miniaturized.Furthermore, the transmission processing frequency for each terminal is fixed.

In view of the problems in the conventional example described above, an object of the present invention is to connect a plurality of terminal devices to each line control unit via a terminal switching unit in a line control system for an information processing device equipped with a large number of terminal devices. Furthermore, based on the concept of providing a common terminal control section for sending switching signals to the terminal switching sections, the present invention aims to reduce the amount of hardware and make it possible to downsize the information processing device.

The present invention relates to a line control system for an information processing apparatus, in which a central processing unit is connected to the information processing apparatus, a line control unit connected to the central processing unit via a path line, and a terminal connected to each of the line control unit. A switching unit, a plurality of terminal devices connected to each of the terminal switching units via a transmission line, a transmission lock generation means, and one of the plurality of terminal devices in accordance with a command from the central processing unit. A terminal control unit is provided which sends a terminal switching signal to the terminal switching unit and sends a clock designation signal to the clock generation means, and the line control unit receives the signal from the terminal switching unit. Sends a signal to the path line, sends a transmission signal from the path line to the terminal switching unit, and inputs a line connection request interrupt signal to the central processing unit based on the input of the received signal or the transmission signal, and The device is characterized in that it performs data reception processing or data transmission processing in response to the line connection request interrupt signal.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 shows an example of an information processing device for implementing the method of the present invention. The information processing device in the figure is a central processing unit 1.
, memory 2, path line 3, terminal device 41.4□,...
14□. , line interface section 5, timer section 9, terminal switching section 101*102*...

10n1 line control unit 111 y 112 m”'e
111s terminal control section 12, clock generation section 13, clock frequency division section 14, and clock selector 15.

Central processing unit 1 and each line control unit 11111121...
. Connected to the line control unit. Further, the transmission lock necessary for each line control section is generated by the clock generation section 13 and the clock frequency division section 14, and is manually applied via the clock selector 15.

To explain in more detail the functions of each part shown in FIG. The interrupt line IRQ from the unit 9 is inputted after being wired-ORed, for example. Each line control unit 111' + 112 +...+ 11nU converts, for example, 8-bit parallel data from the central processing unit 1 into serial data and sends it out as transmission data TXD from the selector 15 with a specified transmission lock. It also converts the serially received data RXD into 8-bit parallel data, interrupts the central processing unit via the interrupt line IRQ, and sends the parallel data to the central processing unit 1 etc. via the path line 3. In response to a command from the central processing unit 1, the terminal control unit 12 inputs a clock selection signal of 2 bits in total to each I bit to the clock selector 15 via the clock selection lines A and B. One of the desired clocks is sent to the line control unit. It's a trench, end unspecified line c,, G2.

. . . selects one of two terminal devices connected to one terminal switching section by setting Gn to high or low level. Each terminal switching section 101', 102. ....

10n is the received data R from two terminal devices respectively.
,,R2,R3* R4,..., R, R as A2n-1
2n using the end r-1-, the end unspecified line GIFG2
,..., selected depending on the level of Gn, the receiving r-data RX
I) is output from ORDATE. In addition, the transmission data TXD is transferred to the unspecified line G1 + G2 r・
....

It is sent to the terminal device selected according to Gn. Note that the unspecified end line G l * G 2 1...I G,
is a low level, each odd-numbered terminal device 411
431...+42n-1 is selected, and when the level is high, even numbered terminal device 42+44*...+4
2n' is selected.

The line interface section 5 connects the transmission line connected to the terminal device and the terminal switching section using, for example, a photocoupler. The memory 2 includes a ROM (read only memory) that accommodates programs executed by the central processing unit 1 and a RAM (random access memory) that accommodates tables, data buffers, and program flags. The timer section 9 counts basic clocks of a constant period, generates an interrupt signal at predetermined time intervals, and interrupts the central processing unit.

The operation of the information processing apparatus configured as described above will be explained using the flowcharts of FIGS. 3 and 4.

In addition, in order to perform the following operations, it is stored in memory 2! Log system flags are provided in the same number as the number of line control units and set to "1" when the line control units are in operation.Line control unit operating flags are provided in the same number as the number of line control units and are connected to each line control unit. A terminal selection flag that is "l" when an odd-numbered terminal device is selected among the selected terminal devices, and "0" when an even-numbered terminal device is selected. When the number of devices is equal to the number of terminal devices and the terminal device is transmitting,
” is provided.

In order to check whether or not there is a line connection request from the terminal device to the central processing unit 1, the timer 9 outputs, for example, 6.6
A timer interrupt is generated every ms, and the third
The timer interrupt processing routine shown in the figure is activated. In this processing routine, for example, in the case of the line control unit (1), first, the line control unit operating flag is checked to determine whether or not the line control unit (1) is operating. As a result of this determination, if it is not in operation, it is determined whether the terminal device (1) is selected by the terminal selection flag, and if the terminal device (1) is not selected, the terminal control unit selects the terminal. The terminal selection signal G1 from 12 is turned off and the terminal selection flag 1 is set to "1". Also, if terminal (1) is selected, select terminal (2)≧
The terminal selection signal Gl is turned on and the terminal selection flag 1 is set to "0". Next, it is determined whether there is a line connection request from the terminal (1) or (2), that is, whether RXD is on. The terminal then turns on the TXD in response to the line connection request from the terminal. Next, set the operating flag of the line control unit (1), and set the line control unit (1) in the timer table provided for each line control unit to monitor the operating time of the line control unit (1). ) is initialized, for example, set to "0".Furthermore, if it is determined that the line control unit (1) is operating at the beginning of the timer interrupt processing routine, the timer table is incremented and then the timer is set to "0". It is determined whether the contents of the table are at a predetermined value, that is, whether a time-up has occurred.

As a result of this judgment, if the time is up, the line control unit (
1) and resets the operating flag of the line control unit (1).

The same process as described above is carried out by the remaining line control units (2) or n.
), and one timer interrupt process is completed.

By the way, after the terminal device makes a line connection request by turning on RXD, it receives a TXD on signal from the line control unit by the above-mentioned timer interrupt processing routine, and then sends data to the corresponding line control unit. do. When the line control section receives data of one character, for example, 8 bits, it issues an interrupt to the central processing unit 1, whereby the line control section interrupt processing shown in FIG. 4 is performed.

Contrary to the above, when the central processing unit 1 issues a line connection request to transmit data to a terminal, for example, in the case of the line control unit (1), the process is performed as follows. First, one of terminals (1) and (2) is selected as required, and the terminal selection signal G1 is set to O or 1. Next, TX
Turn D on and wait for the terminal to respond. The device is RXD
If it responds by turning on the central processing unit 1, data will be transmitted from the central processing unit 1 to the line control unit (1). Line control section (1
) interrupts the central processing unit 1 when it receives data for one character, and in this case as well, the line controller interrupt process shown in FIG. 4 is performed as described above.

Next, the line control section interrupt processing routine shown in the flowchart of FIG. 4 will be explained. In the interrupt processing routine, first, it is determined from which line control unit the interrupt has occurred, and
Set the operation parameters for the line control unit where the interrupt occurred, such as the address of the RAM work area. If the interrupt is not from any line control unit, it is assumed that there is an abnormal interrupt and abnormal interrupt processing is performed. When there is an interrupt from any of the line control units, after setting the above-mentioned operating parameters, it is determined whether the mode is reception mode or transmission mode based on the contents of the transmission flag. As a result of this determination, if the mode is reception mode, reception control processing for one character is performed. Next, it is determined whether the reception process for all the characters has been completed, and if so, it is determined whether it is necessary to switch to a transmission mode, for example, to transmit characters from the central processing unit.

If it is necessary to switch to the transmission mode, the transmission mode flag is set and toggled, and the process ends. Furthermore, if there is no need to switch to the transmission mode, the reception processing is terminated, the line control is reset, and the operating flag of the line control section is reset and set to end the processing. Furthermore, if it is determined that the line control unit in which the interrupt occurred is in the transmission mode after setting the operating parameter, the transmission control process for one character is performed. Next, check whether all characters have been sent.
The island is determined, and if completed, it is then determined whether it is necessary to switch to receive mode. If it is necessary to switch to the reception mode, the reception mode flag is set and the process ends. Furthermore, if there is no need to switch to the reception mode, the transmission is terminated by setting the line control section to one node and resetting the operating flag of the line control section, thereby terminating the process. The line controller interrupt routine as described above is carried out by the line controller issuing an interrupt every time one character, for example 8 bits, is transmitted or received.

In this way, in the information processing device described above, a plurality of terminal devices, for example, two terminal devices, are connected to one line control device via the terminal switching section, and the switching signal (Gs*
Gzs...tan) allows each terminal device to send and receive data (at the same time, the clock selection signal (A, B) from the terminal control unit can be used to transmit and receive data according to the transmission speed of each terminal device. The clock signal can be automatically set. Therefore, according to the present invention, the number of line control units is significantly reduced compared to the conventional type, so the amount of hardware of the information processing device is reduced and the size of the information processing device is reduced. is achieved, and data can be transferred between the terminal device and the terminal device at any transmission speed, so an information processing device with an extremely high degree of freedom can be constructed.

[Brief explanation of drawings]

Figure 1 is a professional circuit diagram showing a conventional information processing device.
FIG. 2 is a block circuit diagram showing an information processing device for implementing a method according to an embodiment of the present invention, and FIGS. 3 and 4 are diagrams for explaining the operation of the information processing device in FIG. This is a flowchart. l: central processing unit, 2: memory, 3: path line, 4114
2+..., 4n,...t 42n-1142n:
Terminal device, 5: Retrospective interface section, 61*62p・
.... 6n: line control section, 7: clock generation section, 8: clock setting section, 9: timer section, 101 * 102 s.
....

Claims (1)

[Claims] 1. In a line control system for an information processing device, the information processing device includes a central processing unit, a line control unit connected to the central processing unit via a path line, and a terminal switching unit connected to each of the line control units. , each of the plurality of terminal devices connected to each of the terminal switching units via the transmission line, the transmission lock generation means, and one of the plurality of terminal devices in accordance with a command from the central processing unit. A terminal control unit is provided which sends a terminal switching signal to the terminal switching unit to determine whether to connect to the line control unit and a clock designation signal to the clock generation means, and the line control unit receives the signal from the terminal switching unit. The central processing unit sends the signal to the path line, sends the transmission signal from the path line to the terminal switching unit, and inputs a line connection request interrupt signal to the central processing unit based on the input of the received signal or the transmission signal. 1. A line control system for an information processing apparatus, characterized in that a data processing apparatus performs data reception processing or data transmission processing in response to the line connection request interrupt signal.