JPS5866435A - Receiving circuit of transmitter and receiver - Google Patents

Receiving circuit of transmitter and receiver

Info

Publication number
JPS5866435A
JPS5866435A JP56164979A JP16497981A JPS5866435A JP S5866435 A JPS5866435 A JP S5866435A JP 56164979 A JP56164979 A JP 56164979A JP 16497981 A JP16497981 A JP 16497981A JP S5866435 A JPS5866435 A JP S5866435A
Authority
JP
Japan
Prior art keywords
circuit
section
power
receiving
certain period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56164979A
Other languages
Japanese (ja)
Other versions
JPS6347171B2 (en
Inventor
Kuniharu Tatezuki
邦治 竪月
Hironobu Inoue
博允 井上
Toshio Abiko
安彦 利夫
Masayuki Matsuo
昌行 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP56164979A priority Critical patent/JPS5866435A/en
Publication of JPS5866435A publication Critical patent/JPS5866435A/en
Publication of JPS6347171B2 publication Critical patent/JPS6347171B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/1607Supply circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transceivers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

PURPOSE:To save the electric power, by supplying the power only to a circuit having slow responsiveness of output in the entire range of a certain section and then supplying the power to the circuits excepting the above-mentioned ones in a short range of a certain section. CONSTITUTION:A power supply VA is applied to a demodulating circuit 6 containing a limiting amplifier 17 having the slow responsiveness of output through a transistor TR1 which is controlled by a long pulse. A power supply control circuit 21 delivers both a long pulse and a short pulse with a certain cycle. Then the VA is supplied to the circuit 6 in a period during which the TR1 is turned on in a section corresponding to a long pulse. At the same time, the TR1 is turned on for a certain period and in response to the short pulse in a short section at the latter part of a section which is prescribed by the long pulse. In this duration, a power supply VB is applied to the circuits other than the circuit 6.

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明はワイヤレスインター帛−:/に用いる送、受信
回路に濁するものである。 従来この種の送、受信回路としてはi!81図に示すよ
うな回路構成のものかあり九。即ち各局の送、受信器は
送信回路部(1)と、受信回路部(2)とから構成され
、送信回路部if)の呼出しスイッチ(3)を投入する
と、呼出し信号を搬送波に乗せた送信信号がアンテナI
4)より相手局に向けて発射されるようになっている。 待機中の送、受信器では受信回路部(2)により、前記
送信信号をフロントエンド(+1)を介して復調回路(
6)で喰波復調し、呼出し信号噴出回路(7)で該呼出
し信号を判別して報知回路(8)を駆動し、呼出し音を
スピーカ(9)より発鳴させるものである。通話中は復
調された音声信号を低周波増幅回路叫にて増幅して音声
を再生する。図中(11)は送信回路部11)に接続し
た送話用マイクであり、O四は受信用アンテナである。 ところで従来の送、受信器の受信回路は省電力化のため
に、受信待機中において第2図(c)に示すように受信
回路部(2)に一定周期tで一定区間pw電源を供給し
、その一定区間PWのみ受信可能とするもので、第2図
(a)のように相手局の送信回路部+11の呼出しスイ
ッチSWが投入されて、51S2図(ψ9よう
The present invention applies to transmitting and receiving circuits used in wireless interfaces. Conventionally, this type of transmitter/receiver circuit is i! Is it possible to have a circuit configuration as shown in Figure 81? That is, the transmitter and receiver of each station consists of a transmitter circuit section (1) and a receiver circuit section (2), and when the call switch (3) of the transmitter circuit section (if) is turned on, a call signal is transmitted on a carrier wave. The signal is antenna I
4) It is now more likely to be emitted towards the other station. In the standby transmitter/receiver, the receiver circuit unit (2) sends the transmitted signal to the demodulator circuit (+1) via the front end (+1).
6) demodulates the electromagnetic waves, a calling signal ejection circuit (7) discriminates the calling signal, drives a notification circuit (8), and makes a ringing tone emit from a speaker (9). During a call, the demodulated audio signal is amplified by a low frequency amplification circuit and the audio is reproduced. In the figure, (11) is a transmitting microphone connected to the transmitting circuit section 11), and O4 is a receiving antenna. By the way, in order to save power, the conventional transmitting and receiving circuits of receivers supply PW power for a certain period at a certain period t to the receiving circuit section (2) during reception standby as shown in FIG. 2(c). , only a certain period PW can be received, and as shown in Fig. 2(a), the call switch SW of the transmitting circuit section +11 of the other station is turned on, and the

【一定期
間呼出し信号が送信されると、その送信期間中に当る上
記受信区間PWで第2図(d)のように呼出し信号を検
出するようくなっている。 この場合受信回路部(2)に流れる平均回路電流■か、
一定区間PWを小さくするとよいのであるが、一定周期
tは呼出しスイッチ(3)が投入されてからの受信応答
性に関係し、省電力化のためとはいえ、大きくするには
限界があシ、tた一定区間PWは受信回路部(2)の出
力応答lC関係し、最も立ち上がりの遅いブロックより
決定される。 第3図は受信回路部(2)の具体的回路ブロック図を示
しており、受信回路部(2)は高周波増幅回路α躊、局
部発振回路(14+) 、 (14t)、周波数混合回
路(15,)、 (15り、バンドパスフィルター(t
ea)、(tag)シらなるフロントエンF i6)と
、りエッチインクアンプ(1カ、  90’H士△φの
移相回路(111、マルチプライヤ0偵、O−バスフィ
ルターよりPLL回路を構成した復調回路−6)と、低
周波増幅回路01と、呼出し信号検たように量大受信を
行なう場合、一定区間PWは回路中極めて出力応答性の
悪いり=ツテインジアンプaカに合わせて設定しなけれ
ばならず、他の回路の応答性がりエッチインクアンプ(
Lカの応答性に比して極めて曳くても電力消費を抑える
ことはりエッチインクアンプ(1?5の応答性によって
左右され、低電力消費化にも限界があった。 本発明は上述の問題点に鑑みて為されたもので、その目
的とするところは量大受信方式において、−屠畜電力化
を図った送、受信器の受信回路を提供するにある。 以下本発明を実施例によって説明する。第4図は受信回
路部(2)の回路ブロック図を示し、図中■幻は発振回
路等からなる電源供給フントロール回路であって、長パ
ルスを一定周期で同大的に出力するとともに、酋長パル
スの後部の期間に同期して短パルスを出力し、これらの
長、短パルスでトランジスタTft I Trtをオン
させ、これらのトランジスタTrs 、 Tryを通じ
て受信回路部(2)の電源Vム、vBt&:供給するよ
う例なっている。しかして受信回路部(2)のフロント
エンド(6)、低周波増幅回路−、呼出し信号検出回路
(1)、報知回路1)には短パルスで制御されるトラン
ジスタTftを通じて電源VBが、また出力応答性の遅
いり工テインジアンプOηを備えた復調回路I6)には
長パルスで制御されるトランジスタTr1を通じて電源
Vムが供給される。尚受信回路部(2)の構成はfJ3
図回路と同様な構成をなし、フロントエンド(6)、復
調回路+6)、低周波増幅回路−の各回路は通常の周知
回路から構成されており、その動作説明は省略する。 しかして受信待機中にあるとすると、電源供給コント0
−ル回路(21)では一定周期で長パルスと、短パルス
とが夫々出力して、長パルスに対応する区間トランジス
タTr+が第6図(C)で示すようにオンしてこのオン
期間中電源Vムが復調回路(6)に供給ンジスタTtt
が一定周期でオンして、このオン期間中に電源Vsが復
調回路I6】以外の回路に供給されることになる。従っ
て電源Vaの供給期間中受信回路部(2)は受信可能状
態となる。今965図(a)で示すように相手局の送信
回路部t1)の呼出しスイッチ(3)が投゛入され、同
図(b)のようにワンショットマルチバイブレータ等に
よって一定期間、呼出し信号が送信されると、受信局側
の受信回路部(2)では前述した受信可能状態の区間中
に受信されると、フロントエンドillと、復調回路V
$1と、呼出し信号検出回路(7)とを介して呼出し信
号を45図(−のように噴出し、呼出し信号検出回路(
7)よ抄の検出出力によって報知回路;・)を駆動し、
その報知出力でスピーカ(9)を駆動し呼出しがあるこ
とを報知するのである。々ころで前記送信信号の送信時
間は量大周期より大きく設定しており、送信信号を1回
送信すると、必らず受信側で受信検出できるようになっ
ている。 本発明はと述のように構成して、一定周期で操り屯され
る一定区間の全区間中出力応答性の遅いす三゛νテイン
クアンプを用いた復調回路にのみ電源が供給され、前記
一定区間の後部の短区間中に復調回路以外の回路にも電
源が供給される受信回路部を具備しであるので、応答性
のすぐれた大部分の受信回路部に不必要な電源供給を排
することができて、一層の省電力化が図れ、例えば小容
量の電池でも長期間使用で自るという効果を奏する
[When a paging signal is transmitted for a certain period of time, the paging signal is detected as shown in FIG. 2(d) in the receiving section PW during the transmission period. In this case, the average circuit current flowing through the receiving circuit section (2),
It would be better to make the fixed period PW smaller, but the fixed period t is related to the reception response after the call switch (3) is turned on, and there is a limit to making it larger, even if it is for power saving. , t and the fixed interval PW are related to the output response IC of the receiving circuit section (2) and are determined from the block whose rise is slowest. Figure 3 shows a concrete circuit block diagram of the receiving circuit section (2), which includes a high frequency amplifier circuit α, local oscillation circuits (14+), (14t), and a frequency mixing circuit (15 , ), (15, bandpass filter (t
ea), (tag) front engine F i6), etched ink amplifier (1 unit, 90'H △φ phase shift circuit (111, multiplier 0 unit, PLL circuit from O-bus filter) When using the constructed demodulation circuit-6) and the low-frequency amplifier circuit 01 to receive a large amount of call signal as detected, the output response in a certain period PW is extremely poor in the circuit. The etch ink amplifier (
Even if the response is extremely low compared to the response of the L amplifier, the ability to reduce power consumption depends on the response of the etch ink amplifier (1 to 5), and there is a limit to the reduction in power consumption. This invention was developed in view of the above, and its purpose is to provide a receiving circuit for a transmitting and receiving device that uses electricity for slaughtering in a large-volume receiving system. Fig. 4 shows a circuit block diagram of the receiving circuit section (2), and the phantom in the figure is a power supply control circuit consisting of an oscillation circuit, etc., which outputs long pulses at the same frequency at a constant period. At the same time, a short pulse is output in synchronization with the latter period of the chief pulse, and these long and short pulses turn on the transistor Tft I Trt, and the power supply V of the receiving circuit section (2) is supplied through these transistors Trs and Try. For example, the front end (6) of the reception circuit (2), the low frequency amplifier circuit, the calling signal detection circuit (1), and the notification circuit (1) are supplied with short pulses. The power supply VB is supplied through the controlled transistor Tft, and the power supply Vm is supplied through the long pulse controlled transistor Tr1 to the demodulation circuit I6) equipped with an engineering amplifier Oη having a slow output response. The configuration of the receiving circuit section (2) is fJ3.
It has the same configuration as the circuit shown in the figure, and the front end (6), demodulation circuit +6), and low frequency amplification circuit (-) are constructed from ordinary well-known circuits, and the explanation of their operation will be omitted. However, if it is waiting for reception, the power supply control is 0.
- In the loop circuit (21), a long pulse and a short pulse are outputted at a constant period, and the section transistor Tr+ corresponding to the long pulse is turned on as shown in FIG. 6(C), and the power is supplied during this on period. Vmu is supplied to the demodulation circuit (6) by the transistor Ttt.
is turned on at regular intervals, and during this on period, the power supply Vs is supplied to circuits other than the demodulation circuit I6. Therefore, during the supply period of the power source Va, the receiving circuit section (2) is in a receiving ready state. Now, as shown in Figure 965 (a), the ringing switch (3) of the transmitting circuit section t1) of the other station is turned on, and as shown in Figure 965 (b), a ringing signal is output for a certain period of time by a one-shot multivibrator, etc. When the signal is transmitted, the receiving circuit section (2) on the receiving station side sends the signal to the front end ill and the demodulating circuit V.
A calling signal is emitted as shown in Figure 45 (-) via $1 and the calling signal detection circuit (7).
7) Drive the notification circuit ;・) by the Yosho detection output,
The notification output drives the speaker (9) to notify that there is a call. In many cases, the transmission time of the transmission signal is set to be longer than the large cycle, so that once the transmission signal is transmitted, it can always be detected by the receiving side. The present invention is configured as described above, and power is supplied only to the demodulation circuit using the 3mm amplifier having a slow output response during the entire period of a certain period that is operated at a certain period. Since it is equipped with a receiving circuit section that supplies power to circuits other than the demodulation circuit during a short period at the end of a certain section, unnecessary power supply to most of the receiving circuit sections with excellent responsiveness is eliminated. This makes it possible to achieve further power savings, and for example, even small-capacity batteries can be used for long periods of time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は送、受信器の基本的回路1057図、第2図軸
)/−(d)は従来の受信方式の説明用タイムチャート
、第3図は従来の受信回路部の回路プO″Jり図、第4
図は本発明の一実施例の受信回路部の回路プ0・νり図
、第5図(a) −(む)は同上の動作説明用タイムチ
ャートであり、(1)は送信回路部、(2)は受信回路
部、(6)はフロシトエンド、(6)は復調回路、(1
(至)は低周波増幅回路、(1憤はり!・シティンジア
ンプである。 代理人 弁理士  石 1)長 七
Figure 1 is a basic circuit 1057 diagram of the transmitter and receiver, Figure 2 (axis)/-(d) is a time chart for explaining the conventional receiving system, and Figure 3 is the circuit diagram of the conventional receiving circuit section. J diagram, 4th
The figure is a circuit diagram of the receiving circuit section according to an embodiment of the present invention, FIGS. (2) is the receiving circuit section, (6) is the floating end, (6) is the demodulating circuit, (1
(to) is a low frequency amplification circuit, (1 outrage!) Shitinji amplifier. Agent Patent attorney Ishi 1) Choshichi

Claims (1)

【特許請求の範囲】[Claims] (1)  フロントエンド、復調回路、呼び出し信号検
出部、低周波増幅回路等からなる受信回路部に受信待機
中に一定周期で一定区間電源が供給されて、通話相手局
からの呼出し信号を闇X的に検出する受信方式の送、受
信器の受信回路において、一定周期で繰り返される一定
区間の全区間中出力応答性の遅いリミツテインクアンプ
を用いた復調回路にのみ電源が供給され、前記一定区間
の後部の短区間中に復調回路以外の回路にも電源が供給
される受信回路部を具備して成ることを特徴とする送、
受信器の受信回路。
(1) While waiting for reception, power is supplied to the reception circuit section consisting of the front end, demodulation circuit, calling signal detection section, low frequency amplification circuit, etc. for a certain period at a certain period, and the calling signal from the other party's station is ignored. In the transmitting and receiving circuit of the receiver, which uses a receiving system that detects the constant frequency, power is supplied only to the demodulation circuit using a limit amplifier with slow output response during the entire period of a certain period that is repeated at a certain period. A transmitter comprising a receiving circuit section to which power is supplied to circuits other than the demodulating circuit during a short section at the rear of the section,
Receiver receiving circuit.
JP56164979A 1981-10-15 1981-10-15 Receiving circuit of transmitter and receiver Granted JPS5866435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56164979A JPS5866435A (en) 1981-10-15 1981-10-15 Receiving circuit of transmitter and receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56164979A JPS5866435A (en) 1981-10-15 1981-10-15 Receiving circuit of transmitter and receiver

Publications (2)

Publication Number Publication Date
JPS5866435A true JPS5866435A (en) 1983-04-20
JPS6347171B2 JPS6347171B2 (en) 1988-09-20

Family

ID=15803518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56164979A Granted JPS5866435A (en) 1981-10-15 1981-10-15 Receiving circuit of transmitter and receiver

Country Status (1)

Country Link
JP (1) JPS5866435A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432673A (en) * 1991-10-14 1995-07-11 Tokyo Shibaura Electric Co Electronic apparatus with storing section and ejector for storing and ejecting card-like electronic member

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432673A (en) * 1991-10-14 1995-07-11 Tokyo Shibaura Electric Co Electronic apparatus with storing section and ejector for storing and ejecting card-like electronic member
US5455737A (en) * 1991-10-14 1995-10-03 Tokyo Shibaura Electric Co Electronic apparatus with storing section for storing detachable unit including groove holding strip-like function label

Also Published As

Publication number Publication date
JPS6347171B2 (en) 1988-09-20

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