JPH09153854A - Intermittent reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an operation tiem rate in a waiting state and to reduce power consumption by means of operating an intermittent reception device with a low speed clock in the waiting state. SOLUTION: An intermittent timer 32 clocking prescribed time TW which is previously set, based on the low speed clock signal generated from a low frequency oscillator 37 and a demodulation part 23 demodulating a transmission signal received in cooperation with the intermittent timer 32 are provided for the device. The intermittent timer 32 transmits a starting timing signal to the demodulation part 23 when the clocking of prescribed time TW is terminated. When reception is terminated, the demodulation part 23 transmits a clocking start timing signal to the intermittent timer 32. Thus, the re-starting of a high frequency reception part 22 and a high frequency oscillator 38 and the high speed operation of CPU 31 become unnecessary and power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermittent receiving apparatus for intermittently receiving only transmission data related to the own station from transmission data transmitted from a base station at regular intervals.

[0002]

2. Description of the Related Art Conventionally, when wireless communication is performed between a base station and a plurality of slave stations, data is transmitted from the base station to each slave station in a time division manner. There is known a time division wireless communication system configured to receive and demodulate only data transmitted with respect to.

When receiving data transmitted from a base station on the slave station side which constitutes such a time division wireless communication system, the following two receiving methods can be considered. First,
First, there is a method of keeping the radio wave in a state of being able to receive radio waves continuously while waiting for transmission data from the base station, and continuing to maintain data synchronization, frequency setting, etc., and second, transmission from the base station related to the local station. There is a method in which, after receiving the transmission data only for the time required to receive the data, the reception operation is temporarily stopped so that the transmission data unrelated to the own station is not received.

In this case, in the first method,
Since it is synchronized with the transmission data, it is possible to reliably receive the transmission data from the base station related to the own station. However, since the power of the slave station is always on, the battery power consumption increases and the battery power becomes effective in a system in which the slave station is driven by a battery, such as a mobile phone or a car phone. There is a problem that it cannot be used for.

Further, in the second method, since the power of the slave station is turned on only during the time when the transmission data from the base station related to the own station has to be received, the power consumption of the battery is higher than that in the first case. The consumption is reduced, and the battery power can be effectively used. Here, an example of trial calculation of power consumption by the above-mentioned first method and second method is shown in Table 1 below. In addition, each data of Table 1 shall be based on the following conditions. That is, the time rate that must be received is 10%, and the power consumption of the high frequency receiving circuit is 150 m.
W, the power consumption of the control circuit is 120 mW, and the power consumption of the high frequency oscillation circuit is 15 mW.

[0006]

[Table 1]

The operating time ratio by the second method is 1
The resynchronization time required for 0% time reception was 10%, and the time required for stabilizing the high-frequency receiving circuit and the high-frequency oscillation circuit prior to resynchronization was 10%. As is clear from Table 1, according to the second method, about 2 times the first method is used.
A low power consumption of 8% (73.5 / 285) can be realized.

On the other hand, the main control unit of the data carrier in the data carrier system is always in a standby state for signal radio waves by operating the data carrier at a low speed clock,
Japanese Patent Laid-Open No. 5-242311 proposes to control the clock to be switched at high speed when radio waves arrive from the antenna unit to reduce unnecessary power consumption and prolong battery operation time. Has been done.

[0009]

However, in the intermittent reception by the above-mentioned second method, the receiving operation must be stopped once, and the receiving frequency must be set and resynchronized before the time to receive. As a result, 28% of all operations are performed despite receiving operation for 10% of the time.
Power consumption is required. Therefore, about 18% (28%
There is a problem in that power consumption is wasted by -10%), which hinders low power consumption.

In the method proposed in Japanese Unexamined Patent Publication No. H5-242311, when the clock is switched at high speed, the input level of the radio wave coming from the antenna unit is detected to determine whether the data is correct or not. Since the determination operation is performed and the high-speed clock is used for this determination operation, there is a problem that power consumption is wasted as in the intermittent reception by the second method described above. Therefore, the present invention has been made in view of the above problems, and it is to reduce the operating time ratio in the standby state and to reduce the power consumption by operating with a low-speed clock in the standby state.

[0011]

In order to solve the above problems, the present invention measures a predetermined TW time which is set in advance from the time when the intermittent reception ends to the start of the next intermittent reception, and the predetermined TW time. When the time elapses, the next intermittent reception is started, so that the re-synchronization process before the reception is required becomes unnecessary, and the operating time ratio during standby can be reduced. Therefore, the average power consumption can be reduced. Further, since it is not necessary to perform resynchronization, it becomes possible to prevent a failure in standby reception.

Further, timer means 32 for counting time based on the low-speed clock signal generated by the low-frequency oscillating means 37.
Since the predetermined TW time set in advance is measured only by providing the above, the structure of this kind of intermittent receiving device becomes simple. Further, a power supply control means 35 for controlling ON / OFF of the power supply of the high frequency oscillating means 38 is provided, and the data processing means 31 is normally operated on the basis of the low speed clock signal generated by the low frequency oscillating means 37, so that the own station can operate. When the related transmission data is received, the power supply control means 35 turns on the power supply of the high frequency oscillating means 38 to switch to the high speed clock signal, and the data processing means 31 is operated by the high speed clock signal to perform the data processing of the reception data. Therefore, the power consumption during standby can be reduced.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a mobile phone in which the intermittent receiving device of the present invention is applied to a mobile phone device (mobile phone). The mobile phone receives the transmission data from the base station, which transmits time-divided predetermined data for each group in which a plurality of slave stations are grouped, and is connected to the base station and the base station as necessary. It is well known to transmit / receive data for a call to / from another telephone device via a telephone network.

In FIG. 1, the mobile phone comprises a communication device 10, a communication device 20, and a control device 30. The communication device 10 converts a voice signal input microphone 11, a received voice reproduction speaker 12, and an analog voice signal input from the microphone 11 into a digital voice signal and a digital voice signal transmitted from a callee. It is composed of a codec 13 which is converted into an analog audio signal and output to the speaker 12.

The communication device 20 includes a communication antenna 21 for performing wireless communication with a base station, and a communication antenna 2
1. A reception high frequency unit 22 that amplifies the reception signal received at 1 and converts it into a predetermined intermediate frequency signal, and a demodulation unit 2 that demodulates the reception signal converted at the reception high frequency unit 22 into an intermediate frequency signal.
3, a modulator 24 that modulates the transmission data into a predetermined transmission signal, a transmission high-frequency unit 25 that converts the transmission signal modulated by the modulator 24 into a communication high-frequency signal and amplifies it, and a communication antenna. The transmission / reception distributor 26 outputs the reception signal from the reception high frequency unit 22 to the reception high frequency unit 22 and outputs the high frequency signal from the transmission high frequency unit 25 to the communication antenna 21.

The control device 30 exchanges voice data for communication with the communication device 10 and the communication device 2
In order to control the reception and transmission operation of 0 and realize the function as a mobile phone, various controls exemplified in the following (1) to (4) are executed. In order to execute such various controls, a control unit 30a mainly composed of a CPU 31
(See FIG. 2), a high-frequency oscillator 37 that oscillates at a cycle shorter than the transmission cycle per bit of data at the base station, and outputs a high-speed clock corresponding to the oscillation cycle, and a transmission cycle at the base station side as well. A low-frequency oscillator 38 that oscillates in a longer cycle and outputs a low-speed clock corresponding to the oscillation cycle.

In order to demodulate the transmission data from the base station in the demodulation section 23, a reception timing signal synchronized with the data transmission cycle per bit on the base station side is generated and output to the demodulation section 23. Timing control.

The base station executes the generation of the reception timing signal and the output of the generated reception timing signal only during the transmission period in which the base station transmits data to the mobile phone.
Intermittent reception control for intermittently executing the reception operation on the communication device 20 side by stopping the generation and output of the reception timing signal during the other period.

A call signal for the mobile phone is detected from the received data demodulated by the demodulation unit 23, and the transmission data for transmitting a response signal to the base station side is output to the modulation unit 24 or illustrated. The transmission data for transmitting a calling signal for calling another telephone device to the base station side corresponding to the telephone number input from the operation unit is modulated by the modulation unit 23.
The line connection control for connecting the telephone line with another telephone device via the switch provided in the base station and the telephone line network by outputting to.

After the telephone line is connected, the digital voice signal of the call destination is extracted from the received data from the demodulation unit 23, and predetermined data is added to the digital voice signal for transmission input via the codec 13. And output to the modulation unit 24 to realize voice communication between the mobile phone and another telephone device.

Here, the power consumption of the oscillator increases in accordance with the oscillation frequency, and the oscillation frequency of the high frequency oscillator 37 used in this embodiment is 5 to 6 MHz, and the power consumption is about 15 mW. Is. The oscillation frequency of the low-frequency oscillator 38 used in this embodiment is several tens of KHz, and its power consumption is about 60 μ.
W. Therefore, the power consumption of the high frequency oscillator 37 is 250 times as large as that of the low frequency oscillator 38.

The high-speed clock output from the high-frequency oscillator 37 is mainly used for the received data processing operation of the CPU 31 (see FIG. 2) and the low-frequency oscillator 38.
The low-speed clock output from is mainly used for measuring the reception waiting time when the CPU 31 and the communication device 20 stop the reception operation due to the execution of the intermittent reception, the timing operation of the intermittent timer 32 described later, and the like.

Next, the control unit 3 which executes the above-mentioned intermittent reception.
0a will be described based on the block diagram shown in FIG. In FIG. 2, the control unit 30a includes a CPU 31 that executes received data processing and various arithmetic processing, an intermittent timer 32 that operates by a low-speed clock output from a low-frequency oscillator 37 to measure a predetermined time, and a high-frequency oscillator. High-speed clock output from 38 and low-frequency oscillator 37
The low-speed clock output from the
Clock switching circuit 3 for sending operation clock to U31
3, a PLL setting circuit 34 that sets a reception frequency from the received serial data, and a power supply control circuit 35 that controls on / off of the power supplies of the high frequency oscillator 38 and the reception high frequency unit 22.

The intermittent timer 32 measures a predetermined interrupt time TI set in advance from the time when the timer is started and a predetermined demodulator start time TW set in advance from the time when the timer is started, and each time TI and When the TW elapses, the interrupt timing signal and the demodulator activation timing signal are transmitted respectively.

Next, the operation of the control unit 30a which executes the above-mentioned intermittent reception will be described with reference to FIGS. 3 is a flowchart showing the operation of the control unit 30a of FIG. 2, and FIG. 4 is a timing chart showing the operation of the control unit 30a of FIG. The interrupt timing signal transmitted from the intermittent timer 32, which operates by the low-speed clock output from the low-frequency oscillator 37, when the preset interrupt time TI has elapsed since the timer was started is input to the CPU 31 (see point A in FIG. 4). As a result, the CPU 31 starts the intermittent reception start-up operation in step 50.

When the intermittent reception start-up operation is started, the CPU 31 sends a power-on signal to the power supply control circuit 35 in step 52. Then, the power supply control circuit 35 turns on the power of the high frequency oscillator 38 to operate the high frequency oscillator 38 (see point B in FIG. 4), and also turns on the power of the reception high frequency unit 22 to operate the reception high frequency unit 22. (Fig. 4
Point B)). Then, at step 54, the CP
U31 activates a built-in timer and determines whether or not a predetermined T ₁ time (for example, 5 msec) at which the operations of the receiving high-frequency unit 22 and the high-frequency oscillator 38 are stabilized has elapsed.
Here, when a predetermined time T ₁ (for example, 5 msec) has elapsed, it is determined to be “YES” in step 54 and the built-in timer is reset.

Next, at step 56, the CPU 31 sends a clock switching signal to the clock switching circuit 33. Then, the clock switching circuit 33 outputs the low-speed clock output from the low-frequency oscillator 37 to the high-frequency oscillator 3.
8 is switched to the high-speed clock output (see point C in FIG. 4), the high-speed clock is output to the CPU 31, and the CPU 3
1 is operated at high speed. When the CPU 31 operates at high speed with the high-speed clock output from the high-frequency oscillator 38, CP
In step 58, the U 31 sends the prestored data to the PLL setting circuit 34 and activates the built-in counter. Then, the PLL setting circuit 34 causes the PLL circuit (not shown) of the reception high frequency section 22 (see FIG. 1).
To the reception frequency (reception channel) (see point D in FIG. 4).

Then, the demodulator activation timing signal sent by the intermittent timer 32 operating by the low-speed clock output from the low frequency oscillator 37 when the preset demodulator activation time TW has elapsed since the timer was activated is step 60. When the signal is input to the demodulator 23 at, the demodulator 23 is activated (see point E in FIG. 4) and starts the demodulation operation of the reception data received by the reception high frequency section 22. At this time, the demodulator 23
Is set by the demodulator start time TW so that the sampling timing of the digital PLL for the bit recover (or also referred to as bit synchronization or data synchronization) is the first point (see the arrow in FIG. 6) of the eye pattern of the received signal. Therefore, resynchronization at the start of reception of the demodulator 23 becomes unnecessary. The intermittent timer 32 resets the timer time when it sends the demodulator activation timing signal.

Here, the reason why resynchronization is unnecessary will be described.
In FIG. 5, the base station sequentially time-divisionally transmits 3-bit data to a plurality of slave stations at a predetermined transmission cycle, and the receiver on the slave station side transmits 3-bit data to itself. Represents the case of receiving intermittently. When receiving a 1-bit digital modulated wave, as shown in FIG. 6, it is common to sample the most open point of the eye pattern of the received signal (see the arrow in FIG. 6) to perform reception with a low error rate. is there. Usually, at the point where the eye pattern of the received signal is the most open, an element such as a digital PLL is used to capture the sampling timing. However, since the point at which the eye pattern of the received signal opens at the start of reception is not known, it is necessary to take time to find this point. This operation is called resynchronization or synchronization acquisition.

In the present invention, as shown in FIG. 6, the intermittent timer 32 has a predetermined T after the end of reception (point F).
The intermittent timer 32 counts W time (this TW time is known in advance in the slave station and this TW time is preset in the intermittent timer 32) using the low-speed clock generated by the low frequency oscillator 37. Since the demodulator 23 is activated at the next reception start point (point E) so that sampling can be performed again at the most open point of the eye pattern, resynchronization is unnecessary.

When the demodulator 23 is activated in step 60, the demodulator 23 operates in step 62 in the reception high frequency section 22.
Demodulates the received data that is related to the local station. When the demodulation operation is completed, in step 64, the demodulator 23 sends a timer start timing signal to the intermittent timer 32. Then, the intermittent timer 32 resets the timer time T with the transmission of the demodulator activation timing signal.
W is set again (see point F in FIG. 4).

Then, when the built-in counter operated in step 58 reaches a preset predetermined count value, CP
In step 66, the U 31 sends a low speed clock switching signal to the clock switching circuit 33. Then, the clock switching circuit 33 switches the high-speed clock output from the high-frequency oscillator 38 to the low-speed clock output from the low-frequency oscillator 37, outputs the low-speed clock to the CPU 31, and operates the CPU 31 at low-speed (see G in FIG. 4). Point).
By operating the CPU 31 at a low speed, the power consumption of the CPU 31 is reduced.

Further, the CPU 31 uses the clock switching circuit 3
At the same time as sending the low-speed clock switching signal to 3,
In step 68, the U 31 sends a power off signal to the power control circuit 35. Then, the power supply control circuit 35 turns off the power supplies of the high-frequency oscillator 38 and the reception high-frequency unit 22 (see point G in FIG. 4) based on the power-off signal.
In this way, by turning off the power sources of the high frequency oscillator 38 and the reception high frequency unit 22 in the waiting state for reception, the high frequency oscillator 38 and the reception high frequency unit 22 are turned off.
Power consumption is reduced. In step 68, when the CPU 31 sends a power-off signal to the power supply control circuit 35, the process returns to step 50, and step 5 described above.
The process from 0 to step 68 is performed for a predetermined time (for example,
In the present embodiment, it is repeatedly executed every 720 msec.

The high frequency oscillating circuit 37 and the receiving high frequency section 22 operate based on the power-on signal sent in step 52, and stop based on the power-off signal sent in step 68. The time until is, for example, 20 to 60 msec. Also, the above step 5
The CPU 31 operates at high speed by the high-speed clock from the high-frequency oscillation circuit 37 based on the clock switching signal sent to the clock switching circuit 33 at 6, and the low-frequency oscillation circuit based on the clock switching signal sent at step 66. The time until the CPU 31 operates at a low speed by the low speed clock from 38 is, for example, 15 to 55 msec.

On the other hand, the high frequency oscillating circuit 37 and the receiving high frequency section 22 are stopped based on the power-off signal transmitted in the above step 68, and restarted based on the power-on signal transmitted again in the step 52. The time until it operates is 700 to 660 msec, for example. Further, the CPU 31 operates at a low speed with the low-speed clock from the low-frequency oscillation circuit 38 based on the clock switching signal transmitted in the above step 66, and the clock switching signal transmitted to the clock switching circuit 33 again in step 56. Based on the above, the time until the CPU 31 operates again at high speed by the high-speed clock from the high-frequency oscillation circuit 37 is, for example, 705 to 665 msec.

Therefore, the time during which the CPU 31 operates at high speed by the high speed clock from the high frequency oscillator 37 is
It is a time within about 10% of the time until the low speed operation is performed by the low speed clock from the low frequency oscillation circuit 38.
Since the operating time of the high frequency oscillating circuit 37 and the receiving high frequency unit 22 is within about 10%, the operating time ratio during standby can be remarkably reduced and the average power consumption can be remarkably reduced.

In addition, a predetermined TW time set in advance from the time when the intermittent reception ends to the time when the next intermittent reception starts is measured,
When the TW time elapses, the next intermittent reception is started, so that the re-synchronization process before the reception is required becomes unnecessary, and the operating time ratio during standby can be reduced. Therefore, the average power consumption can be reduced. Further, since it is not necessary to perform resynchronization, it becomes possible to prevent a failure in standby reception.

The present invention is not limited to the above-described embodiments, but can be implemented in various forms without departing from the gist of the present invention. For example, in the above-described embodiment, the example applied to the mobile phone has been described, but not limited to the mobile phone, any device that intermittently receives the transmission data regularly transmitted from the base station can be used. It can be applied to a device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a mobile phone in which the intermittent reception device of the present invention is applied to the mobile phone.

FIG. 2 is a block diagram showing details of a control unit in FIG.

FIG. 3 is a flowchart showing the operation of the control unit in FIG.

FIG. 4 is a timing chart showing the operation of the control unit shown in FIG.

FIG. 5 is a diagram showing an example of transmission data and intermittent reception.

FIG. 6 is a diagram showing an eye pattern of a received signal.

[Explanation of symbols]

10 ... communication device, 20 ... communication device, 21 ... antenna, 2
2 ... Reception high frequency section, 23 ... Demodulation section, 24 ... Modulation section, 25
... transmission high frequency section, 30 ... control device, 30a ... control section, 3
1 ... CPU (data processing means), 32 ... Intermittent timer (timer means), 33 ... Clock switching circuit (clock switching means), 34 ... PLL setting circuit, 35 ... Power supply control circuit (power supply control means), 37 ... Low frequency Oscillator (low frequency oscillation means), 38 ... High frequency oscillator (high frequency oscillation means)

Claims (3)

[Claims] 1. A discontinuous reception device that discontinuously receives only transmission data related to the local station from transmission data transmitted from a base station at regular intervals, and starts the next discontinuous reception after the end of the intermittent reception. The intermittent receiving apparatus is characterized in that the following intermittent reception is started when a predetermined time set up to is counted and when the predetermined time elapses. 2. An intermittent receiving device for intermittently receiving only transmission data related to the local station from transmission data transmitted from the base station at regular intervals, wherein the transmission data related to the local station is data. Data processing means for processing, and a high frequency that operates only when receiving transmission data related to the local station and oscillates at a cycle shorter than the transmission cycle of each 1-bit data of the transmission data to generate a high-speed clock signal. Oscillating means, low-frequency oscillating means for oscillating at a cycle longer than the transmission cycle to generate a low-speed clock signal, and a predetermined time preset based on the low-speed clock signal generated by the low-frequency oscillating means. A timer unit for counting time; and a demodulating unit for demodulating the transmission signal received in association with the timer unit, wherein the timer unit demodulates at the end of counting a predetermined time. The intermittent receiving apparatus is characterized in that the demodulating means sends a start timing signal to the means, and when the demodulating means finishes the reception, sends a timing start timing signal to the timer means. 3. The intermittent receiving device according to claim 2, wherein the power supply control means controls ON / OFF of the power supply of the high frequency oscillating means, the high speed clock signal generated by the high frequency oscillating means, and the low frequency. Clock switching means for selectively switching between the low-speed clock signal generated by the oscillating means, and when the transmission data related to the own station is received, the power supply control means turns on the power supply of the high frequency oscillating means. In addition, the intermittent receiving device is characterized in that the clock switching means switches to a high-speed clock signal so that the data processing means is operated by the high-speed clock signal.