JPS5866422A - Phase locked loop circuit - Google Patents

Phase locked loop circuit

Info

Publication number
JPS5866422A
JPS5866422A JP56165039A JP16503981A JPS5866422A JP S5866422 A JPS5866422 A JP S5866422A JP 56165039 A JP56165039 A JP 56165039A JP 16503981 A JP16503981 A JP 16503981A JP S5866422 A JPS5866422 A JP S5866422A
Authority
JP
Japan
Prior art keywords
circuit
phase
switch
locked loop
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56165039A
Other languages
Japanese (ja)
Inventor
Ryohei Oba
大庭 良平
Shuitsu Tsutsumi
堤 修逸
Koichi Ito
公一 伊藤
Tomoo Ishikawa
石川 倫男
Shoji Fuse
布施 庄司
Toru Kuge
久下 亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56165039A priority Critical patent/JPS5866422A/en
Publication of JPS5866422A publication Critical patent/JPS5866422A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/14Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/026Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using a memory for digitally storing correction values

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To decrease the power consumption of a phase lock loop circuit, by providing a switch which closes for a prescribed period when a change of the working conditions is detected for the main body of the loop circuit and then conducting an intermittent operation of the circuit main body. CONSTITUTION:A switch 7 which opens and closes the loop of the main body 6 of a PLL circuit by the control of a control circuit 8 is provided between a phase comparator 4 and a loop filter 5. A switch 11 is set between a frequency divider 3 and the comparator 4. When the switches 7 and 11 are closed, a voltage control oscillator 2 has oscillations with a locked frequency. Thus a switch 13 is changed over toward the filter 5, and the control voltage of the oscillator 2 is stored in a control circuit 8. The switches 7, 11 and 13 are opened after a prescribed period of time, and the loop of the main body 6 is set in a non-lock working state. However the oscillator 2 has its continuous operation. These switches are closed again when the value of a temperature detector 12 is changed from the stored value. Thus the oscillating frequency of the oscillator 2 is corrected.

Description

【発明の詳細な説明】 本発明は、消費電力の低減をはかったフェーズロックル
ープ回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked loop circuit that reduces power consumption.

近年、無線通信機等では無線周波数を多数の端末機どう
しで共用し、電波の利用率の向上をはかるため、フェー
ズロックループ回路(PLL回路)を使用した周波数シ
ンセサイザが多く使用されている。jJxaは従来のフ
ェーズロックループ回路を使用した周波数シンセサイザ
の基本構成な示すブロック図である。この周板数ノンセ
サイデは、基準発振器Jの出力と、電圧制御発振器2の
出力を分局器3で分周した出力との位相差を位相比較器
4で検出し、この検出出力をループフィルタ5を経て電
圧制御発振器2へ供給して所望の発振周波数を得るもの
である。
In recent years, frequency synthesizers using phase-locked loop circuits (PLL circuits) have been widely used in wireless communication devices and the like in order to share radio frequencies among a large number of terminals and improve the utilization rate of radio waves. jJxa is a block diagram showing the basic configuration of a frequency synthesizer using a conventional phase-locked loop circuit. This number of plates is determined by detecting the phase difference between the output of the reference oscillator J and the output obtained by dividing the output of the voltage controlled oscillator 2 by the divider 3 using the phase comparator 4, and passing this detected output through the loop filter 5. The signal is then supplied to the voltage controlled oscillator 2 to obtain a desired oscillation frequency.

しかしながら、このように従来のフエーズロツクループ
回路を使用したものにあっては、フェーズロックループ
回路を常に動作状態としているためフェーズロックルー
プ回路自体の消費電力が大きく、携帯用無線機等の低消
費電力機・器への適用が困難だった。
However, in devices using conventional phase-locked loop circuits, the power consumption of the phase-locked loop circuit itself is large because the phase-locked loop circuit is always in an operating state. It was difficult to apply it to power-consuming devices and devices.

本発明は上記事情に着目してなされたもので、その目的
とするところは、フエーズロツグループ回路本体を間欠
的に動作させて消費電力の低減をはかり、かつ上記間欠
動作を能率良く行ない得るようにしたフェーズロックル
ープ回路を提供することにある。
The present invention has been made in view of the above-mentioned circumstances, and its purpose is to reduce power consumption by operating the phase group circuit body intermittently, and to efficiently perform the above-mentioned intermittent operation. An object of the present invention is to provide a phase-locked loop circuit.

以下、本発明の一実施例を第2図を8照して゛  説明
する。なお前記第1図と同一部分には同一符号を付して
詳しい説明は省略する。WIz図において、プエーズロ
ッグループ回路本体6の位相比較器4とループフィルタ
5との間には第1のスイッチ7が介在設置しである。こ
の第1のスインf1は、後述する制御回路8の指示に従
ってフエーズロツグループ回路本体6のループン開閉す
るもので、ループの開成時にはデジタルタ5に接続する
。また電源10とフェーズロックループ回路本体6の分
局器3および位相比較器4との間の電源出力供給路中に
は、第2のスイッチ11が設けである。この第2のスイ
ッチllは、制御回路8の指示に従って上記分周器3お
よび位相比較器4への電源出力供給路をオフ・オンする
ものである。
Hereinafter, one embodiment of the present invention will be described with reference to FIG. Note that the same parts as in FIG. 1 are given the same reference numerals and detailed explanations will be omitted. In the WIz diagram, a first switch 7 is interposed between the phase comparator 4 and the loop filter 5 of the Puezlo loop circuit main body 6. The first swing f1 loops open and close the phase group circuit main body 6 according to instructions from a control circuit 8, which will be described later, and is connected to the digital converter 5 when the loop is opened. Further, a second switch 11 is provided in the power output supply path between the power supply 10 and the branching unit 3 and phase comparator 4 of the phase-locked loop circuit main body 6. This second switch 11 turns off and on the power output supply path to the frequency divider 3 and phase comparator 4 according to instructions from the control circuit 8.

ところで、本実施例のフェーズロックループ回路は、本
回路の動作条件の一要素である周囲温度を検出する温度
検出器12を有している。
By the way, the phase-locked loop circuit of this embodiment has a temperature detector 12 that detects the ambient temperature, which is one element of the operating conditions of this circuit.

そして、この温度検出器12の検出出力を、ループフィ
ルタ5の出力、つまり電圧制御発振器2の制御′電圧と
ともにI83のスイッチ13’j&よびアナログ・デジ
タル(A/D)変換器14をそれぞれ介して制御回路8
へ導入している。ここで第3のスイッチは、−御回路8
の指示に従って上記温度検出器12の検出出力と電圧制
御発振器2の制御電圧とを択一的に制御回路8へ導びく
ためのものである、制御回路8は、前記電圧制御発振器
2の制御電圧の記憶や温度検出器12による検出結果の
記憶および判定等の一連の制御動作を行なうものである
Then, the detection output of the temperature detector 12 is transmitted together with the output of the loop filter 5, that is, the control voltage of the voltage controlled oscillator 2, through the switch 13'j & of the I83 and the analog-to-digital (A/D) converter 14. Control circuit 8
It has been introduced to Here, the third switch is - control circuit 8
The control circuit 8 is for selectively guiding the detection output of the temperature detector 12 and the control voltage of the voltage-controlled oscillator 2 to the control circuit 8 in accordance with instructions from the control circuit 8. It performs a series of control operations such as storing and determining the results of detection by the temperature detector 12.

次に以上のように構成された回路の作用を説明する。先
ず制御回路8から各スイッチ7゜1181Bにスイッチ
閉成信号が出力されると、1oの出力が供給されて、フ
ェーズロックループ回路6はロック動作を開始する。こ
の結果、電圧制御発振器2は基準発振器lの出力周波数
と分周器3の分周数とによって定まる周波数で発振し、
この発振周波数にロックされる。一方前記制御回路8か
らのスイッチ閉成信号により第303スイツf1Bはル
ープフィルタ5側に切換わり、この結果上記ロック状態
における電圧制御発振器2の制御″磁圧がA/D変換器
14でデジタル信号に変換されたのち制御回路8に記憶
される。またこの記憶された制御電圧は、D/A変換器
9へ読出される。
Next, the operation of the circuit configured as above will be explained. First, when a switch close signal is output from the control circuit 8 to each switch 7° 1181B, the output of 1o is supplied, and the phase lock loop circuit 6 starts locking operation. As a result, the voltage controlled oscillator 2 oscillates at a frequency determined by the output frequency of the reference oscillator l and the frequency division number of the frequency divider 3,
It is locked to this oscillation frequency. On the other hand, the 303rd switch f1B is switched to the loop filter 5 side by the switch closing signal from the control circuit 8, and as a result, the control ``magnetic pressure'' of the voltage controlled oscillator 2 in the locked state is converted into a digital signal by the A/D converter 14. The stored control voltage is stored in the control circuit 8. The stored control voltage is also read out to the D/A converter 9.

そして、上記ロック動作に必要な時間が経過して制御回
路8から各スイッチ7m11g13にスイッチ開成信号
が出力されると、分局器3および位相比較器4への電源
供給が断となるとともに第1のスイッチ7が位相比較器
4側がらD/A変換器9側へ切換わってフェーズロック
ループ回路本体6のループは非ロツク動作状態と訛。
Then, when the time required for the above-mentioned locking operation has elapsed and a switch opening signal is output from the control circuit 8 to each switch 7m11g13, the power supply to the branching unit 3 and the phase comparator 4 is cut off, and the first The switch 7 switches from the phase comparator 4 side to the D/A converter 9 side, and the loop of the phase-locked loop circuit main body 6 is in a non-locking operating state.

なる。しかるにこのとき、制御回路8から続出゛され、
D/A変換器9で変換された制御電圧がループフィルタ
5を介して電圧制御発振器2へ供給されるため、電圧制
御発振器2の発振動作は継続してなされる。一方、前記
制御回路8からのスイッチ開成信号により第3のスイッ
チ13がループフィルタ5側から温度検出器12側へ切
換わると、この切換直後の温度検出器12の検出値がA
/De換器14を経て制御回路8に導入され、記憶され
る。そして、その後温度検出器12で得られた検出値は
、順次制御回路8に導入される。
Become. However, at this time, the control circuit 8 outputs one after another,
Since the control voltage converted by the D/A converter 9 is supplied to the voltage controlled oscillator 2 via the loop filter 5, the oscillation operation of the voltage controlled oscillator 2 continues. On the other hand, when the third switch 13 is switched from the loop filter 5 side to the temperature detector 12 side by the switch opening signal from the control circuit 8, the detected value of the temperature detector 12 immediately after this switching is A.
The signal is introduced into the control circuit 8 via the /De converter 14 and stored. Then, the detected values obtained by the temperature detector 12 are sequentially introduced into the control circuit 8.

さて、この状態で、例えば室温の上昇により、温度検出
器12で得られた検出値が前記ロック動作直後に記憶し
た値に対して所定量以上変化すると、制御回路8はこれ
を検出した時点で各スイッチ1alleJBに対しスイ
ッチ開成信号を出力する。この結果、フェーズロックル
ープ回路本体6のループが閉成され、かつ分周器38よ
び位相比較器4に電源10の出力が供給されて、フェー
ズロックループ回路本体6はロック動作を行なう。これ
により電圧制御発振器2の発振周波数の温度変動に対す
る修正がなされる。またこの修正後の電圧制御発振器2
の制御電圧は、修正前の値に代わって制御回路8に記憶
され1次のループ開成時における電圧制御発振器2の発
振動作用に供される。
Now, in this state, if the detected value obtained by the temperature detector 12 changes by a predetermined amount or more from the value stored immediately after the locking operation due to, for example, a rise in the room temperature, the control circuit 8 detects this. A switch open signal is output to each switch 1alleJB. As a result, the loop of the phase-locked loop circuit main body 6 is closed, and the output of the power supply 10 is supplied to the frequency divider 38 and the phase comparator 4, so that the phase-locked loop circuit main body 6 performs a locking operation. As a result, the oscillation frequency of the voltage controlled oscillator 2 is corrected for temperature fluctuations. Also, the voltage controlled oscillator 2 after this modification
The control voltage is stored in the control circuit 8 in place of the value before correction and is used for the oscillation action of the voltage controlled oscillator 2 when the primary loop is opened.

と そしてロック動作鉱終了すると、制御回路8から各スイ
ッチ7m11m1:Iにスイッチ開成信号がそれぞれ出
力されて、ループは開成状態となり、この間前述したよ
うに温度監視がなされる。
When the lock operation is completed, a switch open signal is output from the control circuit 8 to each switch 7m11m1:I, and the loop becomes open, and during this time the temperature is monitored as described above.

ここで、上記ロック動作に要する時間は約1緩慢で所定
量変化する時間は長いので、上記間欠ロック動作により
低減される消費電力は非常に大きなものとなる。
Here, since the time required for the above-mentioned locking operation is about 1 slow and the time for changing the predetermined amount is long, the power consumption reduced by the above-mentioned intermittent locking operation becomes very large.

このように、本実施例の回路によれば、フェーズロック
ループ回路本体6を間欠ロック動作させることがでへる
ので、回路の消費電力を大幅に低減することができる。
In this way, according to the circuit of the present embodiment, the phase-locked loop circuit main body 6 can be locked intermittently, so that the power consumption of the circuit can be significantly reduced.

したがって、例えば電池を使用した携帯用無線機等への
適用も可能となり、携帯用無線機の小を化や性能向上を
はかることができる。また本実施例では、回路の動作条
件の重要な要素である周囲温度を監視し、この周囲温度
が許容量を超える変化を示したときにロック動作を一行
なわしめるようにしているので、必要なときにロック動
作を行なうことができ、タイマ等によりロック動作の周
期を固定化した手法に比べて、能率良く、シかも確実な
間欠ロック動作を行なうことができる。さらに本実施例
では、電圧制御発振器2の制御電圧をデジタル信号に変
換してメモリに記憶するようにしているので、記憶中の
制御電圧値に変動が生じることがない。したがって、記
憶手段としてコンデンサを用いた場合に比べて精度の高
い間欠ロック動作を行なわせることができる。
Therefore, it is possible to apply the present invention to, for example, a portable radio device using a battery, and it is possible to downsize the portable radio device and improve its performance. In addition, in this embodiment, the ambient temperature, which is an important element of the circuit operating conditions, is monitored, and when the ambient temperature shows a change exceeding the allowable amount, a lock operation is performed. The intermittent locking operation can be performed more efficiently and reliably than a method in which the cycle of the locking operation is fixed using a timer or the like. Furthermore, in this embodiment, since the control voltage of the voltage controlled oscillator 2 is converted into a digital signal and stored in the memory, there is no fluctuation in the stored control voltage value. Therefore, intermittent locking operation can be performed with higher precision than when a capacitor is used as the storage means.

なお1本発明は上記実施例に限定されるものではない0
例えば、動作条件として周囲温度の変化以外に、電源l
O電圧の変動を監視し、その結果に応じてロック動作を
行なうようにしてもよい、またこれら周囲温度による制
御と電源電圧による制御とは並行して行なってもよい。
Note that the present invention is not limited to the above embodiments.
For example, in addition to changes in ambient temperature as operating conditions,
Fluctuations in the O voltage may be monitored and a locking operation may be performed in accordance with the monitoring results.Also, the control based on the ambient temperature and the control based on the power supply voltage may be performed in parallel.

さらに前記実施例では、分局器3と位相比較器4とに対
する電源供給を断するようにしたが、その他に基準発振
器等の外股回路の電源を断するようにしてもよく、また
ループフィルタ6がアクティブフィルタより構成されて
いる場合シーは、このループフィルタ6への電源供給を
断とするようにしてもよい、要するに、ループを構成す
る各回路のうち電圧制御発振器を除く各回路の少なくと
も1つの回路への電源供給を断に1丁ればよい。またロ
ック動作から不動作状態への移行は、位相比較器から発
生されるロック完了信号を検出して行なってもよく、位
相比較器にロック完了信号発生機能がない場合には、タ
イマにより予め時間も設定しておいてもよい。
Further, in the above embodiment, the power supply to the branching unit 3 and the phase comparator 4 is cut off, but it is also possible to cut off the power supply to an external circuit such as a reference oscillator, and the loop filter 6 may also be cut off. In the case where the loop filter 6 is constituted by an active filter, the power supply to the loop filter 6 may be cut off.In short, at least one of the circuits constituting the loop except for the voltage controlled oscillator All you need to do is cut off the power supply to one circuit. In addition, the transition from lock operation to non-operation state may be performed by detecting a lock completion signal generated from a phase comparator.If the phase comparator does not have a lock completion signal generation function, a timer is used to set the lock completion signal in advance. may also be set.

その他、各スイッチra11.1Bの構成やフエーズロ
ツグループ回路の適用対象、間欠ロック動作の制御手順
等についても、本発明の要旨を逸脱しない範囲で種々変
形して実施できる。
In addition, the configuration of each switch ra11.1B, the application of the phase lock group circuit, the control procedure for intermittent locking operation, etc. can be modified in various ways without departing from the gist of the present invention.

以上詳述したように、フェーズロックループ回路本体の
ループgよび回路への電源供給をそれぞれオン、オフす
る第1および第2のスイッチを設けるとともに、電圧制
御発振器の制御電圧を記憶する記憶回路ヶ設け、かつ回
路の動作条件を監視してこの監視結果に応じて前記第1
Sよび第2の各スイッチを閉状態にするようにした本発
明によれば、フェーズロックループ回路本体を間欠的に
動作させて消費電力の低減をはかり、かつ上記間欠動作
を能率良く行ない得るフエーズロツグループ回路を提供
することができる。
As described in detail above, the first and second switches are provided to turn on and off the power supply to the loop g of the phase-locked loop circuit and the circuit, respectively, and a memory circuit is provided to store the control voltage of the voltage controlled oscillator. and monitoring the operating conditions of the circuit, and depending on the monitoring results, the first
According to the present invention, in which the S and second switches are closed, the main body of the phase-locked loop circuit is operated intermittently to reduce power consumption, and the intermittent operation can be efficiently performed. EZROTS group circuits can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフエーズロツグループ回路を使用した周
波数シンセサイザの基本構成を示すブロック図、第2図
は本発明の一実施例におけるフエーズロツグループ回路
を使用した周波数シンセサイザの回路ブロック図である
。 l・・・基準発振器、2・・・電圧制御発振器(vc”
o)3・・・分周器、4・・・位相比較器、5−・ルー
プフィルタ、6・・・フエーズロツグループ回路本体、
7・・・第1のスイッチ、8・・・制御回路、9・・・
D/A変換器、10・・・電源、71−第2のスイッチ
、12・・・温度検出器、13−第3のスイッチ、14
・・・A/D変換器。 出願人代理人 弁理士 鈴 江 武 彦第1頁の続き ■発 明 者 久下亨 日野市旭が丘3丁目1番地の1 東京芝浦電気株式会社日野工場
FIG. 1 is a block diagram showing the basic configuration of a frequency synthesizer using a conventional phase group circuit, and FIG. 2 is a circuit block diagram of a frequency synthesizer using a phase group circuit according to an embodiment of the present invention. be. l... Reference oscillator, 2... Voltage controlled oscillator (vc"
o) 3... Frequency divider, 4... Phase comparator, 5-... Loop filter, 6... Phase group circuit body,
7... First switch, 8... Control circuit, 9...
D/A converter, 10 - power supply, 71 - second switch, 12 - temperature detector, 13 - third switch, 14
...A/D converter. Applicant's representative Patent attorney Takehiko Suzue Continued from page 1 ■Inventor Toru Kushita 3-1-1 Asahigaoka, Hino City Hino Factory, Tokyo Shibaura Electric Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] フ:c −スoツクループ回路本体と、このフェーズロ
ックループ回路本体のループを開閉する第1のスイッチ
と、フェーズロックループ回路本体の電圧制御発振器を
除いた各回路のうち少なくとも1つの回路の電源をオフ
、オンする第2のスイッチと、前記フェーズロックルー
プ回路本体のループ開成時に電圧制御発振器の制御電圧
を紀憶しこの記憶した制御電圧をフェーズロックループ
回路本体のループ開成時に電圧制御発振器に供給して発
振動作を継続せしめる記憶回路と、フェーズロックルー
プ回路本体のループ開成時にフェーズロックループ回路
本体の動作条件を監視しその変動を検出する監視回路と
、この監視回路によりフェーズロックループ回路本体の
動作条件の変動が検出されたとき前記第1および第2の
各スイッチを所定時間だけ開状態から閉状態にしてフェ
ーズロックループ回路本体にロック動作を行なわせるロ
ック制御回路とを具備したことt特徴とするフェーズロ
ックループ回路。
F: c-socket A power source for at least one circuit out of the loop circuit body, the first switch that opens and closes the loop of this phase-locked loop circuit body, and each circuit other than the voltage-controlled oscillator of the phase-locked loop circuit body. a second switch for turning off and on the phase-locked loop circuit, and a second switch for storing the control voltage of the voltage-controlled oscillator when the loop of the phase-locked loop circuit main body is opened, and transmitting the stored control voltage to the voltage-controlled oscillator when the loop of the phase-locked loop circuit main body is opened. A memory circuit that supplies power to continue the oscillation operation, a monitoring circuit that monitors the operating conditions of the phase-locked loop circuit body and detects fluctuations when the loop of the phase-locked loop circuit body is opened, and this monitoring circuit and a lock control circuit that turns each of the first and second switches from an open state to a closed state for a predetermined period of time to perform a locking operation on the phase lock loop circuit body when a change in the operating condition is detected. Features a phase-locked loop circuit.
JP56165039A 1981-10-16 1981-10-16 Phase locked loop circuit Pending JPS5866422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56165039A JPS5866422A (en) 1981-10-16 1981-10-16 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56165039A JPS5866422A (en) 1981-10-16 1981-10-16 Phase locked loop circuit

Publications (1)

Publication Number Publication Date
JPS5866422A true JPS5866422A (en) 1983-04-20

Family

ID=15804667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56165039A Pending JPS5866422A (en) 1981-10-16 1981-10-16 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPS5866422A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0299674A2 (en) * 1987-07-11 1989-01-18 Plessey Overseas Limited Improvements in or relating to frequency synthesisers
JPH07162274A (en) * 1993-12-06 1995-06-23 Nec Corp Integrated circuit for receiver
JP2009182918A (en) * 2008-02-01 2009-08-13 Toyota Industries Corp Voltage controlled oscillation circuit
US7616066B2 (en) 2005-07-13 2009-11-10 Futaba Corporation Oscillation device and controlling method therefor
JP2011199481A (en) * 2010-03-18 2011-10-06 Renesas Electronics Corp Clock system
JP2014155004A (en) * 2013-02-07 2014-08-25 Furukawa Electric Co Ltd:The Oscillation circuit and method of controlling the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0299674A2 (en) * 1987-07-11 1989-01-18 Plessey Overseas Limited Improvements in or relating to frequency synthesisers
JPH07162274A (en) * 1993-12-06 1995-06-23 Nec Corp Integrated circuit for receiver
US7616066B2 (en) 2005-07-13 2009-11-10 Futaba Corporation Oscillation device and controlling method therefor
JP2009182918A (en) * 2008-02-01 2009-08-13 Toyota Industries Corp Voltage controlled oscillation circuit
JP2011199481A (en) * 2010-03-18 2011-10-06 Renesas Electronics Corp Clock system
JP2014155004A (en) * 2013-02-07 2014-08-25 Furukawa Electric Co Ltd:The Oscillation circuit and method of controlling the same

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