JPS5866336A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPS5866336A
JPS5866336A JP16342281A JP16342281A JPS5866336A JP S5866336 A JPS5866336 A JP S5866336A JP 16342281 A JP16342281 A JP 16342281A JP 16342281 A JP16342281 A JP 16342281A JP S5866336 A JPS5866336 A JP S5866336A
Authority
JP
Japan
Prior art keywords
diffusion
pocl3
emitter
produced
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16342281A
Other languages
Japanese (ja)
Inventor
Kimio Nakada
中田 喜美男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16342281A priority Critical patent/JPS5866336A/en
Publication of JPS5866336A publication Critical patent/JPS5866336A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To reduce life of carriers at forming emitter region using POCl3, by a method wherein diffusion temperature and gas concentration are raised and crystal distorsion is produced at the emitter region. CONSTITUTION:Si substrate 3 is heated 1 to about 1,100 deg.C and POCl3 together with N2 and O2 (for preventing POCl3 from etching by thermal cracking gas) is flowed and emitter diffusion is performed. Flow rate of POCl3:N2:O2=1:2:1 is supplied and the treating of about 30min is performed, and P having smaller atomic radius than that of Si is forcedly injected at high concentration into the emitter and larger stress is produced and strain is produced in Si substrate and the storage time is decreased and switching property is improved. Strain state can be freely selected by controlling the temperature, gas flow rate and diffusion time. In this constitution, since conventional metal diffusion is not used the limitation for crack by contamination of SiO2 is obviated and switching property can be improved.

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法にかかり、特にスイッ
チング特性が要求されるNPN )ランジスタの製造方
法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing an NPN transistor which requires good switching characteristics.

従来、スイッチング特性が要求されるNPN )ランジ
スタでメサ型やブレーナ型外どの拡散型のものでは、高
周波特性が良好でかつ、いかに1!(トランジション周
波数)が高くてもスイッチングに用いたときのスイッチ
ング速度が速いとは限らない。スイッチング特性のスト
レージ時間(tsL菖)を小さくするには半導体のキャ
リヤのライフタイムを短かくすることが必要で、これに
は−毅にキャリアのライフタイムを短かくするような金
属の金、銅、鉄、ニッケル(前記のうち金が最も多く用
いられている)、いわゆるライフタイムキラーをトラン
ジスタのコレクタ側から拡散導入している。
Conventionally, diffusion type transistors such as mesa type and Brenna type (NPN) transistors, which require good switching characteristics, have good high frequency characteristics and are very good! Even if the transition frequency is high, the switching speed when used for switching is not necessarily high. In order to reduce the storage time (tsL) of switching characteristics, it is necessary to shorten the lifetime of carriers in semiconductors. , iron, nickel (of the above, gold is most commonly used), so-called lifetime killers, are introduced by diffusion from the collector side of the transistor.

しかし、上記の方法では表面に被着された酸化シリコン
膜中にも金が拡散されてIC110e ■CIO等のリ
ーク電流が増大し、て高信頼性が得られないことや、金
拡散のばらつきによりストレージ時間を精度よくコント
ロールする事が難かしい欠点がある。上記の他に半導体
基板の活性領域の1層を厚くする手段、ベース(P層)
の高濃度化またはベース幅(Wi+)を狭くするなどの
手段もあるが他に要求される特性面からの制約による限
度があるので適しない。
However, with the above method, gold is also diffused into the silicon oxide film deposited on the surface, increasing the leakage current of IC110e CIO, etc., making it impossible to obtain high reliability, and due to variations in gold diffusion. The drawback is that it is difficult to precisely control storage time. In addition to the above, means for thickening one layer of the active region of a semiconductor substrate, base (P layer)
Although there are measures such as increasing the concentration of the material or narrowing the base width (Wi+), these methods are not suitable because they are limited by constraints from other required characteristics.

この発明は錠上の従来の欠点を改良するためになされた
もので、スイッチング特性が要求される半導体装置の製
造におけるエミッタ拡散を改良しシリコン結晶内に歪を
生じさせライフタイムの値化をはかるようにしたことを
特徴とするものである。
This invention was made to improve the drawbacks of conventional locks.It improves emitter diffusion in the manufacture of semiconductor devices that require switching characteristics, creates strain in silicon crystals, and measures lifetime values. It is characterized by the following.

以下にこの発明を1実施例につき詳細に゛説明する。第
1図は1実施例に用いられる不純物拡散装置を示し、加
熱炉(1)中に挿入された石英の反応容器(2)にシリ
コン基板(3)、(3’)−・・を装入し、反応容器の
一端から反応気体を導入し内部を所定の雰fllにする
ための反応気体導入口(4m)、(4b)・−が設けら
れており、また、この反応容器の他端は開放端になって
いる。錠上の装置により、シリコン基板を1050℃〜
1100℃に加熱し、反応気体導入口からエミッタ拡散
のためのオキシ塩化リン(POCIs) tキャリヤガ
スのN!ガス、オキシ塩化リンの分解生成ガスの塩素系
ガス(PCI!i 、 Cjz)  によるエツチング
防止の偽ガスとともに流入してエミッタ拡散を施す。こ
のとき、−例としてオキシ塩化リン、Nへの流量の比を
1:2:1にして15−30分間で、シリコン原子半径
をこえたソース(リン原子社シリコン原子に比べて小さ
い)が強制点にエミッタ部に注入されて大きなストレス
を生じ(psが 15〜勺以下ではディスロケーション
が発生し)シリコン基板に歪が発生し、このためτが低
下しストレージ時間が小Ke、り、スイッチング特性が
向上する。、仁の歪の状態は温度、ガスの流量、拡散時
間のコントロールによって、第2図(a)〜(d) K
示すように任意に選ぶことができる。すなわち、各図は
いずれもエミッタ部にジルトルエツチングを施してシリ
コン中のひずみを検出したものでシリコンの結晶方向が
示されている。また−1図(C) 、 (d)は相当に
歪の大きい場合で、斜線はいずれも凹みを生じているこ
とを示すものであシ、写真では黒く写っている。上記(
a)〜(d)のような歪を発生させるには夫々次のよう
に行なった。
The present invention will be described in detail below with respect to one embodiment. Figure 1 shows an impurity diffusion device used in a first embodiment, in which silicon substrates (3), (3'), etc. are charged into a quartz reaction vessel (2) inserted into a heating furnace (1). A reaction gas inlet (4m), (4b), etc. is provided for introducing the reaction gas from one end of the reaction container to create a predetermined atmosphere inside the reaction container, and the other end of the reaction container is It has an open end. The device on the lock heats the silicon substrate to 1050℃~
Heating to 1100°C, phosphorus oxychloride (POCIs) t carrier gas N! for emitter diffusion from the reaction gas inlet! A chlorine-based gas (PCI!i, Cjz), which is a gas produced by decomposition of phosphorus oxychloride, flows in together with a pseudo gas to prevent etching and performs emitter diffusion. At this time, for example, with the ratio of the flow rates to phosphorus oxychloride and N to 1:2:1, for 15 to 30 minutes, the source exceeding the radius of the silicon atom (smaller than the silicon atom) is forced. This causes a large stress (dislocation occurs when ps is less than 15 to 15) and causes distortion in the silicon substrate, resulting in a decrease in τ, a decrease in storage time, and a decrease in switching characteristics. will improve. , the state of strain in the nickel can be determined by controlling the temperature, gas flow rate, and diffusion time as shown in Figures 2 (a) to (d).
You can choose arbitrarily as shown. That is, each of the figures shows the strain in silicon detected by subjecting the emitter section to dilat etching, and the crystal orientation of the silicon is shown. Furthermore, Figures 1 (C) and (d) show cases where the distortion is considerably large, and the diagonal lines indicate that a dent has occurred, which is shown in black in the photograph. the above(
In order to generate the distortions shown in a) to (d), the following steps were carried out.

第2図(&) 加熱温度(’C)  105G 雰囲気ガスの種類と流量(L/分)、時間(分)へ  
 1 −1 −1 03   05−0.5−05 POCIs O−(15−0 時間(分)5−15−5 第2図(ロ) 加熱温度(℃)1o5゜ 雰囲気ガスの種類と流量(L/分)、時間(9)鳥  
  1 −1 −1 へ    05− O5−05 POCIs   O−05−0 時間(分)5−30−5 82図(e) 加熱温度CC)  1100 雰囲気ガスの種類と流量(L/分)、時−間@)Nx 
    1 −1 −1 へ    05−05−05 POCIs   O−05−0 時間(分)5−15−5 第2図(d) 加熱温度(℃)  1100 雰囲気ガスの種類と流量(L/分)、時間@)Nx  
   1 −1 −1 020S   05  05 POClm   6  0.5  0 時間(分) 5−30−5 この発明によれば、エミッタ領−形廖によってシリコン
結晶中に歪を生じさせて不イッテング特性を改善するも
ので、従来のようにライフタイムを短かくする金属を拡
散することがないため、酸化シリコン膜が汚染されて生
ずるリーク電流に対する制限が不要で、任意にコントロ
ール−できるという顕著な効果がある。
Figure 2 (&) Heating temperature ('C) 105G Type of atmospheric gas, flow rate (L/min), time (min)
1 -1 -1 03 05-0.5-05 POCIs O- (15-0 Time (minutes) 5-15-5 Figure 2 (B) Heating temperature (°C) 1o5° Type and flow rate of atmospheric gas (L / minute), time (9) bird
To 1 -1 -1 05- O5-05 POCIs O-05-0 Time (minutes) 5-30-5 Figure 82 (e) Heating temperature CC) 1100 Type and flow rate of atmospheric gas (L/min), hour- Between @)Nx
To 1 -1 -1 05-05-05 POCIs O-05-0 Time (min) 5-15-5 Fig. 2 (d) Heating temperature (℃) 1100 Type and flow rate of atmospheric gas (L/min), Time @)Nx
1 -1 -1 020S 05 05 POClm 6 0.5 0 Time (minutes) 5-30-5 According to the present invention, strain is generated in the silicon crystal by the emitter region shape to improve the unfitting characteristics. Since there is no diffusion of metal that shortens the lifetime as in the conventional method, there is no need to limit leakage current caused by contamination of the silicon oxide film, and there is a remarkable effect that it can be controlled arbitrarily.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体基板に対する不純物拡散用の装置を示す
断面図、第2図(1)〜(d)はいずれもエミッタ部の
ひずみを示す図である7、 1   加熱炉 2   反応容器 3.3′   シリコン基板 4&、4b  反応気体導入口 代理人 弁理士  井 上 −男 第1図 第2図 (lλ   (b) (C)            (d、)手続補正書(
自発) 57.1.13 昭和  年  月  日 特許庁長官 島 1)春 樹 殿 1、事件の表示 昭和56年特許−第163422号 2、発明の名称 半導体装置の製造方法 3、補正をする者 事件との関係 特許出願人 (307)東京芝浦電気株式会社 4、代理人 〒144 東京都太田区曲出4−」目41@11号第−津野田ビル 井上特許争務所内 5、補正の対象 明細書の発明の詳細な説明の欄 6、補正の内容 明細書の第3頁第19行目(末社より2行目)および第
20行目(末社)を次に補正する。 1シリコンの格子に歪を生じさせるソース(きわめて為
濃度のドープ鷺、なお、リン原子はシリコン原子に比べ
て小さい原子半径を有する)が強制的にエミッタ」 以上
FIG. 1 is a cross-sectional view showing an apparatus for diffusing impurities into a semiconductor substrate, and FIGS. 2 (1) to (d) are views showing strain in the emitter section. 7.1 Heating furnace 2 Reaction vessel 3.3 ' Silicon substrates 4&, 4b Reactive gas inlet agent Patent attorney Inoue Figure 1 Figure 2 (lλ (b) (C) (d,) Procedural amendment (
Voluntary) 57.1.13 Showa year, month, day, Japan Patent Office Commissioner Shima 1) Haruki Tono1, Indication of the case 1982 Patent - No. 1634222, Title of invention Method for manufacturing semiconductor device 3, Person making amendment case Relationship with Patent Applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent Address: 144 Kurude 4, Ota-ku, Tokyo, Item 41 @ No. 11 - Tsunoda Building Inoue Patent Dispute Office 5, Specification subject to amendment Column 6 of the Detailed Description of the Invention, page 3, line 19 (second line from the end) and line 20 (from the end) of the statement of contents of the amendment will be amended next. 1 A source that causes strain in the silicon lattice (a very highly doped heron; phosphorus atoms have a smaller atomic radius than silicon atoms) is forced to become an emitter.

Claims (1)

【特許請求の範囲】[Claims] オキシ塩化リンを拡散源とするエミッタ領域形成とライ
フタイムを短化させるφ段とを備えた半導体装−の製造
方法において、−ミツ−領域のシリコン結晶内に歪を生
じさせるように拡散の温度、ガス濃度の高い拡散を施す
ことによってエミッタ領域の形成とライフタイムの短化
とを排せ行表うことを特徴とする半導体装置の製造方法
In a method for manufacturing a semiconductor device including formation of an emitter region using phosphorus oxychloride as a diffusion source and a φ stage for shortening the lifetime, the diffusion temperature is adjusted so as to cause strain in the silicon crystal of the region. A method of manufacturing a semiconductor device, characterized in that formation of an emitter region and shortening of lifetime are eliminated by performing diffusion with a high gas concentration.
JP16342281A 1981-10-15 1981-10-15 Method of manufacturing semiconductor device Pending JPS5866336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16342281A JPS5866336A (en) 1981-10-15 1981-10-15 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16342281A JPS5866336A (en) 1981-10-15 1981-10-15 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5866336A true JPS5866336A (en) 1983-04-20

Family

ID=15773595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16342281A Pending JPS5866336A (en) 1981-10-15 1981-10-15 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5866336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341650A (en) * 2020-03-13 2020-06-26 天水天光半导体有限责任公司 Bubble-emitting phosphorus diffusion process method for reducing triode reverse amplification factor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341650A (en) * 2020-03-13 2020-06-26 天水天光半导体有限责任公司 Bubble-emitting phosphorus diffusion process method for reducing triode reverse amplification factor
CN111341650B (en) * 2020-03-13 2023-03-31 天水天光半导体有限责任公司 Bubble-emitting phosphorus diffusion process method for reducing triode reverse amplification factor

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