JPS586613A - Noise reduction common-use circuit - Google Patents

Noise reduction common-use circuit

Info

Publication number
JPS586613A
JPS586613A JP56105235A JP10523581A JPS586613A JP S586613 A JPS586613 A JP S586613A JP 56105235 A JP56105235 A JP 56105235A JP 10523581 A JP10523581 A JP 10523581A JP S586613 A JPS586613 A JP S586613A
Authority
JP
Japan
Prior art keywords
circuit
amplifier
noise reduction
input
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56105235A
Other languages
Japanese (ja)
Other versions
JPS6338122B2 (en
Inventor
Nobuhiro Suzuki
信博 鈴木
Masaru Sasaki
賢 佐々木
Yasuo Kominami
小南 靖雄
Kazuo Watanabe
一雄 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Pioneer Corp
Original Assignee
Hitachi Ltd
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Pioneer Corp, Pioneer Electronic Corp filed Critical Hitachi Ltd
Priority to JP56105235A priority Critical patent/JPS586613A/en
Publication of JPS586613A publication Critical patent/JPS586613A/en
Publication of JPS6338122B2 publication Critical patent/JPS6338122B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G11/00Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
    • H03G11/08Limiting rate of change of amplitude

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)

Abstract

PURPOSE:To prevent the generation of a click noise during recording and reproduction switching by extracting an AC component from an input signal to a compressing and expanding circuit, and then feeding it back to a preceding amplifying circuit. CONSTITUTION:A recording input signal after being amplified by an AC amplifier 13 is inputted through an amplifier 15 to a characteristic varying circuit 6, where it is compressed. A playback input signal, on the other hand, is amplified by an AC amplifier 14 and then inputted through the amplifier 15 to the characteristic varying circuit 6, where it is expanded. The output of the amplifier 15 is fed negatively back to amplifiers 13 and 14 through the AC feedback circuit consisting of a resistance and a capacitor. During recording and reproduction switching, only the amplifier 13 or 14 is activated. At this time, the DC levels of both the amplifiers are nearly equal even if there is variance in offset, and an AC feedback circuit is used in common, reducing click noises that a tape deck generate as much as possible.

Description

【発明の詳細な説明】 本発明は、テープデツキ用ノイズリダクションシステム
に関し、特に、かかるノイズリダクションシステムの圧
縮及び伸張共用回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction system for a tape deck, and more particularly to a common compression and expansion circuit of such a noise reduction system.

磁気テープ゛を用いてアナログ録音をするテープデツキ
において、録再特性のダ・イナミレンジの拡大をなすた
めにドルビーノイズリダクションシステム等のノイズリ
ダクションシステムカ広り用いられている。
In tape decks that perform analog recording using magnetic tape, noise reduction systems such as the Dolby noise reduction system are widely used to expand the dynamic range of recording and playback characteristics.

かかるノイズリダクションシステムは、録音さるべき入
力信号をあるレベルにまで圧縮してテープに録音しテー
プから得られる再生出力を伸張して元に戻す圧縮回路及
び伸張回路を備えている。
Such a noise reduction system includes a compression circuit and an expansion circuit that compress an input signal to be recorded to a certain level, record it on a tape, and expand and restore the playback output obtained from the tape.

この圧縮回路及び伸張回路は、ちょうど互いに逆特性に
なっておシ、はとんどの部分が共用出来るため、通常、
単一の共用回路として構成され外部からの指定により、
圧縮回路としであるいは伸張回路して作用するようにな
っている。
The compression circuit and decompression circuit have exactly opposite characteristics to each other, and most parts can be shared, so usually,
It is configured as a single shared circuit, and depending on external specifications,
It is designed to act as a compression circuit or as an expansion circuit.

かかる共用回路の従来例を第1図に示す。第1図の回路
においては、録音さるべき入力信号が入力端子lに供給
され、テープデツキから得られる再生信号が入力端子2
に供給されるように接続される。端子1を経た録音入力
信号は第1DC増幅回路(以下アンプ)3の一方の入力
端子に供給され、端子2を経た再生入力信号は第2DC
アンプ4の一方の入力端子に供給される。第1及び第2
DCアンプ3,4の他方の入力端子と出力端子との間に
は各々帰還抵抗R1,R2が接続され、該他方の入力端
子は共に抵抗R3,R4を介して基準電位v7に接続さ
れている。第1及び第2DCアンプ3゜4の出力端子は
、アナログ切替スイッチ502つの入力端子5cL、 
5bに接続されている。アナログ切再生(PB)指定制
御信号に応じて入力端子5α又は5bを出力端子5Gに
選択的に接続する。出力端子5cは特性可変回路6に接
続されている。特性可変回路6は、録音制御指定制御信
号又は再生指定制御信号に応じて圧縮特性回路又は伸張
特性回路となる。特性可変回路6は、デツキ(図示せず
)に供給さるべきレベル圧縮された信号を出力端子6a
に出力し、スピーカ等を含む再生処理回路(図示せず)
に供給さるべきレベル伸張された信号を出方信号に応じ
て圧縮又は伸張作用をなすのであるが、録音指定制御信
号から再生指定制御信号に切替わるとき、特性可変回路
6から大なるレベルのクリックノイズが生ずる。・これ
は、DCアンプ3,4が直流増幅をなすアンプであシ、
内部能動素子のオフセット電圧のバラツキにょシ出力直
流電位が互いに犬きく異なる故である。
A conventional example of such a shared circuit is shown in FIG. In the circuit shown in Figure 1, the input signal to be recorded is supplied to input terminal 1, and the playback signal obtained from the tape deck is supplied to input terminal 2.
connected to be supplied to the The recording input signal passing through terminal 1 is supplied to one input terminal of the first DC amplifier circuit (hereinafter referred to as amplifier) 3, and the playback input signal passing through terminal 2 is supplied to the second DC amplification circuit (hereinafter referred to as amplifier) 3.
It is supplied to one input terminal of the amplifier 4. 1st and 2nd
Feedback resistors R1 and R2 are connected between the other input terminal and output terminal of the DC amplifiers 3 and 4, respectively, and the other input terminals are both connected to a reference potential v7 via resistors R3 and R4. . The output terminals of the first and second DC amplifiers 3゜4 are the analog changeover switch 50, two input terminals 5cL,
5b. The input terminal 5α or 5b is selectively connected to the output terminal 5G according to the analog cut-off playback (PB) designation control signal. The output terminal 5c is connected to the characteristic variable circuit 6. The characteristic variable circuit 6 becomes a compression characteristic circuit or an expansion characteristic circuit depending on the recording control designation control signal or the playback designation control signal. The characteristic variable circuit 6 outputs a level-compressed signal to be supplied to a deck (not shown) at an output terminal 6a.
and a reproduction processing circuit (not shown) including speakers, etc.
It compresses or expands the level-expanded signal to be supplied to the output signal depending on the output signal, but when switching from the recording designation control signal to the playback designation control signal, a large level click is generated from the characteristic variable circuit 6. Noise occurs.・This is an amplifier in which DC amplifiers 3 and 4 perform DC amplification.
This is because the output DC potentials are significantly different from each other due to variations in the offset voltages of the internal active elements.

本発明は、上記した如き従来例における問題点を解決し
て、録音再生切替時においてもクリックノイズが生じな
いノイズリダクション共用回路を提供することを目的と
する。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the conventional example and to provide a noise reduction common circuit that does not generate click noise even when switching between recording and playback.

本発明によるノイズリダクション共用回路は、録音指定
制御信号によって活性化される低利得の第1差動アンプ
と再生指定制御信号によって活性化される低利得の第2
差動アンプの出力信号を増幅する高利得の第3のアンプ
とを備え、第3のアンプの出力信号のうちの交流成分の
みを第1及び第2差動アンプの入力端子に帰還する一方
第1及び第2差動アンプは交流アンプとして作用せしめ
るように構成された切替回路を含むことを特徴としてい
る。
The noise reduction common circuit according to the present invention includes a first low-gain differential amplifier activated by a recording designation control signal and a low-gain second differential amplifier activated by a playback designation control signal.
a high-gain third amplifier that amplifies the output signal of the differential amplifier, and feeds back only the AC component of the output signal of the third amplifier to the input terminals of the first and second differential amplifiers; The first and second differential amplifiers are characterized in that they include switching circuits configured to operate as AC amplifiers.

以下、本発明の実施例を第2図によって説明する。Hereinafter, embodiments of the present invention will be described with reference to FIG.

第2図に示した本発明によるノイズリダクション共用回
路において、入力端子11.12には録音入力信号及び
再生入力信号が各々供給される。第1及び第2差動アン
プ13,14は各々例えば1対のトランジスタからなる
低利得の差動アンプであり、差動アンプ13 、14の
一方の入力端子は直流カット用キャパシタC1,C2を
介して入力端子11 、12 K接続されかつ抵抗R5
,R6を介して基準電位v7に接続されている。また、
差動アンプ13 、14の残シの端子は、抵抗R8,キ
ャパシタC3の直列回路を介して接地されている。更に
、差動アンプ13 、14は、録音指定制御信号及び再
生指定制御信号によって活性化されるようになっている
。例えば、差動アンプ13.14の差動対への定電流供
給をオン・オフするように構成することが出来る。差動
アンプ13゜14の出力端子は、第3のアンプ15の入
力端子に接続されている。アンプ15は、例えば多段ア
ンプであって高利得を有する。アンプ15の取方端子は
、特性可変回路6の入力端子に接続されており、特性可
変回路60機能及び出力端子6a 、 6bの接続関係
は従来例と同様である。アンプ15の出力端子と差動ア
ンプ13 、14の共通接続入力端子との間には帰還抵
抗R7が接続され、抵抗R7,R8及ぶキャパシタC3
によって交流帰還回路が形成されている。
In the noise reduction common circuit according to the present invention shown in FIG. 2, input terminals 11 and 12 are supplied with a recording input signal and a reproduction input signal, respectively. The first and second differential amplifiers 13 and 14 are each a low-gain differential amplifier consisting of, for example, a pair of transistors, and one input terminal of the differential amplifiers 13 and 14 is connected to the DC cut capacitors C1 and C2. input terminals 11 and 12 K are connected and resistor R5
, R6 to the reference potential v7. Also,
The remaining terminals of the differential amplifiers 13 and 14 are grounded through a series circuit of a resistor R8 and a capacitor C3. Furthermore, the differential amplifiers 13 and 14 are activated by a recording designation control signal and a reproduction designation control signal. For example, it is possible to configure the constant current supply to the differential pair of the differential amplifiers 13 and 14 to be turned on and off. The output terminals of the differential amplifiers 13 and 14 are connected to the input terminal of the third amplifier 15. The amplifier 15 is, for example, a multi-stage amplifier and has a high gain. The terminal of the amplifier 15 is connected to the input terminal of the variable characteristic circuit 6, and the function of the variable characteristic circuit 60 and the connection relationship between the output terminals 6a and 6b are the same as in the conventional example. A feedback resistor R7 is connected between the output terminal of the amplifier 15 and the common connection input terminal of the differential amplifiers 13 and 14, and a capacitor C3 is connected to the resistors R7 and R8.
An AC feedback circuit is formed.

上記した如く構成された本発明によるノイズリダクショ
ン共用回路において、録音指定と再生指定とが切替わる
場合、差動アンプ13 、14の活性状態が切替わるの
であり、このとき、差動アンプ13゜14の直流レベル
は同一アンプに構成することで互いに基準電位vrにほ
ぼ等しくかつ低利得であり直流的にはゲインが1である
から内部能動素子のオフセットの多少のバラツキがあっ
ても出力電位の変動は極めて小さく、クリックノイズは
発生しなれ いのである。また、抵抗R8とキャパシタCa、;l”
らなる接地回路嶌は差動アンプ13 、14に対して共
用されており、差動アンプ13,14について各々必要
とせず部品点数の削減に寄与すると票にこのノイズリダ
クション共用回路をIC化したとき抵抗R8とキャパシ
タC3との間にキャパシタ外付用のピンが1本必要とな
るだけであって、ビン数削減にも寄与するのである。更
に、C1R5とC2R60時定数をそろえることにより
電源投入時の不安定状態において録音再生切換を行なっ
てもクリックノイズは極めて小さくなるのである。
In the noise reduction shared circuit according to the present invention configured as described above, when the recording designation and the playback designation are switched, the active states of the differential amplifiers 13 and 14 are switched. By configuring them in the same amplifier, the DC levels of both are almost equal to the reference potential vr and have a low gain, and the gain is 1 in terms of DC, so even if there is some variation in the offset of the internal active elements, the output potential will not fluctuate. is extremely small, and no click noise occurs. In addition, the resistor R8 and the capacitor Ca, ;l”
This grounding circuit is shared by the differential amplifiers 13 and 14, and when this noise reduction shared circuit is integrated into an IC, it is said that each of the differential amplifiers 13 and 14 is not required and contributes to a reduction in the number of components. Only one external pin for the capacitor is required between the resistor R8 and the capacitor C3, which also contributes to reducing the number of bins. Furthermore, by making the C1R5 and C2R60 time constants the same, click noise becomes extremely small even when recording/playback is switched in an unstable state when the power is turned on.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示すブロック図、第2図は本発明の実
施例を示すブロック図である。 主要部分の符号の説明 11 、12・・・入力端子   13 、14・・・
差動アンプ15  ・・・・・・第3のアンプ
FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. Explanation of symbols of main parts 11, 12... Input terminals 13, 14...
Differential amplifier 15...Third amplifier

Claims (1)

【特許請求の範囲】 (リ 第1及び第2制御信号に各々応じて活性化される
ように構成された低利得の第1及び第2差動増幅回路と
、前記第1及び第2差動増幅回路の出力端子双方に接続
された入力端子を有する高利得の第3増幅回路と、前記
第3増幅回路の出力電圧の交流成分のみを前記第1及び
第2差動増幅器各々の一方の神子に帰還する帰還回路と
、前記第1及び第2差動増幅回路各々の他方の入力端子
に交流入力信号を供給する交流入力回路と、前記第3増
幅回路の出力信号を前記第1又は第2制御信号に応じて
圧縮し又は伸張する作用をなす特性可変回路とからなる
ことを特徴とするノイズリダクション共用回路。 (2)前記帰還回路は、前記第3増幅器の出力端子と一
端において接続し前記第1及び第2差動増幅器の前記一
方の入力端に他端において接続した抵抗回路と、前記抵
抗回路の前記他端と基準電位点との間に接続された抵抗
とキャパシタとの直列回路とからなることを特徴とする
特許請求の範囲第1項記載のノイズ゛リタ゛クンSン%
f回語・(3)前記直列回路のキャパシタが前記基準電
位点側に接続されていることを特徴とする特許請求の範
囲第2項記載のノイスーリダクンヨンFE[IBJ
[Scope of Claims] a high-gain third amplifier circuit having an input terminal connected to both output terminals of the amplifier circuit; and a high-gain third amplifier circuit having an input terminal connected to both output terminals of the amplifier circuit; an AC input circuit that supplies an AC input signal to the other input terminal of each of the first and second differential amplifier circuits; and an AC input circuit that supplies the output signal of the third differential amplifier circuit to the first or second differential amplifier circuit; A noise reduction shared circuit comprising a characteristic variable circuit that compresses or expands according to a control signal. (2) The feedback circuit is connected at one end to the output terminal of the third amplifier, and a resistor circuit connected at the other end to the one input terminal of the first and second differential amplifiers; and a series circuit of a resistor and a capacitor connected between the other end of the resistor circuit and a reference potential point. Noise recovery S ratio according to claim 1, characterized in that
(3) The noise reduction FE [IBJ according to claim 2, characterized in that the capacitor of the series circuit is connected to the reference potential point side.
JP56105235A 1981-07-06 1981-07-06 Noise reduction common-use circuit Granted JPS586613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56105235A JPS586613A (en) 1981-07-06 1981-07-06 Noise reduction common-use circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56105235A JPS586613A (en) 1981-07-06 1981-07-06 Noise reduction common-use circuit

Publications (2)

Publication Number Publication Date
JPS586613A true JPS586613A (en) 1983-01-14
JPS6338122B2 JPS6338122B2 (en) 1988-07-28

Family

ID=14401985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56105235A Granted JPS586613A (en) 1981-07-06 1981-07-06 Noise reduction common-use circuit

Country Status (1)

Country Link
JP (1) JPS586613A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481402A (en) * 1987-09-22 1989-03-27 Canon Kk Signal processor
JPS6481401A (en) * 1987-09-22 1989-03-27 Canon Kk Signal processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03100822U (en) * 1990-01-30 1991-10-22

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481402A (en) * 1987-09-22 1989-03-27 Canon Kk Signal processor
JPS6481401A (en) * 1987-09-22 1989-03-27 Canon Kk Signal processor

Also Published As

Publication number Publication date
JPS6338122B2 (en) 1988-07-28

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