JPS5864610A - Signal detector - Google Patents

Abstract

PURPOSE:To detect each peak value of an input signal precisely by passing the output signal of each level comparator, provided for the positive and negative half waves of the input signal respectively, through a gate circuit respectively, and thus obtaining a logical output of amplitude information on the input signal. CONSTITUTION:Switching means TRa and TRb which attenuate the held voltages of holding means Ca and Cb when input signals (a) and (-a) drop in level to a specified or less level difference than the held voltages of the peak-value holding means Ca and Cb, and level comparators 15a and 15b which make level comparisons between the held voltages of the holding means Ca and Cb, and input signals (a) and (-a). Then, output signals of the level comparators 15a and 15b are passed through a gate circuit 16 respectively to generate a logical output of pieces of amplitude information on the input signals (a) and (-a). Consequently, positive and negative peak points of the input signals (a) and (-a) are detected accurately, and the amplitude information on the input signal is detected accurately and stably even in case of momentary variation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection device, and particularly to a signal detection device that accurately detects the level of a digital signal reproduced from a magnetic recording medium with very few code errors (t=extremely small) even when there is a level change. The object of the present invention is to provide a signal detection device that can detect signals.

Generally, when reproducing a digital signal recorded on a magnetic recording medium such as a magnetic tape, the low frequency component close to the DC component is greatly reduced due to the differential characteristics of the winding of the magnetic head. In many cases, the peak level of the reproduced digital signal is detected and processed in order to obtain the original digital signal from the reproduced digital signal, which is a differentiated waveform of the low recorded digital signal. This peak level detection device uses the output from the magnetic head.
The differential waveform signal of the digital signal is amplified to a predetermined level, then rectified and further differentiated, and the zero-crossing point corresponds to the peak position.The zero-crossing point can be detected using a Schutz trigger circuit, etc. there were. However, this conventional signal detection device has a complicated circuit configuration and has many unstable elements such as a differential circuit, leading to malfunctions when there are level fluctuations in the reproduced signal, and it is difficult to reproduce the original code at the time of recording. There were drawbacks such as a lack of fidelity.

The present invention eliminates the above-mentioned drawbacks, and the following describes the first
An embodiment thereof will be described with reference to FIGS. 5 to 5.

The present invention relates to a signal detecting device provided in a digital signal reproducing device. Prior to explaining the signal detecting device, an outline of a recording device and a reproducing device for the digital signal detected by the device of the present invention will be explained.

FIG. 1 shows a block system diagram of an example of a general magnetic arranging device for digital signals. In the figure, a digital signal of a binary code to be recorded that enters an input terminal 1 is passed through a converter 2 and processed by two stages of cascade-connected 1-bit delayers 3 and 4, each having a 1-bit period and a total of 2 pint periods. After a delay, it is returned to converter 2. As a result, between the input digital signal of converter 2#'i and the digital signal obtained by delaying the output digital signal of converter 2 by 2 bit periods, the corresponding bits are converted into binary codes. Addition modulo 2 is performed, and the resulting addition signal f is supplied to a 1-bit delay device 3, and also supplied to a constant current amplifier 5 as a recording binary code digital decoding. The constant current amplifier 5 amplifies the binary code digital signal for recording of the upper sweetfish to an appropriate current value and supplies it to the winding of the recording magnetic head 60, and thereby the magnetic tape 7.
Record it above. The recording magnetic head 6 has, for example, a plurality of gaps, and simultaneously forms a plurality of trunks corresponding to the plurality of gaps on the magnetic tape in the longitudinal direction of the magnetic tape T.

Figure 4 (4) shows an example of the waveform of the input digital signal that entered input terminal 1, and the numerical value at the top is 2 to be recorded.
Indicates the value code (original data). Also, Fig. 4 ω) Cane converter 2
The waveform of the recording binary code digital signal output from n is shown. The magnetic reproducing apparatus shown in FIG. 1 can perform magnetic recording and reproducing of digital signals using a partial response method that does not transmit a direct current component and is suitable for magnetic recording and reproducing by layering the differential characteristics of the magnetic head.

FIG. 2 shows a block system diagram of an example of a magnetic reproducing device equipped with the device of the present invention. In the figure, Wf! is on the multi-track on the magnetic tape T! The recording binary code digital signal shown in FIG. When the distribution current reverses from negative to positive, it becomes a positive pulse, and when it reverses from positive to negative, it becomes a negative pulse. The ternary code signal waveform is as follows. This ternary code signal is converted to 75
? After being amplified to a required level, the signal is supplied to the crosstalk canceller circuit 1o. Crosstalk canceller circuit 1o
A plurality of n are provided corresponding to head gaps on a plurality of sides of the magnetic head 8, and a reproduction signal f' is obtained from the ternary code signal of the track to be reproduced and the tracks on both sides adjacent to the ternary code signal n.
A ternary code signal with L-running crosstalk removed is supplied, respectively, and the T'Lfel value code signal is reproduced from the track to be reproduced and reproduced from the tracks on both sides mixed with code crosstalk. The value code signals are canceled and removed to produce a ternary code signal from which crosstalk has been removed. An example of the configuration of this two-circuit io on a stalk scan is as follows:
A circuit previously proposed by the present applicant in Japanese Patent Application No. 511-407!1311 can be used.

The ternary code signal extracted from the crosstalk canceller circuit 1o is supplied to an equalizer 11, where it compensates for high-frequency components attenuated in the process of magnetic recording and reproduction, and adjusts the signal to a characteristic having an appropriate band. Furthermore, the reproduced signal waveform itself is subjected to waveform equalization to prevent code amount interference. As a result, the output signal waveform of the equalizer 11 becomes a ternary code signal having signal levels corresponding to +1°0 and -1 without code amount interference. This ternary code signal is branched into two (n), and is supplied to the signal detection device 12 of the present invention through an inverting amplifier and a non-inverting amplifier provided at the output stage of the equalizer 11, where +1 ．． The signal level corresponding to -1 is +
1, the signal level corresponding to 1fc0 is set to O and the edge is converted into a binary code signal, and the signal is output to the output terminal 13 so that the original original code digital signal at the time of recording is restored. nru.

FIG. 3 shows a circuit diagram of an embodiment of the signal detection device 12 according to the present invention. In the figure, a non-inverting amplified ternary signal with an activation amount of 11 and an inverted amplified ternary signal with an equalization amount of 11 are input to the input terminals of 14am and 14bti, respectively. Here, from the input terminal 14a, the level comparison operational amplifier 15! The first circuit section leading to L and the input terminal 141
), the second circuit sections leading to the level comparison operational amplifier 1sb and Vc have the same configuration, and corresponding parts are given the same reference numerals, and circuit elements constituting the first circuit section are given the subscript a. 1, and the circuit elements constituting the second circuit section are given a suffix. Input terminals 14a, 14b
are connected to the inverting input terminals of the operational amplifiers 15a and 15b, while the operational amplifier 15a is connected through rectifying diodes D, Db'.

Connected to the non-inverting input terminal of tab. Diode Da
e Db cathode and operational amplifiers 15a, 15b
The connection point with the non-inverting input terminal of the transistor is grounded via the peak value holding capacitor Oa, 01), while the collector of the switching PNP is grounded. ing. Furthermore, the base of the transistor Tras Trb is a resistor R,?
! '+1) input terminal through? 4a and 14b.

The output terminals of operational amplifiers 15a and 15b are 2-power NA
It is connected to each input terminal of the ND circuit 16. In addition,
Of course, other switching elements may be used instead of the transistor Tra e TrbO.

In the signal detection device 12a having the above configuration, the input terminal 14
Assuming that a ternary stroke signal a shown in FIG. When the above three-value signal a rises in the positive direction and reaches the level (the time at this time is indicated by t at 0 in FIG. 4), the diode D turns on, The three-value signal a is applied to the capacitor Oa through the diode Da to charge the capacitor Oa. (also the output voltage) is shown in Figure 4 (
As shown by the dotted chain 11b in C), following the positive rise in the signal level of the three-value signal a, the diode D is
The voltage increases by the threshold voltage vTH of a at a lower voltage value. Then, the signal level of the three-value signal a passes through the positive peak point and starts to decrease, but the voltage across the capacitor ca, bh, the diode DIL, and the transistor 'I'r
Since all n of a are off, the charging voltage value at the above positive peak point remains unchanged as shown in FIG. 4(C) despite the decrease in the signal level of the three-value signal a.
Continuing, the signal level of the three-value signal a is the threshold voltage vT of the transistor T compared to the voltage across the capacitor c1.
The time when it became lower than H' (Figure 4 (indicated by t2 at 0)
From then on, the transistor Tr& is turned on by the three-value signal a applied to its base.

When the transistor Tra is turned on, the capacitor OA is discharged, so that the voltage between both ends of the capacitor 01 drops to approximately the ground level (strictly speaking, the loss voltage between the transistor 01 and the collector).

Also, during or just before the discharge period of the charge in the capacitor ca, the signal level of the three-value signal a changes to the capacitor C.
I! Since the voltage across L is less than the threshold value 'VCIH of diode Da compared to the voltage, diode Da is turned off. After the voltage across the capacitor Oa reaches approximately the ground level, the three-value signal a continues to decrease in level, passes the peak point of the eclipse, and begins to rise further in the positive direction.
Since the transistor Tr& is in the ON state during the period until it becomes higher than the pre-adjustment value alarm pressure vTH, as shown in Fig. 4 (
As shown in C), the voltage across the capacitor 010 remains approximately at the ground level. Thereafter, the same operation as above is repeated.

In this way, the transistor Tra is connected to the ternary signal a.
The switching is controlled by the capacitor Ca.
The voltage across the capacitor ca obtained by controlling the charging and discharging of is applied as a control voltage to the non-inverting input terminal of the operational amplifier 15a, and then to the inverting input terminal of the operational amplifier 15a.
The level is compared with the value signal a. The output signal waveform after level comparison by the operational amplifier 15a is output from the operational amplifier 1.
If 5a does not have hysteresis characteristics, as shown by the condensed lines in Figure 4), at the intersection of the signal levels a and b, 11% from the low level or from the hello level.
If the voltage has a hysteresis characteristic, it becomes a binary voltage that changes to the high level, as shown by the dashed line in Φ) in the same figure.

Similarly, the value signal e shown in FIG. The signal n is applied to the circuit 16, is NANDed here, and is the signal f shown in FIG.
It is output as a value mark signal detection signal. This detection signal f
is the source of the binary stamp signal (shown at ω in the figure) to be recorded and reproduced before the converter 2 converts the binary stamp signal shown in FIG. It has a level that roughly corresponds to the data.

This detection signal f/ri is applied to the data terminal of a D-type flip-flop (not shown) from the output terminal 13, for example, and the phase and signal nl as shown in FIG. By applying a clock pulse of the same frequency and latching the input detection signal fe at the data terminal at the rising edge of the clock pulse, the output from the Q output terminal of the D-type flip-flop is as shown in FIG. It is possible to accurately reproduce and output a binary encoded signal whose timing matches the original binary encoded signal.

Figure 5 line shows the input level versus code error rate characteristics when an M-sequence random code signal is magnetically recorded and reproduced by the magnetic recording device and magnetic reproducing device shown in Figures 1 and 2. Input terminal 14a.

14t+ shows the input ternary code signal level. As is clear from Fig. 5, the input ternary code signal level is 1.2v.
~s, svl), the bit error rate is constant at an extremely low value of about -p11ch, and the signal can be detected stably and faithfully. This is because, as described above, since the control voltage 1 is generated immediately in response to the ternary mark signal B, each of the positive and negative peak points of the ternary mark signal a can be accurately detected.

Furthermore, as shown in FIG.
rL, the noise level increases in accordance with the input level,
This is because a phenomenon occurs in which noise causes data to malfunction even though the signal level is zero. Furthermore, as shown in FIG. 5, when the input ternary code signal a becomes smaller than 1.2 V, the code lI palm rate increases -p due to the diodes DB and Dl in the ternary code signal a and the control voltage. This is because there is a threshold voltage "TH" etc. of It has been confirmed that this embodiment can significantly improve the bit error rate to about i, compared to conventional devices that detect peak values above a predetermined level.

In addition, the present invention apparatus Fi has a configuration in which signal detection is possible even when the input signal is a binary signal other than the above-mentioned three-value signal, and the peak value is held after performing half-wave rectification on the positive and negative sides of the input signal. However, various other modifications can be considered.

As described above, the signal detection device of the present invention is provided with a rectification holding circuit that holds a peak value after half-wave rectification of an input signal, and a peak value holding means in the rectification holding circuit, so that the input signal level is A switching means for attenuating the holding voltage of the nuclear holding means by an input signal when the holding voltage of the holding means becomes less than a certain level difference, and a level comparator for comparing the levels of the holding voltage of the peak value holding means and the input signal, respectively. The level detection circuit section consisting of
Each level comparator output signal of the level detection circuit section provided for each negative half wave is configured to pass through a gate circuit and logically output the amplitude information of the input signal. Since the holding voltage of the peak value holding means is immediately generated as a control voltage, each positive and negative peak point of the input signal can be accurately detected. The amplitude information of the input signal can be detected extremely stably and accurately even if there are 7. When a ternary encoded signal with a sharp pattern is supplied as an input signal from a magnetic recording medium on which an encoded signal is distributed, the above control voltage is set to a constant value, and the input signal is On the other hand, compared to conventional devices that detect peak values above a predetermined level, this device has the advantage of being able to significantly improve the code error rate and further improving reliability.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing an example of a general magnetic recording device for digital signals, Fig. 2 is a block system diagram showing an example of a magnetic reproducing device equipped with the device of the present invention, and Fig. 3 is a block system diagram showing an example of a magnetic reproducing device equipped with the device of the present invention. A circuit diagram showing an embodiment of the signal detection device shown in FIG.
FIG. 5 is a diagram showing an example of the relationship between the input signal level and the bit error rate in FIG. 3. 1... Digital signal input terminal, 2... Converter, 3
゜4...1-bit delay device, 6...Magnetic head for recording, T...Magnetic tape, --...Magnetic head for reproduction, 1
1... Equalization amount, 12... Signal detection device, 13...
Output terminals, 14a, 14b... B l [sign signal input terminal, f5a * 1ab... level comparison operation, operational amplifier, 16... NAND circuit, DI! L,'D
b... Rectifier diode, O, I Ob... Peak value holding capacitor, Tras Trb... Switching PNP) transistor. Figure 2 Figure 3 Figure 4 → Sunny Figure 5

Claims (1)

[Claims] 1. A rectification holding circuit that holds a peak value after half-wave rectification of an input signal, and a peak value holding means in the rectification holding circuit, which is provided for the input signal level to the holding means. The voltage was below a certain level difference from the holding voltage. In this case, a level detecting circuit section consisting of a switching means for attenuating the holding voltage of the holding means and a level comparator for comparing the levels of the holding voltage of the peak value holding means and the input signal, respectively, is connected to Signal detection characterized in that the output signal of each level comparator of the level detection circuit section provided for each half wave is configured to pass through a gate circuit and logically output the amplitude information of the scissors input signal. Device. 2. The signal detection device according to claim 1, wherein the input signal is a three-value signal reproduced from a magnetic recording medium on which a binary signal is recorded.