JPS5864146U - Receiver mute circuit with priority - Google Patents
Receiver mute circuit with priorityInfo
- Publication number
- JPS5864146U JPS5864146U JP1981157942U JP15794281U JPS5864146U JP S5864146 U JPS5864146 U JP S5864146U JP 1981157942 U JP1981157942 U JP 1981157942U JP 15794281 U JP15794281 U JP 15794281U JP S5864146 U JPS5864146 U JP S5864146U
- Authority
- JP
- Japan
- Prior art keywords
- receiver
- level
- priority
- terminal
- transceiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Transceivers (AREA)
- Noise Elimination (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による使用例の図解、第２図は本考案の
実施回路例を示す。
１・・・ＡＦ増幅器、２・・・スピーカ、３． ４．
１１゜１４・・・・・・コンデンサ、５，８，９，１０
．１３・・・抵抗、７．１２・・・トランジスタ、１５
．１８・・・ダ、イオード、１６・・・スレショルド調
整器。FIG. 1 illustrates an example of the use of the present invention, and FIG. 2 shows an example of an implementation circuit of the present invention. 1... AF amplifier, 2... speaker, 3. 4.
11゜14... Capacitor, 5, 8, 9, 10
．． 13...Resistor, 7.12...Transistor, 15
．． 18...Da, diode, 16...Threshold adjuster.
Claims (1)
度上位の受信機あるいは送受信機より制御レベルを入力
する端子と、受信優先度下位の受信機あるいは送受信機
に制御レベルを出力する端子と、 （２）前記入力端子のレベルがし、のとき、ＡＦ信号回
路に並列に設けた第１の制御用トランジスタのコレクタ
・エミッタ間導通をＯＮにすることによりＡＦ倍信号ミ
ュートする回路と、（３）受信入力により第２の制御用
トランジスタあコレクタ・エミッタ間導通をＯＮにする
回路と、前記出力端子のレベルを、トランジスタがＯＮ
のときにＬレベルにクランプする回路と、（４）前記入
力端子と前記出力端子間にそう人し、入力端子ラインが
Ｌレベルのとき、出力端子ラインをＬレベルにクランプ
するダイオードと、より成ることを特徴とする優先順位
付の受信機ミュート回路。[Claims for Utility Model Registration] In a radio receiver or transceiver, (1) a terminal for inputting a control level from a receiver or transceiver with a higher reception priority, and a terminal for inputting a control level from a receiver or transceiver with a lower reception priority; (2) When the level of the input terminal is high, an AF multiplied signal is generated by turning ON conduction between the collector and emitter of the first control transistor provided in parallel with the AF signal circuit. (3) a circuit that turns on conduction between the collector and emitter of the second control transistor in response to the reception input;
(4) a diode that is connected between the input terminal and the output terminal and clamps the output terminal line to L level when the input terminal line is at L level; A receiver mute circuit with priorities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981157942U JPS5864146U (en) | 1981-10-23 | 1981-10-23 | Receiver mute circuit with priority |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981157942U JPS5864146U (en) | 1981-10-23 | 1981-10-23 | Receiver mute circuit with priority |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5864146U true JPS5864146U (en) | 1983-04-30 |
| JPS6236366Y2 JPS6236366Y2 (en) | 1987-09-16 |
Family
ID=29950447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981157942U Granted JPS5864146U (en) | 1981-10-23 | 1981-10-23 | Receiver mute circuit with priority |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5864146U (en) |
-
1981
- 1981-10-23 JP JP1981157942U patent/JPS5864146U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6236366Y2 (en) | 1987-09-16 |
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