JPS586344B2 - Fugou Kasouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code conversion device, and particularly to a coding device using a multi-stage divisional coding method.

Recently, various encoding methods have been proposed for data compression and transmission time reduction of facsimile signals.

One of these encoding methods is a multi-stage divisional encoding method that is suitable for computer processing.

(IEICE Communication Systems Study Group Material CS73-36 (1)
(Refer to 973-07)) In this multi-stage divisional encoding method, the signals corresponding to the I scanning area are divided into multiple blocks, the presence or absence of a black level in each block is detected, and if there is a black level, a code "1" is generated. is assigned, and if there is none, a code 10" is assigned.

Thereafter, the block in which the black level has been detected is further divided, and the above-described operations are repeated, and for the finally divided block, a unit area code representing the state of the black and white levels in that block is sent out.

Such a multi-stage divisional encoding method determines the black and white level on a block-by-block basis, so it is suitable for encoding and decoding using a computer.

However, a simple and easy-to-configure encoding and decoding device suitable for the multi-stage divisional encoding method has not yet been proposed.

An object of the present invention is to provide an encoding device having a simple configuration and suitable for a multi-stage divisional encoding method.

According to the present invention, there is provided a memory for storing an image signal divided into predetermined lengths and a conversion code whose code has been converted, a means for selectively writing the image signal and the conversion code into the memory, and the memory. means for selectively reading out the image signal or the conversion code in integer units of n (≧2) and converting it into a 1-bit conversion code; and a code necessary for decoding among the image signal and conversion code read from the memory; An encoding device is obtained which has means for selecting a code and an address code, means for providing addresses for writing and reading from the memory, and means for controlling the timing of each of the means.

The present invention reads an image signal written in a memory in a predetermined bit unit, converts the code to form a conversion code, and then
By writing the conversion code into memory and repeating this operation, division codes and unit area codes are accumulated in memory, and from among these accumulated codes, necessary address codes and code codes are transmitted. It is a device.

Here, the address code and the code code are the divided codes and unit area codes to be transmitted, excluding the all-zero divided codes and unit area codes.

The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining a multi-stage divisional encoding method according to the present invention.

In FIG. 1, an image signal A is a binary code string to be encoded, and here a code string corresponding to one scanning line of a facsimile signal is shown.

Note that the figure shows a case where the number of samples for one scanning line is 1024.

Further, in the figure, the shaded area indicates the black level, and the numerical values indicate the run lengths of the white level and the black level.

When encoding, the 1024-bit image signal A is first divided into four groups of 256 bits, and the presence or absence of a black level in each group is detected.

The primary division code B is generated by giving a code of "1" representing the black level when there is a black level, and giving a code of "0" representing the white level when there is no black level.

Therefore, in the case of image signal A, (1110) is obtained as primary division code B.

Next, in this primary division code B, "
For the 1'' group, this 256-bit group is further divided into four secondary groups of 64 bits, and the presence or absence of a black level is detected for each secondary group.

Here, as in the case described above, if there is a black level, “
If there is no code, a code of "1" is given, and if there is no code, a code of "0" is given, and a secondary division code C is generated.

In the case of image signal A, this secondary division code C is (0001)
(0100) (0100).

Furthermore, for the quadratic group of code “1” of the quadratic division code C,
This is divided into four parts, and the presence or absence of the black level is detected for each tertiary group in units of 16 bits.
00) is generated.

In addition, the group of code "1" of the cubic division code D is divided into groups of 4 bits, (0101) (0001) (1001
) (0011), and finally, when the quaternary division code E is "1" representing the black level, the 4 bits of the image signal A are sent as is as a unit area code. .

The 1st to 4th division codes are sent out in order from the 1st division code,
After sending out the quaternary division code, 4 bits of the image signal are sent out.

Therefore, the image signal is sent out without being mixed in each divided code.

Here, the primary to quaternary division codes do not represent the image signal A, but are related to the position of the black level or white level of the image signal, so they are called address codes.

On the other hand, since the unit area code is related to whether the image signal A is a white level or a black level, it is called a code code.

When the image signal A shown in FIG. 1 is code-converted by the multistage divisional encoding method, the primary divisional code B becomes (1110), and three "1"s appear.

Further, the secondary division code C is a code of 3×4=12 bits, the tertiary division code D is a code of 3×4=12 bits, and the quaternary division code E is a code of 4×4=16 bits.

Since the number of unit area codes F is 4, 7×4=28 bits become the remaining unit area codes.

FIG. 2 is a diagram for explaining one embodiment of the present invention.

Note that here, the division size n is set to 4, and the number of samples for one scanning line is set to 1024.

Referring to the diagram, an image signal A as shown in FIG. be done.

On the other hand, the timing control circuit 13 generates a control signal and sends it to the gate 12 based on the master clock from the terminal 14 and the encoding start signal from the terminal 15.

The gate 12 sends the 4-bit image signal from the serial/parallel converter 11 to the memory 16 in response to a control signal.

In the memory 16, the image signal is written in units of 4 bits at addresses O to 255 in accordance with the address signal from the memory address non-control circuit 17.

The image signal written in the memory 16 is sent to the code conversion circuit 18 in units of 4 bits at an appropriate time, such as after 1024 bits of information for one scanning line have been written.

The code conversion circuit 18 takes the logical sum of 4 bits and converts it into a 1-bit conversion code.

Further, in this code conversion circuit 18, the 4-bit converted code that is sequentially code-save converted is serial-parallel converted by a control signal from the timing control circuit 13, and is converted into a converted code in units of 4 bits.

This 4-bit conversion code is sent from the code conversion circuit 18 to the memory 16 via the gate 12, and is controlled by addresses 256 to 256 by the address signal of the memory address control circuit 17.
319 every 4 bits.

Next, the code conversion circuit 18 takes the logical sum of the 4-bit conversion codes written in addresses 256 to 319, sequentially converts them into 1-bit conversion codes, and converts the conversion codes into serial and parallel codes every 4 bits. Convert address 320-33
Write in 5.

Similarly, the conversion codes written at addresses 320-325 are converted to addresses 336-339.
The conversion codes written to addresses 336 to 339 are code-converted and written to address 340.

By the operation described above, addresses 0 to 34 of memory 16 are
This means that the image signal and conversion code are written in 0.

When an address signal is given from the memory address control circuit 17 in this state, it is sequentially read from address 340 in the reverse direction to address 0, and an output signal is sent from the output terminal 20 of the parallel-to-serial conversion circuit 19 through the code conversion circuit 18. be done.

At this time, the code conversion circuit 18 calculates the logical sum of the codes corresponding to the n-bit (here, 4 bits) address code (or code code) output from the memory 16, and determines whether any one of the n bits In the case of 1, a high level control signal is given to the timing control circuit 13.

The timing control circuit 13 receives the control signal and sends a clock to the clock terminal 21 to instruct the timing of the n-bit address code (or code code).

At this time, since the code sent from the code converter 18 is an address code (or code code), it is parallel-to-serial converted by the parallel-to-serial conversion circuit 19, and the code sent from the above-mentioned clock terminal 2
output terminal 2 as an output sign in synchronization with the clock to
sent to 0.

When the logical sum of the codes corresponding to the address code (or code code) is O, no clock is sent from the clock terminal 21, and therefore the code sent at this time is not determined to be the address code (or code code).

By transmitting the code in this format, the number of transmitted bits can be reduced.

FIG. 3 is a diagram for explaining the operation of the memory address control circuit 17 shown in FIG. 2, and shows time on the horizontal axis and address numbers on the vertical axis.

Referring to the figure, a straight line A indicates the operation of the read counter, in which an image signal is written in units of 4 bits at addresses 0 to 255 of the memory, and then the image signal is read out from the same address.

Furthermore, it can be seen that in the portion of addresses 256 to 339, a conversion code including a quadratic division code is read from a quaternary division code.

Further, straight line B is a diagram showing the operation of the write counter, and it can be seen that the conversion code including the 4th division code to the 1st division code is written in the address 256-340 portion of the memory.

A straight line C shows the operation of a counter that reads out codes from the encoding device, and counts down from address 340 to include the primary division code to the quaternary division code (address code) and unit area code (code code). The conversion code and image signal are being read.

Although the circuit configuration of the encoding device of the present invention has been described above,
The division size and division unit of the image signal are 102
It goes without saying that the size is not limited to 4 and 4, and that it can be of any size.Furthermore, although the circuit configuration is shown divided by function, if it is replaced with a micro or minicomputer, the size shown in Figure 2. Of course, all the functions shown in can be performed simultaneously.

As described above, in the present invention, code conversion can be performed by repeating the operation of reading an image signal written in a memory, performing code conversion, and then writing the converted code into the memory.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining an embodiment of the binary image signal encoding method according to the present invention, FIG. 2 is a block diagram showing the circuit configuration of the encoding device of the present invention, and FIG. FIG. 2 is a diagram for explaining the operation of a counter in the encoding device of the present invention. Explanation of symbols 12... Gate, 13... Timing control circuit, 16... Memory, 17... Memory address control circuit, 18... Code conversion circuit, 19... Parallel-serial conversion circuit.

Claims (1)

[Claims] 1. Receive a series of image signals representing an image, divide the image signals into a plurality of groups and encode them, and encode an address code representing the position of each image signal and a code code corresponding to a part of the image signal over time. An encoding device that generates data in a manner that does not mix the image signal with a timing control circuit that controls timing according to a predetermined sequence; a gate for selecting a converted code obtained by partial code conversion under the control of the timing control circuit; and a memory for sequentially storing the image signal and the converted code selected by the gate. , a memory address control circuit that controls write and read addresses of the memory according to the control of the timing control circuit, and a code pattern of the image signal and conversion code written in the memory in units of (positive integer ≧2); a code conversion circuit that makes a determination under the control of the timing control circuit, generates a 1-bit conversion code and stores it in the memory through the gate, and sequentially reads out the contents of the memory; a parallel-to-serial conversion circuit that sends out the contents of the memory in the form of a serial code, the code conversion circuit logically ORing the contents of the memory and sending the result to the timing control circuit; An encoding device characterized in that, when the logical sum is 1, a clock synchronized with the serial code is generated.