JPS5863218A - Equalizer - Google Patents

Equalizer

Info

Publication number
JPS5863218A
JPS5863218A JP16208181A JP16208181A JPS5863218A JP S5863218 A JPS5863218 A JP S5863218A JP 16208181 A JP16208181 A JP 16208181A JP 16208181 A JP16208181 A JP 16208181A JP S5863218 A JPS5863218 A JP S5863218A
Authority
JP
Japan
Prior art keywords
waveform
circuit
circuits
delay
equalizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16208181A
Other languages
Japanese (ja)
Inventor
Junkichi Sugita
杉田 順吉
Hiroyuki Uchida
裕之 内田
Yutaka Hayata
裕 早田
Shigemi Imakoshi
今越 茂美
Tetsuo Sekiya
哲夫 関谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16208181A priority Critical patent/JPS5863218A/en
Publication of JPS5863218A publication Critical patent/JPS5863218A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/04Control of transmission; Equalising
    • H04B3/14Control of transmission; Equalising characterised by the equalising network used
    • H04B3/143Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers
    • H04B3/144Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers fixed equalizers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Amplifiers (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To obtain a cosine equalizer, by using a delaying circuit which has a cascade connection of the primary and secondary all pass circuits. CONSTITUTION:The reproduced waveform given from an input terminal Ti is turned into waveforms A, B and C of different phases and with no change of form through the delaying circuits 30 and 40. Each of the circuits 30 and 40 has a cascade connection of the primary and secondary all pass circuits. The waveforms B and C are synthesized by resistances R51 and R52 plus a variable resistance RV1 with a proper ratio and then fed to a differential amplifier 51. The output B+C of the amplifier 51 is controlled by a variable resistance RV2 for its amplitude and added with the waveform A at the next differential amplifier 52. Thus a waveform D having a narrowed width is delivered to an output terminal T0. Thus the size is reduced for an equalizer which corrects the reproduced waveform of a digital signal recorded with high density.

Description

【発明の詳細な説明】 この発明は、q#にデジタル信号を磁気記録したテープ
から再生した波形、又は伝送路で歪な−うけた波形を修
復するイコライザに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an equalizer that restores a waveform reproduced from a tape on which a digital signal is magnetically recorded on q#, or a waveform that is distorted in a transmission path.

デジタル信号を磁気テープに記録し、再生する装置にお
いて、一般に磁気テープに記録するデータの密度を高く
すると、相対的に磁気テープの再生スピードが低下する
ことになるので、その再生波形は高域の周波数成分が失
われてなまりが生じ。
In devices that record and play back digital signals on magnetic tape, generally speaking, increasing the density of data recorded on the magnetic tape will result in a relative decrease in the playback speed of the magnetic tape. Frequency components are lost and an accent occurs.

正確なデータが得られなくなる。Accurate data cannot be obtained.

そのため波形を等化するイコライザを使用し。Therefore, use an equalizer to equalize the waveform.

再生波形を等化して記録密度を高くする技術が知られて
いる。
Techniques for increasing recording density by equalizing reproduced waveforms are known.

第111j(aHまこのような波形の等化を行うフサイ
ンイコライザを示したもので、このコサインイコライザ
は、第1図(b)に示すように再生波形Aに対し、τ、
だけ位相が進んだ波形B、及び7重だけ位相がおくれて
いる波形Cを遅延回路1及び2Wcよって形成し、前記
再生波形Aと、適当な振幅値とする係数回路3,4を介
して波形B、及び波形Cを加減算回路5によって演算し
、つまり再生波形Aから波形B、及び波形Cを差引くこ
とに本 よって再生波形のピーク点を変えることなく、そのパル
ス幅を狭くした波形りを形成するものであが比較的小さ
い場合は遅延線などを遅延回路1゜及び2として使用す
ることができるが、磁気テープと磁気ヘッドの相対速度
が比較的小さい(例えば標準力tットのテープ速度であ
る4、8cm/sωもので高密度記録な行なったと針の
イコライザとして使用するときは、前記遅延量τ1 、
τ雪 としてlO〜15μm位が必要となり、パッシン
グタイプの遅延線ではその形状が非常に大きくなって実
用的ではない。
No. 111j (aH) This shows a cosine equalizer that equalizes a waveform like this. This cosine equalizer is used for the reproduced waveform A as shown in FIG. 1(b).
A waveform B whose phase is advanced by 7 times, and a waveform C whose phase is delayed by 7 times are formed by the delay circuits 1 and 2Wc, and the waveforms are formed by the reproduced waveform A and the coefficient circuits 3 and 4 that set an appropriate amplitude value. By calculating waveform B and waveform C using the addition/subtraction circuit 5, that is, by subtracting waveform B and waveform C from the reproduced waveform A, a waveform with a narrowed pulse width can be obtained without changing the peak point of the reproduced waveform. If the magnetic tape to be formed is relatively small, delay lines or the like can be used as delay circuits 1 and 2, but the relative speed between the magnetic tape and the magnetic head is relatively small (for example, when the tape has a standard force of When high-density recording is performed at a speed of 4.8 cm/sω, the delay amount τ1,
A τ snow of about 10 to 15 μm is required, and a passing type delay line has a very large shape and is not practical.

この発明は、かかる点に鑑みてなされたもので。This invention was made in view of this point.

アクティブな回路によつ℃必要な遅延特性を持たせ、イ
コライザを小型に形成するよ5にしたものである。
5 in order to provide the active circuit with the necessary delay characteristics and to form a compact equalizer.

以下、この発明のイコライザについて説明する。The equalizer of this invention will be explained below.

まず、インピーダンス素子り、CKよって形成されろパ
ッシブなオールパス回路(全域通過回路)における一般
的な位相特性について述べる。
First, general phase characteristics in a passive all-pass circuit formed by impedance elements and CK will be described.

第2図に示すように、−次のオールバス回路10と、二
次のオールバス回路20を従属接続したときそ−れぞれ
の伝送係数は で示されること、が知られている。
As shown in FIG. 2, it is known that when a second-order all-bus circuit 10 and a second-order all-bus circuit 20 are connected in cascade, their respective transmission coefficients are expressed by.

但し、S=j ω ω;角周波数 ω、ニー次のオールバス回路10の中心角周波数(位相
が90°回る角周波数) ω。二二次のオールバス回路20の中心角周波数(位相
が180°回る角周波数) を示す。
However, S=j ω ω; angular frequency ω, center angular frequency of the knee-order all-bus circuit 10 (angular frequency at which the phase rotates 90°) ω. The central angular frequency (angular frequency at which the phase rotates 180 degrees) of the second-order all-bus circuit 20 is shown.

これらの式から、−次のオールバス回路10の遅延特性
は。
From these equations, the delay characteristics of the all-bus circuit 10 are as follows.

2ω− τ、(ω)=□ ・・・・・・・・・・・・・・・・・
・・・・(3)ω2+ω2 二次のオールバス回路20の遅延特性は。
2ω− τ, (ω)=□ ・・・・・・・・・・・・・・・・・・
...(3) ω2+ω2 What is the delay characteristic of the secondary all-bus circuit 20?

になる。become.

この第(3)式は第3図のτ、IC示すように角周波1
1 数ωの増加と共VC順次減少する曲線を示し、第(4)
式はτ、で示すように中心角周波数ω。をビーク点とし
て左右に減少する単峰性の曲IIIVcなる。
This equation (3) has an angular frequency of 1 as shown by τ and IC in Figure 3.
1 shows a curve in which VC sequentially decreases as the number ω increases, and the (4)
The formula is τ, as shown by the central angular frequency ω. It becomes a unimodal curve IIIVc which decreases left and right with the peak point being the peak point.

したがって、第2図のように一次のオールバス回路10
と、二次のオールバス回路20を従属接続したときの綜
合遅延量は、τ=τ、(す+τbcm)のこの図から、
綜合遅延量τはω、からω、までの帯域において、ω2
.ω。及びQを適宜設定することによって、はぼ平坦な
遅延量τ、とすることができ、前記したω、〜ω、まで
の信号帯域にについては遅延線による遅延特性と同一の
機能をもたすことができろ。
Therefore, as shown in FIG.
From this diagram of τ=τ, (S+τbcm), the total delay amount when the secondary all-bus circuit 20 is connected in cascade is as follows.
The total delay amount τ is ω2 in the band from ω to ω.
.. ω. By appropriately setting and Q, a fairly flat delay amount τ can be obtained, and the signal band from ω to ω has the same function as the delay characteristic of the delay line. Be able to do that.

今、必要な周波数帯域を約50 KHz  とし、その
周波数帯域で遅延量をlO〜15μ膠とする場合につい
て、前記中心角周波数ω1.ω。及びQについて検討し
た結果、−=l〜1.s、Q=0.7ωa 〜0.85にすれば、はぼ満足できる遅延特性が得ら4
ることを確かめた。
Now, in the case where the required frequency band is about 50 KHz and the delay amount in that frequency band is lO~15μ, the central angular frequency ω1. ω. As a result of considering and Q, -=l~1. If s, Q = 0.7ωa ~ 0.85, a very satisfactory delay characteristic can be obtained4.
I confirmed that.

したがって、前述した第1図のコサインイコライザにお
い工、取り扱5周波数帯域な約50KHz。
Therefore, the cosine equalizer shown in FIG. 1 described above deals with 5 frequency bands of approximately 50 KHz.

遅疵回路1.2の遅延時間τ1.τ、として10〜15
μ自とするときは、前述した一次のオールバス回路10
.及び二次のオールバス回路20を従属接続した回路で
遅延回路1.2が実現でき、遅延線を使用することなく
回路な小型に形成できることになる。
Delay time τ1 of delay circuit 1.2. τ, 10 to 15
μ itself, the above-mentioned first-order all-bus circuit 10
.. The delay circuit 1.2 can be realized by a circuit in which the second-order all-bus circuit 20 and the second-order all-bus circuit 20 are connected in series, and the circuit can be made compact without using a delay line.

第4図はか〜ろ一次及び二次のオールバス回路をCRを
使用してアクティブな回路によって具体化した一実施例
を示すもので、−次のオールバス回路10は差動増幅器
11.抵抗R11+R+* 、R111(− 及びコンデンサCssで形成され、二次オールパス回路
20は差動増幅器21.抵抗R□、R2t h R* 
s 。
FIG. 4 shows an embodiment in which the primary and secondary all-bus circuits are realized by active circuits using CR, and the -th all-bus circuit 10 is a differential amplifier 11 . Resistors R11+R+*, R111(-) and capacitor Css form the secondary all-pass circuit 20, which is a differential amplifier 21. Resistors R□, R2th R*
s.

R鵞4及びコンデンサC□+C2x+ で形成したもの
である。
It is formed by R 4 and capacitor C□+C2x+.

この回路において、−次のオールバス回路10の中心角
周波数ω、は、ω’  ” C,、R,Tであり。
In this circuit, the central angular frequency ω of the -th all-bus circuit 10 is ω'''C,,R,T.

で1図示した抵抗値及び容量QiVcすると、ω、キ3
1.26KHz  、  ω。中40.86KHz と
なり、−!」−中1,3とすることができた。
If the resistance value and capacitance QiVc are shown in the diagram, then ω, Q3
1.26KHz, ω. It becomes 40.86KHz in the middle, -! ” - I was able to make it 1st and 3rd year of junior high school.

ωa となる。ωa becomes.

jlE5図はliA図の回路図に図示した数値の抵抗。The jlE5 diagram shows the resistance values shown in the circuit diagram of the liA diagram.

及びコンデンサを使用して回路を作り実際に遅延特性を
測定したデータを図示したものである。この図から約5
0KHz の帯域幅において、遅延時間τが、12.5
μBではぼ一定になっていることが分かる。
This figure shows data obtained by actually measuring the delay characteristics of a circuit made using a capacitor and a capacitor. From this figure, about 5
At a bandwidth of 0 KHz, the delay time τ is 12.5
It can be seen that μB is almost constant.

第6図は前記第4図で示した遅延回路を利用して前述し
たコサインイコライザを具体化した一実施例な示すもの
で、30及び40は1M4図で示した7クテイブな一次
及び二次のオールバス回路で加 形成した遅延回路、50は可減算回路を示す。
FIG. 6 shows an embodiment of the above-mentioned cosine equalizer using the delay circuit shown in FIG. A delay circuit formed by adding an all-bus circuit, 50 indicates a subtractable circuit.

前記加減算回路50は二つの差動増幅器51゜52及び
抵抗Ril〜R1m及び可変抵抗器RV、。
The addition/subtraction circuit 50 includes two differential amplifiers 51 and 52, resistors Ril to R1m, and a variable resistor RV.

Rv3より構成されている。遅延回路30.40は第4
図に示したものを使用する。
It is composed of Rv3. The delay circuit 30.40 is the fourth
Use the one shown in the diagram.

この回路は前述した第1図(a)のコサインイコライザ
の動作原理と同様に動作する。つまり入力端子T+から
入力された再生波形は、その波形な変えろことなく遅延
回路30.及び40によって遅延され、前記第1図(b
)で示した位相の異なる波形A、B、Cを形成する。波
形B、Cは抵抗R1゜R,1,及び可変抵抗RV、  
によって適正な比率で合成され、差動増幅器51に入力
される。差動増幅器51の出力であるB+C波形はさら
に可変抵抗RV、  によって振幅を調整さ11.次の
差動増幅s52で波形Aと加算されて、出力端子T、 
K幅を狭くした波形In出力するものである。
This circuit operates in the same manner as the cosine equalizer shown in FIG. 1(a) described above. In other words, the reproduced waveform input from the input terminal T+ is transferred to the delay circuit 30 without changing its waveform. and 40, said FIG. 1(b
) waveforms A, B, and C having different phases are formed. Waveforms B and C are resistance R1゜R,1 and variable resistance RV,
The signals are combined at an appropriate ratio and input to the differential amplifier 51. The amplitude of the B+C waveform output from the differential amplifier 51 is further adjusted by a variable resistor RV.11. It is added to the waveform A in the next differential amplification s52, and the output terminal T,
A waveform In with a narrower K width is output.

なお、帯域幅として50K)I、遅延量として125μ
mに設定した遅延回路は+ PCMオーディオ信号をカ
セットのテープ速度4.8 cm/aで再生するとpk
使用するコサインイコライザに必[LKとさいうまでも
ない。
In addition, the bandwidth is 50K)I, and the delay amount is 125μ.
The delay circuit set to m is + pk when playing a PCM audio signal at a cassette tape speed of 4.8 cm/a.
It goes without saying that LK is required for the cosine equalizer used.

以上詳述したように、この発明のイブライザは遅延回路
として一次、及び二次のオールバス回路を7クテイブ回
路によって形成したので遅延線を用いることなくコサイ
ンイコライザが形成でき物に、テープ速度がおそい場合
に高密度で記録したデジタル信号の再生回路において、
波形を修復す型 るためのイコライザを小形に形成することができるとい
う利点な有する。
As detailed above, in the equalizer of the present invention, the primary and secondary all-bus circuits are formed as delay circuits by 7-acting circuits, so a cosine equalizer can be formed without using a delay line, and the tape speed is slow. In the reproduction circuit of digital signals recorded at high density,
It has the advantage that the equalizer for restoring the waveform can be formed in a small size.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)はコサインイコライザのブロック
図、及びその各部波形図、12図は一次及び二次のオー
ルバス回路の従属接続図、第3図は第2因の遅延特性M
、第4図はこの発明の一実施例を示す遅蔦回路図、第5
図は第41!21の特性図、纂6因はこの発明のイコラ
イザを示す回路図である。 第 1 図(a) Δ 第2図 第3図 tAJI             ωa   woW
2ω ト− Cつ  〜  ?−。 +−一一
Figures 1 (a) and (b) are block diagrams of the cosine equalizer and their respective waveform diagrams, Figure 12 is a dependent connection diagram of the primary and secondary all-bus circuits, and Figure 3 is the delay characteristic M of the second factor.
, FIG. 4 is a delay circuit diagram showing one embodiment of the present invention, and FIG.
The figure is the 41st!21st characteristic diagram, and the sixth factor is a circuit diagram showing the equalizer of the present invention. Figure 1 (a) Δ Figure 2 Figure 3 tAJI ωa woW
2ω To C ~? −. +-11

Claims (1)

【特許請求の範囲】 コサインイコライザにおいて、中心角周波数をω、とす
る一次のオールバス回路と、中心角周波数なω。とする
二次のオールバス回路を従属接続して遅延回路を形成し
、前記中心角周波数の比をωゆ −= 1〜1.5. 前記二次のオールバス回路のQω
龜 を0.7〜0.85に設定したことを脣徴とするイブラ
イザ。
[Claims] A cosine equalizer includes a first-order all-bus circuit with a center angular frequency of ω and a center angular frequency of ω. A delay circuit is formed by cascade-connecting secondary all-bus circuits, and the ratio of the central angular frequencies is set to ω = 1 to 1.5. Qω of the secondary all-bus circuit
Ibrizer's characteristic is that the barrel is set between 0.7 and 0.85.
JP16208181A 1981-10-13 1981-10-13 Equalizer Pending JPS5863218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16208181A JPS5863218A (en) 1981-10-13 1981-10-13 Equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16208181A JPS5863218A (en) 1981-10-13 1981-10-13 Equalizer

Publications (1)

Publication Number Publication Date
JPS5863218A true JPS5863218A (en) 1983-04-15

Family

ID=15747718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16208181A Pending JPS5863218A (en) 1981-10-13 1981-10-13 Equalizer

Country Status (1)

Country Link
JP (1) JPS5863218A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2576729A1 (en) * 1985-01-29 1986-08-01 Ampex EQUALIZER CONTROL BY VOLTAGE
JPH01236729A (en) * 1988-03-16 1989-09-21 Fujitsu Ltd Differentiating circuit and magnetic recording and reproducing circuit using same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2576729A1 (en) * 1985-01-29 1986-08-01 Ampex EQUALIZER CONTROL BY VOLTAGE
JPH01236729A (en) * 1988-03-16 1989-09-21 Fujitsu Ltd Differentiating circuit and magnetic recording and reproducing circuit using same

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