JPS5863168A - Field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To remove the unstability of a field effect type semiconductor device when operated at cryogenic temperature by forming a p-n junction with semiconductor having no thermal carrier production at the operating temperature in the vicinity of the surface of a semiconductor substrate and stopping the majority carrier to flow to the substrate. CONSTITUTION:A field silicon oxidized film 5 of approx. 700nm and a gate silicon oxidized film 3 of approx. 50nm are formed on the prescribed region on a p type (100) silicon substrate 1 having 3.5X10<15>atoms/cm<3> of boron density, arsenic is added by an ion implantation method to a channel region, thereby forming an n type region 6. Thereafter, a polysilicon for a gate electrode is formed by the ordinary silicon gate step, and with the polysilicon as a mask for ion implantation arsenic is added to the source and drain region at approx. 10<21>atoms/cm<3>. Further, an Al electrode is removed through a through hole step. When the impurity is lower than 10<17>atoms/cm<3> at the cryogenic temperature, the carrier is frozen, and the n type layer 6 becomes semi-insulating, and no unstability of characteristics occur as the conventional MOSFET, and back gate effect is not presented at all.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a field effect semiconductor device that operates stably and at high speed at extremely low temperatures.

Conventional semiconductor devices are designed and manufactured to operate at around room temperature (300°C), but if you try to operate them at, for example, liquid helium temperature (4.2K), they may not function properly as a semiconductor device. Or it doesn't work at all. For example, in a silicon bipolar transistor, impurities added to silicon are not thermally ionized at extremely low temperatures, so no carriers are generated (so-called carrier freezing) and the transistor does not operate at all. On the other hand, in FETs such as the M-8 field effect transistor (M-S FmT), carriers are injected into the semiconductor surface from the source region where carrier freezing does not occur due to the high impurity concentration, and furthermore, below the gate, carriers are injected into the semiconductor surface. The electric field effect ionizes impurities near the surface and unfreezes the carriers, making it possible to operate even at extremely low temperatures.

When such a field effect semiconductor device is operated at a low temperature, (a) carrier mobility is improved, and (b) wiring resistance is reduced. In particular, if a superconducting material is used, the wiring resistance can be reduced to zero. (c) Carrier freezing can be caused in a semiconductor substrate to make it semi-insulating, and the capacitance between electrodes, wiring and ground can be significantly reduced. The above effects are often more significant as the operating temperature is lower. Therefore, field effect semiconductor devices operated at extremely low temperatures have the great advantage of operating at high speed.

However, in the conventional M-8 FIT shown in FIG. 1, it was impossible to operate it with good reliability due to the instability of the characteristics at extremely low temperatures, which will be described below.

In FIG. 1, the voltage (VsUB) applied to the p-type silicon substrate 1 is set to zero, the voltage (VD) is applied to one side (drain) of the n+ diffusion layer 2, and the other side (source) of the n+ diffusion layer 2 is applied. Current flowing through the drain when grounded (■D)
FIG. 2 shows the VD characteristics at 4.2 K, with the voltage (vo) applied to the gate electrode 4 on the p-type substrate 1 via the insulating film 3 as a parameter. Note that 5 in FIG. 1 is a field oxide film.

From Figure 2, it can be seen that hysteresis occurs in the voltage/current characteristics, which is ■. Even if you fix it, it depends on the history of how to give the VD. This means that the M-work 1 changes.
It can be seen that the circuit using 9 FETs has unstable operation. Additionally, when vsUB is changed, the threshold voltage (vTH) usually changes (so-called back gate effect), but in the conventional case, the change in vTH does not occur instantaneously, and a time delay of several seconds may occur. Fell. This similarly made the circuit operation unstable.

The above instability can be explained using the band diagram along the dotted line 8 in FIG. 1 shown in FIG. For the semiconductor substrate 1,
When a positive voltage is applied to the gate electrode 4 through the gate insulating film 3, an inversion layer is formed on the surface of the semiconductor substrate l due to the field effect, and electrons (indicated by Ionization occurs, and the generated holes (indicated by 0) move to the semiconductor substrate 1 along the potential gradient. For this reason, the semiconductor substrate 1 changes from a semi-insulating property to a conductor, which causes the aforementioned back gate effect, but since the amount of holes supplied at this time is limited, the change does not occur instantaneously. Characteristics usually change with a long time constant.

Further, the generation of holes due to the electric field on the semiconductor surface is further modulated when a large electric field is applied near the drain, resulting in complicated instability as shown in FIG.

In order to eliminate the instability of field effect semiconductor devices when operated at extremely low temperatures, the present invention provides a large number of p-n junctions near the surface of the semiconductor substrate using a semiconductor that does not generate thermal carriers at operating temperatures. This prevents carriers from flowing into the semiconductor substrate, and its purpose is to provide a semiconductor device that operates stably and at high speed at extremely low temperatures.

The present invention will be described in detail below based on Examples.

FIG. 4 is a sectional view of a field effect semiconductor device according to the first embodiment of the present invention. The feature of the first embodiment of the present invention is that a conductor layer 6 of a conductivity type opposite to that of the semiconductor substrate is provided so as to include the channel on the surface of the semiconductor substrate 1. Note that parts having the same functions as those of the conventional example shown in FIG. 1 are designated by the same reference numerals, and explanations thereof will be omitted. The effect will be explained below. FIG. 5(a) is a band diagram of a portion along the broken line 7 shown in FIG. 4, in the case of vG=Ov and v8UB=Ov.

At room temperature, if such a structure is used, a current flows through the n region with vG = OV, but at extremely low temperatures, when the impurity concentration (5) is below about 10 atoms θ/1yn3, carriers freeze, so the n-type layer 6 It is semi-insulating,
Further, since there is a potential barrier from the source n+ region 2 to the n-type layer 6, no current will flow between the source and drain unless a positive voltage is applied to Vo to lower the potential barrier. Therefore, MO8FIn'r shown in FIG. 4 is ■.

It operates as a so-called enhancement type in which current flows when >0. Voltage V. Even if vG is applied to the gate electrode 4, the area other than the semiconductor surface is semi-insulating, so most of the electric field is applied to the semiconductor surface, and when vG>0, the surface is in an accumulation state as shown in FIG. 5(b). If C, V, < O, then
As shown in FIG. 5(Q), inversion occurs on the surface and holes are generated, but these holes do not flow out to the substrate side because of the potential barrier between the surface inversion layer and the n-shadow region. Therefore, the substrate is not supplied with holes, which are majority carriers, and the substrate remains semi-insulating. Therefore, unlike conventional MOS FETs, there is no instability in characteristics, and no back gate effect appears at all.

Next, the first embodiment will be described in more detail.

(6) A field silicon oxide film 5 of about 700 nm and a gate silicon oxide film 3 of about 50 nm are formed in predetermined areas on a p-type (100) silicon substrate 1 with a boron concentration of 3.5 x 10 atoms/αs. Then, by ion implantation, the acceleration voltage was 110 θV, and the implantation amount was 2.
Arsenic was added to the channel region under the conditions of 6×10'at and Om87-R to form the n-shaded region 6. Thereafter, polysilicon for a gate electrode was formed by a normal silicon gate process, and using this as an ion implantation mask, about 10 atoms/crn3 of arsenic was added to the source/drain regions.

Furthermore, the first electrode was extracted through a through-hole process.

FIG. 6 shows the t-vTll characteristics when the first embodiment manufactured as described above was operated at 4.2. It can be seen that the instability seen in FIG. 2 (conventional MOS and IT) is not seen at all, and normal PET operation is stable. Also, FIG. The back gate voltage of the threshold voltage (V8
It can be seen that there is no backgate effect at all, although it shows dependence (UB). For comparison, the VBUB dependence at 4.2K of the conventional example is shown in B, and there is a back gate effect that is almost the same as when operating at room temperature. That's all,
In the example of Wooden Slab 1, it is clear that there is no flow of majority carriers into the frozen substrate, and thus the characteristics can be stabilized, and at the same time, a semi-insulating substrate can be obtained.

In the first embodiment, it goes without saying that the same operation is possible even if the conductivity types are reversed. Further, in the case of this embodiment, since the substrate remains semi-insulating, the impurity concentration of the substrate does not play a role in MOS PET operation, and may be any impurity concentration within the range that causes carrier freezing. In addition, in a layer of conductivity type opposite to the substrate on the channel surface, the mechanism in which current begins to flow is determined only by the potential barrier, and at extremely low temperatures where carriers freeze, the Fermi level is the edge of the conduction band or valence band. The impurity concentration has little effect on the M2S FFtT characteristics. Therefore, it has the advantage of being less susceptible to fluctuations in impurity concentration.

Next, a cross-sectional structural diagram of the second embodiment of the present invention is shown in FIG.
This will be explained below. This is the impurity concentration that causes carrier freezing at extremely low temperatures (here, the phosphorus concentration I x 10Ill).
crn-3) Field oxide film 15. It has a gate insulating film 13 and a source/drain region 12 made of an r-swelled diffusion layer with a high impurity concentration (arsenic concentration 1×10"crn-" in this case) that does not cause carrier freezing even at extremely low temperatures. The structure has a p-type layer 16 near the surface of the semiconductor. Here, it is necessary to select an impurity concentration for the p-type layer 16 that freezes carriers at an extremely low temperature, and in this example, I x 10" ff
i"-".

With this structure, the gate voltage V. When is zero, the band diagram as shown in Figure 9(a) (Here, the band diagram in Figure 9 1 shows the part along the wave 1s17 in Figure 8) is the p-type layer. 16 and n-type substrate] The carrier of l is frozen and becomes semi-insulating. At the surface of the p-type layer, the band is slightly deformed due to the work function difference between the semiconductor and the gate electrode, but because the electric field is weak, it remains semi-insulating, so a channel is not formed (9). No current flows between the source and drain. When vG>0, as shown in FIG. 9 (1,), the carriers are unfrozen by the electric field on the surface of the p-type layer 16,
Electron injection from the source occurs, and a current begins to flow between the source and drain at a certain VG=vTH. At this time, holes are generated in the p-type layer 16 and the p-type layer becomes non-semi-insulating, but the electrons in the inversion layer on the surface of the p-type layer 16 do not flow out from near the surface to the substrate side. Although carrier freeze is released, this does not affect the n-type substrate 11, and no current flows between the source and drain.

As explained above, according to the second embodiment of the present invention, since the substrate always remains semi-insulating, instability due to majority carrier outflow to the substrate as in the conventional example does not occur, and the substrate It offers the already mentioned advantages of being semi-insulating. It goes without saying that the second embodiment can also operate with the conductivity types reversed.

(lO) Next, FIG. 10 shows an n-channel FEiT similar to the embodiment of the tube 1 of the present invention and an embodiment of the tube 2 of the present invention, but
Complementary type MO8 with PET changed to p-channel type
A third embodiment is shown in which a (0-MOS) inverter is configured. Note that in FIG. 10, parts similar to those in FIGS. 4 and 8 are denoted by the same reference numerals, and explanations thereof will be omitted. n- in the figure
FIT is an n-channel IT, p-FET is a p-channel FET, a is an input terminal, b is an output terminal, and Vo is a power supply. The p-type diffusion layer 22 is the n+ type diffusion layer 12 in FIG.
The n-type semiconductor layer 26 has the same function as the p-type semiconductor layer 16 in FIG. 8, but has a different conductivity type for a p-channel FET. If such a configuration is used, the 0
-Deep diffusion layer (which is essential for MOS inverters)
This method has the advantage that the problems associated with forming a deep diffusion layer, such as the generation of crystal defects due to long-term thermal diffusion at high temperatures, can be eliminated and the yield can be improved. At the same time, as already explained, high-speed operation becomes possible by making the substrate semi-insulating.

As explained above, the present invention prevents the majority carriers from flowing into the substrate at extremely low temperatures where carrier freezing occurs, eliminates the instability of FFtT% due to the majority carriers flowing out, and makes the substrate semi-insulating. This made it possible to use it as a sex.

Therefore, in addition to improving carrier mobility and reducing wiring resistance due to low-temperature operation of semiconductor devices, it is possible to reduce wiring capacitance by using semi-insulating substrates, and at the same time, stable operation of F
Since ET has become available, it has become possible to provide semiconductor devices that are highly reliable and operate at high speed.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional field effect semiconductor device, Fig. 2 is a characteristic diagram of a conventional field effect semiconductor device, Fig. 3 is a band diagram of a conventional field effect semiconductor device, and Fig. 4 is a bookmark diagram of a conventional field effect semiconductor device. A sectional view of an embodiment of the invention tube [1'□, FIG. 5(a). (l11), (C) is a band diagram of the embodiment of the invention tube 1, FIG. 6 is a characteristic diagram of the embodiment of the invention tube 1, and FIG. 7 is a bank gate of the conventional and embodiment of the invention tube 1. Figures 8 (a), 1 (b), and 10 (c) are diagrams comparing the characteristics; FIG. The figure shows a sectional view of an embodiment of the tube 3 of the present invention. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...source/drain region, 3...gate insulating film, 4...gate electrode, 5...
Field oxide film, 6... n-type semiconductor layer, 11...
n-type semiconductor substrate, 12...source/drain region, 1
3... Gate insulating film, 14... Gate electrode, 15.
...Field oxide film, 16...p-type semiconductor layer, 22
...Source/drain region, 26...n-type semiconductor layer Patent applicant (13) Cause■ (01)y6<>'1. Ward d (H
A△)M3! 9/1 Figure 10 Procedural Amendment (Method) % Formula % 1. Indication of the case 1982 Patent Application No. 160936 2. Name of the invention Field-effect semiconductor device 3. Person making the amendment Relationship with the case Patent Applicant name (422) 0 Telegraph and Telephone Public Corporation 4, Agent 5, Date of amendment order: February 4, 1980 (Shipping date: February 23, 1980)
6. Target of correction::. Column 7 of “Brief explanation of one drawing of the specification”, contents of amendment

Claims (1)

[Claims] In a semiconductor device having a source region and a drain region formed on a semiconductor substrate and a gate electrode for controlling channels between these regions, the semiconductor device has a first conductivity type and at an operating temperature, carriers are generated by thermal ionization of impurities. a semiconductor substrate in which no carriers are generated due to thermal ionization of impurities at an operating temperature, the semiconductor layer being arranged to form a p-n junction with the semiconductor substrate and including the channel; A field effect semiconductor device characterized by: