JPS5861666A - Semiconductor device and preparation of the same - Google Patents

Semiconductor device and preparation of the same

Info

Publication number
JPS5861666A
JPS5861666A JP16125481A JP16125481A JPS5861666A JP S5861666 A JPS5861666 A JP S5861666A JP 16125481 A JP16125481 A JP 16125481A JP 16125481 A JP16125481 A JP 16125481A JP S5861666 A JPS5861666 A JP S5861666A
Authority
JP
Japan
Prior art keywords
purity
metal
high melting
semiconductor device
compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16125481A
Other languages
Japanese (ja)
Inventor
Minoru Inoue
実 井上
Yasuhisa Sato
泰久 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16125481A priority Critical patent/JPS5861666A/en
Publication of JPS5861666A publication Critical patent/JPS5861666A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce software error by alpha rays by providing conductor and insulation layer consisting of a metal of the IVA, VA, VIA, VIII group in the fourth to sixth period with purity of 99.999%, or its alloy or compound on the semiconductor substrate. CONSTITUTION:When Mo is formed from MoF6 using H2 as the carrier and Ar as the diluent gas, the Th and U becomes difficult to mix with Mo due to a difference of vapor pressure, effect increases in accordance with a reaction temperature, and the vaporization source or sputtering source with purity of 99.999- 99.9999% can be obtained by freely setting a temperature at about 1,200 deg.C. While, when SiH4 etc. is mixed with the reaction gas, a high melting temperature compound MoSi2 can be obtained and its purity can be set to 99.999% or higher by applying the zone-melt method to the metal Mo. In case a conductor or insulation layer is provided by evaporation or sputtering method using one or two kinds or more of these targets, contents of the alpha-rays radioactive substance such as Th or U etc. can be reduced to 1/10 or less and thereby reliability of software error can be improved by 10 times or more.

Description

【発明の詳細な説明】 本発明は千尋体tcよ、特にメモリ部を有する半導体集
積回路装置及びその製造方法に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to Chihirotai TC, and particularly to a semiconductor integrated circuit device having a memory section and a manufacturing method thereof.

半導体装置の導体層形成材料として、アルミニタム(A
I)よt)4関急照で6って、製造工程中にセルフアラ
イメント(s+elf attgntn*nt)法等を
導入した場合に必要とされる熱処理条件に耐え、かつ多
結晶シリコン(St)jジも低い電気抵抗を有するモリ
ブデン(Mo)等の高融点金属、或いはこれよpも化学
的に安定でるるモリブデン・シリナイド(MoSit)
等の高1点並属化合資が試みられて−る0またこれらの
導体ノーの形成方法としては真空蒸着法、スパッタリン
グ法或いは−A相成長(Chemical Vapor
 Deposition ;−以下CVL)と略称する
)法等が知られている。
Aluminum (A
I) Yot) 4) 6) Polycrystalline silicon (St) that withstands the heat treatment conditions required when self-alignment (s+elf attgntn*nt) method etc. is introduced during the manufacturing process. A high melting point metal such as molybdenum (Mo), which has low electrical resistance, or molybdenum silinide (MoSit), which is also chemically stable.
Attempts have been made to synthesize high-point parallel materials such as
Deposition (hereinafter abbreviated as CVL) method is known.

半導体基板上に真空蒸着法又はスノ(ツタリング法によ
って高融点金属よシなる導体Jlを形成する場合に、蒸
発源又はスパッタ・ターゲットとされる核高融点金属の
線区は蛾もN度の萬いもので99.99−であり、これ
らの蒸発源又はスノくツタeターダットにはトリウム(
Tb)、ウラン(U、)が100 ppb程度以上存在
し、又、高融点金、属化合物に関しても、該高融点金属
に対する比率が前記と同程度のTh、 Uが存在する。
When a conductor made of a high melting point metal is formed on a semiconductor substrate by a vacuum evaporation method or a sputtering method, the line area of the nuclear high melting point metal used as an evaporation source or sputtering target is approximately N. Thorium (99.99-
About 100 ppb or more of Tb) and uranium (U) are present, and as for high melting point metals and metal compounds, Th and U are present in the same proportion as above with respect to the high melting point metal.

かくの如き蒸発源又はスノくツタ・ターゲットを用いて
導体層を形成した半導体装置においては、該導体層に含
まれるTh、 Uの放射性〜1磯によムアルファ粒子が
16’個/d・hour程度放出され為このアルファ粒
子がチップ表面を透過する際に記憶ノード付近に多数の
電子−正孔対を生成し、これがメモリ中の蓄積データを
逆転し、シングル・ビット・エラーt−発生するOこの
シングルeビット・エラーは該半導体装置の記憶領域内
で2ンダ復するものであって、以下ソフト・エラーと呼
ぶ。
In a semiconductor device in which a conductive layer is formed using such an evaporation source or a snow ivy target, the radioactivity of Th and U contained in the conductive layer ~16' alpha particles/d・hour When these alpha particles pass through the chip surface, they create a large number of electron-hole pairs near the storage node, which reverses the stored data in the memory and causes a single bit error. This single e-bit error repeats in two orders within the storage area of the semiconductor device, and is hereinafter referred to as a soft error.

前記高融点差属としtは、第1VA族、第VA族。The high melting point difference t is Group 1 VA or Group VA.

第VTA族もしくはS−涙に勇し、かつ第4周期乃至$
6周JgJvC属する金属が対象とされるが、これらの
金属中、例えばタンタル(Ta)、チタン(Ti)等の
虜化物をDRA;□/Tのコ/fンサの誘4体とするこ
とが試みられており、こ0・場合においても該蓋属にf
tnるTh、 Uは前記ソフト−エラーの要因となる。
Group VTA or S--Tearful, and Period 4 to $
Metals belonging to 6 circles JgJvC are targeted, but among these metals, for example, captive substances such as tantalum (Ta) and titanium (Ti) can be used as di4 materials of co/f of DRA;□/T. It has been attempted, and even in this case, f
tnTh, U is the cause of the soft error.

アルファ線の放射は劣えばパッケージ材料からも必シ得
るが、チップ上に計A護痕を設けることによシかな94
M諷させることが可能であるのに対し、半導体素子を形
成する4体層又は絶縁層に対して紘防博が困翔で必るo
 ’フル7I祿放射に起因する前6己ンフト・工2−の
発生は薩牛専体a寛の構造。
Emission of alpha rays can be obtained from the packaging material to a lesser extent, but it may be possible to do so by providing a trace on the chip.94
While it is possible to make a comparison with M, it is difficult and necessary for Hirobo Hiroshi to deal with the four-layer or insulating layer that forms a semiconductor element.
'The occurrence of the previous 6th self-lift and engineering 2- due to the full 7I radiation is the structure of the Satsuma beef exclusive a-hiro.

動作条件等に依存し、一般に半纏体記憶装置ρ;高集積
化され、各メモリーセルθシ荷蓄atが少くなるに伴っ
てノット曇エン−が発生し易くなる。
Depending on operating conditions and the like, in general, as semi-integrated storage devices become highly integrated and the storage capacity of each memory cell θ decreases, knot clouding becomes more likely to occur.

従来′@肯された一例としては、4r(bitの14M
をこりいて、アルファ縁によるソフト・エラーで偏Al
lシが104乃至10”FIT裸度まで劣化する場合が
めることが知られている0 4i:礒明は、系IVA族、箒Vム族、縞Vt人族もし
くは嬉%′11臘に属し、かつ44周期乃至第6周期に
属する金属(以下4融点金属と略称する2又は咳高戚点
金lI4を含むオ菫4L、<は化奮qよすなる、真空4
膚法又はスバッタリ/グ去により形成された導体層又は
絶縁4t−有する一P4体値−に関して、前記のアルフ
ァ線による〕7)・エフ−に就iての1i!願性を改善
することt−目的とする0本発明においては、前v!、
都体層又は絶縁層を形成するにあたりて、〆空蒸着のi
IA発源又はスノ(ツタ・ターゲットとして、純度が9
9.999%以上+2)該高融点金属、又は純度が99
.9994以上の核高融点金属を含む合金もしくは化合
物を用いること全労歓とし、それによって純度が99.
999−以上の該高融点金属又は該高融点食J4を含む
合金もしくは化合物よルなる導体層又は絶縁層を有する
半導体装置が提供される。
An example that has been accepted in the past is 4r (bit of 14M).
due to the soft error caused by the alpha edge.
It is known that when the lushi deteriorates to 104 to 10" FIT nakedness, it is known that Metals belonging to the 44th period to the 6th period (hereinafter abbreviated as 4 melting point metals 2 or 4L containing metals with high melting points,
Regarding the conductor layer or insulation 4t formed by the skin method or the splatter/glue removal, the above-mentioned alpha rays]7)・F-i for 1i! In the present invention, the purpose is to improve the applicability of the previous v! ,
When forming a metropolitan layer or an insulating layer,
IA source or snow (as ivy target, purity 9
9.999% or more +2) The high melting point metal or purity is 99%
.. It is acceptable to use an alloy or compound containing a nuclear refractory metal with a purity of 999.
There is provided a semiconductor device having a conductive layer or an insulating layer made of an alloy or compound containing the high melting point metal or the high melting point eclipse J4 of 999- or higher.

更に前記の純度が9.9.999%以上の該高融点金属
、又は純度が99.999%以上Q該高融点金mt−含
む合金もしくは化合物よりなる蒸発源又はスパッタータ
ーゲットts該高融点金属の気体状化合゛物管用いてC
VD法により形成すること、又はゾ。
Furthermore, an evaporation source or sputter target made of the high melting point metal with a purity of 9.9.999% or more, or an alloy or compound containing the high melting point gold mt with a purity of 99.999% or more of the high melting point metal. C using a gaseous compound tube
Forming by VD method, or

−/メルト法により実現することを特徴と子るO以下本
発明を実施例により具体的に説明する0まf、cvo法
によ)蒸発源又はスパッタ・り′−グツトを形成する実
施例としては例えば水素(8)t−命ヤリアガス、アル
ゴン(ムr)を皇軍(N重)或いはHa!希釈ガスとし
て、例えば弗化モリブデン(MoFJよp化学反応 M o Fs + 311t 4 Mo + 6 HF
によりMot4る0この際にTh、UはMoとの蒸気圧
の羞によp形成された固相Mo中に混入1く、原料とし
たMoF・よ911度が同上する0この効果は反応温度
が高くなるに伴って大きくなるために1000℃以上、
例えば12000程直で実施するが、半導体基板上に直
接導体層を形成する場合と異な1反応iuc’e任意に
選択することがり能でらりて、不方法によりて99.9
99チ以上99.9999チ根度θ純度の蒸発源又はス
パッタφターゲッ)1−得ることが可能である。
The present invention will be explained below in detail with reference to examples, as examples of forming an evaporation source or sputtering groove (by CVO method). For example, hydrogen (8) t-life gas, argon (mr) the imperial army (N heavy) or Ha! As a diluent gas, for example, molybdenum fluoride (MoFJ)
At this time, Th and U are mixed into the solid phase Mo formed by the vapor pressure of Mo, and the raw material MoF is 911 degrees.This effect is due to the reaction temperature. 1000℃ or more because it becomes larger as the temperature increases,
For example, it is carried out directly at about 12,000 yen, but unlike the case of directly forming a conductor layer on a semiconductor substrate, it is possible to arbitrarily select one reaction IUC'e, and it is 99.9 yen depending on the method.
It is possible to obtain an evaporation source or sputter φ target with a purity of 99.9999 degrees or more.

ま友、f4一点食属化合物例えばMo51g’を得るた
めには、モノシラン(S1fIJ等を反応気体中に混合
する。
Well, in order to obtain the f4 single-point edible compound, for example Mo51g', monosilane (S1fIJ, etc.) is mixed into the reaction gas.

高純度の蒸発源又はスパッタ・ターゲットを得る油の′
A実施例しては、例えば會属MOにゾーンメルト法5c
通用して99.9991以上にIA遜することがoJ能
でるる。
of oil to obtain a high purity evaporation source or sputter target.
As an example of A, for example, zone melt method 5c is applied to the associated MO.
Generally speaking, it is possible to outperform IA over 99.9991.

前記実施例等によ多形成された線区99.999−以上
の蒸発源又はスパッタ争ターゲツ)を用いて半導体装置
の導体層又はlA#層を形成する実施例としては次のよ
うな棟々の方法がめる0まず、線区99.999チ以上
の一種類のdI&一点食属よりなるターグツl用い、A
r等の茶請性ガス中でスパッタさせて、半導体基板上に
44g99.999チ以上の咳高融点金属よりなる導体
層を形成するO純度99.999チ以上の高融点金属よ
りなるター偵 ゲyトを二種類又はそれ以上を用い、Ar等の不燈に@
f 99.999%以上の咳高融点金属の合金又は化合
物よりなる導体層を形成する。
Examples of forming a conductor layer or lA# layer of a semiconductor device using the 99.999- or more line sections (evaporation source or sputtering target) formed in the above embodiments, etc. are as follows. First, use one type of dI & one-point food category consisting of line section 99.999 or more, A
A target made of a high melting point metal with a purity of 99.999 cm or more is formed on a semiconductor substrate by sputtering in a tea-like gas such as R. Using two or more types of y, @ to non-lighting such as Ar
f A conductor layer made of an alloy or compound of a high melting point metal of 99.999% or more is formed.

前記例と同様に、純度99.ev9%以上のA一点食属
よりなるターゲットと、高純度シリコンよシ晃 なるターゲットとを用いAr等の不治性ガス中で同時に
スパッタさせて、半導体4板上に高f4度の該金属珪化
豐よりなる導体層を形成する。
As in the previous example, the purity was 99. Using a target made of single-point A metal with an ev of 9% or more and a target such as high-purity silicon, sputtering is performed simultaneously in an incurable gas such as Ar, and the metal silicide with a high f4 degree is sputtered onto four semiconductor substrates. A conductor layer consisting of the following is formed.

又、金II4珪化吻よシなる導体ノーは、該高融点食上 属のみをターゲットとし、Ar尋の茶漬性ガスに5iH
4等を添加した混合気体t4人してスパッタリングを実
施することによっても形成場れる。
In addition, the conductor No. 4, which has a gold II4 silicified nose, targets only the high melting point eclipse, and 5iH
The formation field can also be formed by performing sputtering using a mixed gas to which 4 or the like is added.

更にII4fm点金属窒点食は、窒素ガス(N宜ンk 
Arうh 等の不治性ガスに代え或いは〃αえることに゛よ多形成
され、高融点金J4#!化物は酸素ガス(OlJをAr
h 等の不信性ガスに加えることにより形成される。
Furthermore, point II4fm metal nitrogen pitting is caused by nitrogen gas (N
High melting point gold J4#! The compound is oxygen gas (OlJ is Ar
It is formed by adding it to an untrustworthy gas such as h.

なお、高融点金属酸化物は前記方法によシlX金属層を
形成した後に熱酸化法等により酸化物とすることも可能
である。
Incidentally, the high melting point metal oxide can also be made into an oxide by thermal oxidation method or the like after forming the IX metal layer by the above method.

以上の例はスパッターターゲットとして高融点金属を用
いた例であるが、先に述べた如き閥融点金属化合物もし
くは合金をターゲットとじてスノくノタリングヲ果厖す
ることによりても、該尚融点釜属化合物もしくは合金よ
pなる導体層又は杷一層が得られる。
The above example is an example in which a high melting point metal is used as a sputter target, but it is also possible to use a high melting point metal compound or alloy as a target to achieve a high melting point metal compound as described above. Alternatively, a conductive layer or a loquat layer made of alloys can be obtained.

以上側れの場合においてもスノ(ツタ・ターゲット(i
:純度99.999チ以上の純度とするときに、形成さ
れる4体躯又は絶縁層の純ft−9’j、’j99チ以
上とすることが可能で6夕、又、酩子ビーム蒸宥法につ
いても蒸発源を99.999−以上の純度とするときト
コ様の結果が得られる。
Even in the case of sideways, snow (ivy target (i)
: When the purity is 99.999cm or higher, the purity of the four-body structure or insulating layer to be formed can be ft-9'j,'j99cm or higher. Regarding the method, similar results can be obtained when the purity of the evaporation source is 99.999 or higher.

以上の如くにして形成されfc純1i99.999−以
上の導体ノー又は絶縁ノーはφずれもアルファ線放射−
がlδ’1lii!/”hour以下を示し、純度99
.9999%と得た例についてはアルファ巌放射量が1
01J61/ctll・hour以下を得る例も得られ
た。そしてこの導体層を半纏体記憶装置に通用して、1
0乃玉1O1I″IT4!度以下の高信頼度を得ること
ができた。
The fc pure 1i99.999 or more conductor or insulator formed as described above also emits alpha rays even if there is a φ deviation.
is lδ'1lii! /”hour or less, purity 99
.. For the example obtained with 9999%, the alpha ion radiation amount is 1
An example was also obtained in which less than 01J61/ctll·hour was obtained. Then, this conductor layer is used in a semi-integrated storage device, and 1
We were able to obtain high reliability of less than 0 degrees 1O1I''IT4! degrees.

以上説明した即く、本発明は、純度99.999−以上
の前記扁融点並属、又は咳高融点差属金含む合金もしく
は化合物よりなる1IA4I源又はスパッタ壷ターゲッ
トを用いる真!、にd法文はスバッタリ/グ法によ1純
度99.999チ以上の導体層又は絶縁4t−形成する
ことによシ、トリタム(Tb)2り2/(U)等のアル
ファ嶽奴耐吻質の含i菫を従来の1/10以−Fとし、
アルファ編放射によるソフト・工2−に関する信頼BL
:tlO倍以工高める効果を有する。
As described above, the present invention provides a method using a 1IA4I source or a sputtering target made of an alloy or compound containing metals with similar or high melting points having a purity of 99.999 or higher. , by forming a conductive layer or insulating layer with a purity of 99.999 or higher by the Subbattari/G method, alpha resistant materials such as tritum (Tb) 2 and 2/(U) etc. The quality of the violet is set to 1/10 or more of the conventional value,
Trust BL regarding software/engineering 2- by alpha edition radiation
:Has the effect of increasing tlO times more.

Claims (1)

【特許請求の範囲】 (1)  glVA、i、 jgVAfjj gvrA
ye 4 L < ハgVI族に属し、かつ、第4PM
期乃至第6A期に属する純度が99.999係以上の金
属、又は純度が99.999チ以上の該金4を含む合金
もしくは化合物で構成した導体層又は絶縁層を半導体基
板上に設けてなる半導体装置0 (21glVA族、!VA族t aiVIA族もL<、
4m)JIAに属し、かつ、第4fRIA乃至!X6周
期に属する純度が99.999−以上の金属、又は純度
が99.999−以上の該金属を含むせ薫もしくは化合
″at−蒸発源又はスパッタ・ターゲットとして、半導
体i板上に、該金属又は該金属を含む曾釡もしくは化合
物よりなる導体層又は絶縁層を、真空蒸着又はスパッタ
蒸着すること′ft籍砿とする半導体装置のJA:I!
Ly5法0 (3)  前記蒸発源又は前記スノ(ツタ・ターゲット
が該#L属を言む化合留よシ気相成長法によって形成さ
れたものであること′ft籍倣とする脣I/f請求の城
門第2現記−の半導体装置の製造方法。 (4)151記蒸発源又は前記スパッタ・ターゲットが
、ゾーンメルト法によりd[t99.999−以上とさ
れたものでるることを特徴とする特1ff−請求の範囲
第2現記−の半導体装置の製造方法。
[Claims] (1) glVA, i, jgVAfjj gvrA
ye 4 L < Belongs to the HagVI tribe and is the 4th PM
A conductive layer or an insulating layer made of a metal with a purity of 99.999% or higher belonging to the period to 6A period, or an alloy or compound containing the gold 4 with a purity of 99.999% or higher is provided on a semiconductor substrate. Semiconductor device 0 (21glVA group, !VA group taiVIA group also L<,
4m) Belongs to JIA and is from the 4th fRIA to! A metal with a purity of 99.999 or more belonging to the Or vacuum-depositing or sputter-depositing a conductive layer or an insulating layer made of a metal or a compound containing the metal.JA:I!
Ly5 method 0 (3) The evaporation source or the ivy target is formed by a compound distillation method or a vapor phase epitaxy method that refers to the #L group. A method for manufacturing a semiconductor device according to Claim No. 2 of the present invention. (4) The 151st evaporation source or the sputtering target is produced by a zone melting method to have d[t99.999- or more. A method of manufacturing a semiconductor device according to the second aspect of claim 1ff.
JP16125481A 1981-10-09 1981-10-09 Semiconductor device and preparation of the same Pending JPS5861666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16125481A JPS5861666A (en) 1981-10-09 1981-10-09 Semiconductor device and preparation of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16125481A JPS5861666A (en) 1981-10-09 1981-10-09 Semiconductor device and preparation of the same

Publications (1)

Publication Number Publication Date
JPS5861666A true JPS5861666A (en) 1983-04-12

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JP16125481A Pending JPS5861666A (en) 1981-10-09 1981-10-09 Semiconductor device and preparation of the same

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066425A (en) * 1983-09-22 1985-04-16 Nippon Telegr & Teleph Corp <Ntt> High-purity molybdenum target and high-purity molybdenum silicide target for lsi electrode and manufacture thereof
JPS60234364A (en) * 1984-05-07 1985-11-21 Toshiba Corp Semiconductor device
JP2002069624A (en) * 2000-08-30 2002-03-08 Toshiba Corp Sputtering target

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066425A (en) * 1983-09-22 1985-04-16 Nippon Telegr & Teleph Corp <Ntt> High-purity molybdenum target and high-purity molybdenum silicide target for lsi electrode and manufacture thereof
JPS60234364A (en) * 1984-05-07 1985-11-21 Toshiba Corp Semiconductor device
JP2002069624A (en) * 2000-08-30 2002-03-08 Toshiba Corp Sputtering target

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