JPS5858605U - controller - Google Patents

controller

Info

Publication number
JPS5858605U
JPS5858605U JP15474281U JP15474281U JPS5858605U JP S5858605 U JPS5858605 U JP S5858605U JP 15474281 U JP15474281 U JP 15474281U JP 15474281 U JP15474281 U JP 15474281U JP S5858605 U JPS5858605 U JP S5858605U
Authority
JP
Japan
Prior art keywords
integrator
differential amplifier
receives
output
reset circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15474281U
Other languages
Japanese (ja)
Inventor
晝馬　俊治
相川　正樹
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP15474281U priority Critical patent/JPS5858605U/en
Publication of JPS5858605U publication Critical patent/JPS5858605U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の且実施例を示す電気的接続図である
。第２図は、本考案の応用例を示す構成１ブロック図で
ある。　４ １・・・・・・差動増幅器、２・・・・・・積分器、３
・・・・・・比較、器、Ｒ１乃至Ｒ６・・・・・・抵抗
、Ｃ□、Ｃ２・・・・・・コンデンサ、ＳＷ・・・・・
・スイッチ。FIG. 1 is an electrical connection diagram showing an embodiment of the present invention. FIG. 2 is a block diagram of a configuration showing an application example of the present invention. 4 1...Differential amplifier, 2...Integrator, 3
...Comparison, device, R1 to R6...Resistance, C□, C2...Capacitor, SW...
·switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御対象物理量の目標値と測定値を受ける差動増幅器と
、該差動増幅器の出力を受ける積分器と、前記差動増幅
器及び積分器の各出力を加算した値が成る基準値と等し
くなるように積分器に制御電圧を印加するリセット回路
とを有し、該リセット回路の出力を前記積分器に断続し
て印加することによりＰ動作とＰＩ動作を選択的に行わ
しめることができるようにしたことを特徴とする調節計
。A differential amplifier that receives the target value and measured value of the physical quantity to be controlled, an integrator that receives the output of the differential amplifier, and a reference value that is the sum of the outputs of the differential amplifier and the integrator. and a reset circuit for applying a control voltage to the integrator, and by intermittently applying the output of the reset circuit to the integrator, the P operation and the PI operation can be selectively performed. A controller characterized by:
JP15474281U 1981-10-16 1981-10-16 controller Pending JPS5858605U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15474281U JPS5858605U (en) 1981-10-16 1981-10-16 controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15474281U JPS5858605U (en) 1981-10-16 1981-10-16 controller

Publications (1)

Publication Number Publication Date
JPS5858605U true JPS5858605U (en) 1983-04-20

Family

ID=29947335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15474281U Pending JPS5858605U (en) 1981-10-16 1981-10-16 controller

Country Status (1)

Country Link
JP (1) JPS5858605U (en)

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