JPS5857986A - Printer - Google Patents

Printer

Info

Publication number
JPS5857986A
JPS5857986A JP56157835A JP15783581A JPS5857986A JP S5857986 A JPS5857986 A JP S5857986A JP 56157835 A JP56157835 A JP 56157835A JP 15783581 A JP15783581 A JP 15783581A JP S5857986 A JPS5857986 A JP S5857986A
Authority
JP
Japan
Prior art keywords
signal
travelling
input
gate
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56157835A
Other languages
Japanese (ja)
Inventor
Yasushi Okamura
岡村 康
Tatsuo Tezuka
手塚 辰雄
Fumio Fukushige
福重 文夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56157835A priority Critical patent/JPS5857986A/en
Publication of JPS5857986A publication Critical patent/JPS5857986A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J29/00Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
    • B41J29/38Drives, motors, controls or automatic cut-off devices for the entire printing mechanism

Landscapes

  • Accessory Devices And Overall Control Thereof (AREA)
  • Character Spaces And Line Spaces In Printers (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE:To obtain a printer which can detect overload by generating a timing pulse in synchronism with a travelling of a printing head and utilizing the cycle of this pulse. CONSTITUTION:When a driving circuit 4 receives a driving control signal (a) from a CPU3 and energizes a motor and makes a printing head travel, a timing pulse is emitted from a timing pulse generator 1 with longer cycles at first, gradually shorter cycles secondly and steady-state cycles at last in synchronism with the travelling. A monostable multivibrator 6 to which the pulse is input makes L level output under the steady-state travelling, while a monostable multivibrator 7 to which the signal (a) is input outputs L level under nonsteady- state travelling immediately after the motor driving and H level output under steady-state travelling, while the outputs of the vibrator 6, 7 are input into an AND gate 8 and inhibit detection under nonsteady-state travelling immediately after the motor driving. When entering into the long pulse cycle due to an overload, the outputs of the vibrator 6 and gate 8 becomes H level and input into the AND gate 9 together with the signal (a), and a stop signal is transmitted from the CPU3 by an output of the gate 9.

Description

【発明の詳細な説明】 本発明は、印字ヘッドの走行に同期してタイミングパル
スを発生する印字装置1t+ζおいて、印字ヘッドが外
部からの制動力により一定スピード以下になったり、駆
動回路に異常が発圧しtコり等して印字ヘッドが停止し
た場合(以下オーバーロードと称す)の検出装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a printing device 1t+ζ that generates timing pulses in synchronization with the running of the print head. The present invention relates to a detection device for when the print head stops due to pressure generation and stiffness (hereinafter referred to as overload).

従来オーバーロードの検出方法として、印字ヘッド用駆
動モータとこのモータの@−回路との閾に抵抗を挿入し
、この抵抗の両端の電圧によって電流を検出し、この電
流によってモータの負荷を検出する方法がある。これに
は、抵抗分のロスを小さくするため、抵抗値はなるべく
小さいものを使用せねばならない。すると、過負荷等が
かかった場合の変動電圧は小さくなるので、増幅器の増
幅度も上げねばならなくなり、そのため回路の動作点の
バラツキも大きくなってくる。さらに、モータサーボ細
路の駆動方法をPWM方式にすると。
Conventional overload detection methods include inserting a resistor between the print head drive motor and the motor's @-circuit threshold, detecting the current based on the voltage across this resistor, and detecting the motor load based on this current. There is a way. For this purpose, in order to reduce resistance loss, the resistance value must be as small as possible. As a result, the fluctuation voltage when an overload or the like is applied becomes smaller, and the amplification degree of the amplifier must also be increased, which increases the variation in the operating point of the circuit. Furthermore, if the motor servo narrow path is driven by a PWM method.

積分回路も必要となってくる。An integrating circuit will also be required.

また、ヘッドがめる2点間を走行する平常の時間を設定
し、異常時にはその時間が経過してもヘッドが決めらn
た点へこないことをタイマーにより検知して行なう方法
でもある。しかし、これは異常が生じてオーバーロード
検出装置が動作するまでの時間がかかる。
In addition, the normal time for the head to travel between two points is set, and in the event of an abnormality, the head cannot be determined even after that time has passed.
It is also a method that uses a timer to detect when the target point has not been reached. However, this takes time until an abnormality occurs and the overload detection device operates.

本発明はこnらの問題を解消するものであり。The present invention solves these problems.

タイミングパルス信号の周期を利用してオーバーローF
を検出しようとするもので、以下本発明の構成をその一
実施例を示す図面に基づいて説明する。
Overlow F using the period of the timing pulse signal
The configuration of the present invention will be explained below based on the drawings showing one embodiment thereof.

ヘッドの走行に同期してタイミングパルスを発生するタ
イミングパルス発生部、(7)は前記タイミングパルス
発生部(1)の信号の周期を検出してオーバーロードを
検知するオーバーロード検m目u、ca>はプログラム
ストアード方式のマイクロプルセッサ(以下CPUと略
す)で、前記オーバーロード検出囲路(2)の信号を割
込みとして入力する。(至)は印により制御され、印字
ヘッドの停止時や起動時に上記オーバーロ」ド検出回路
(2)の信号を禁止するオーバーロードキャン七に回路
である。
A timing pulse generator (7) generates a timing pulse in synchronization with the running of the head, and (7) an overload detector (u, ca) that detects an overload by detecting the cycle of the signal of the timing pulse generator (1). > is a program stored type microprocessor (hereinafter abbreviated as CPU), which inputs the signal from the overload detection circuit (2) as an interrupt. (to) is an overload can circuit 7 which is controlled by a mark and inhibits the signal from the overload detection circuit (2) when the print head is stopped or started.

次iこ、上記構成の要部を電気−路で示した第2図およ
びタイムチャートで波形を示したN1図にもとづいて動
作を説明する。第2図において、第1図と同じ符号を付
した部分は111図のそOと同じJl成部である。CP
U(2)から第1図(荀の信号で示すように印字ヘッド
走行用モータの駆動囲路に)に駆動側−信号(il始点
&tIliiI図のムで示す)を送ると、モータは起動
し、印字ヘッドが走行する。
Next, the operation will be explained based on FIG. 2, which shows the main parts of the above-mentioned configuration as electrical paths, and FIG. N1, which shows waveforms as time charts. In FIG. 2, the parts with the same reference numerals as in FIG. 1 are the same Jl parts as those in FIG. 111. C.P.
When a drive-side signal (indicated by il start point & tIliiii in Fig. , the print head runs.

すると、こnと同期しているタイミングパルス発生部…
よりHa図(b)のタイミングパルスが出方される。こ
の信号は、起動直後は周期が長く、徐々に短か(なって
第1図のipで示さnる一定周期となり、モノステーブ
ルマルチバイブレータ(句へ入力される。このモノステ
ーブルマルチバイブレーク(11)のQ出力は第ME(
t)で示8tLるように第8図(締の波形の立上り1こ
よりトリガさtL、その後ある一定時間(Tcで示す。
Then, the timing pulse generator that is synchronized with this...
Therefore, the timing pulse shown in Ha diagram (b) is produced. This signal has a long cycle immediately after startup, and gradually becomes shorter (it becomes a constant cycle indicated by ip in Figure 1), and is input to the monostable multivibrator (11). The Q output of is the first ME (
As shown by 8tL in FIG.

)Lレベルとなる。ここでTcは1)より長く設定さn
てぃて、モータ起動後、第8図(荀のタイミングパルス
が一定周期ipとなる定常走行を開始すると、モノステ
ーブルマルチバイブレータ(6)のQ出力は第8図(c
)の様に、Lレベルになったままとなる。
) becomes L level. Here Tc is set longer than 1) n
After starting the motor, the Q output of the monostable multivibrator (6) will be as shown in Fig. 8 (c).
), it remains at L level.

また前記CPU(aJより出力される印字ヘッド走行ス
ピードの駆−11御信号はモノステーブルマルチバイブ
レータ(ηへも同時に伝えらイlる。このる出力は第$
図(優で示すように、第*回(a)の駆動側−信号が発
生すると同時にLレベルとなり、モータが定常走行を行
なってJ[8図(−のタイミングパルスの周期がipに
なる頃までLレベルを維持する(tBで示す)。このモ
ノステーブルマルチバイブレータ<1)からのQ信号と
前記モノステーブルマルチバイブレータ−)からのη信
号をANDゲート(8)へ号は禁止され、モータ躯動走
行開始点ムよりLレベルとなっている。ここで第8図の
B点でオーバーロードがかかり、モータの走行スピード
が低下し、第8図(b)のタイ、電スゲパルスの信号の
周期がTcより長(なると、前記モノステーブルマルチ
バイブレーク(2)の?出力は第@jN(c)のように
■レベJl/ トなり、ml囚(・)で示されるように
■レベルが^NDゲート(旬より出力される。この信号
は次段のANDゲート(旬へ入力、される、また前記C
Pυ(2)より出力される印字ヘッド走行用モータのK
m@御信号も入力されるため、出力にはgS図(ぎλで
示すようにオーバーロード時のみ麗レベルが出力さn。
In addition, the drive 11 control signal for the print head running speed output from the CPU (aJ) is simultaneously transmitted to the monostable multivibrator (η.
As shown in Figure (Excellent), at the same time as the drive side signal of the The Q signal from this monostable multivibrator (<1) and the η signal from the monostable multivibrator (1) are sent to the AND gate (8). It is at the L level from the dynamic traveling start point. Here, an overload is applied at point B in Fig. 8, the running speed of the motor decreases, and the period of the signal of the tie and electric Suge pulse shown in Fig. 8 (b) is longer than Tc (when the monostable multi-by-break ( The ?output of 2) becomes the ■level Jl/ as shown in the th. AND gate (input to and done by the above C)
K of the print head running motor output from Pυ(2)
Since the m@ control signal is also input, the output is at the high level only in the event of overload, as shown in the gS diagram (g).

この信号は前記cruに)g:#lり込み信号として入
力され、 crυ(3)より直ちにモータ停止信号が出
力されるため、印字ヘッドはjIB図の5点で停止する
This signal is inputted to the above-mentioned cr as the input signal, and since the motor stop signal is immediately output from crυ(3), the print head stops at five points in the jIB diagram.

以上の様に2本発明によnば、タイミングパルス信号の
周期よりオーバーロードの検出を行ない。
As described above, according to the present invention, overload is detected from the period of the timing pulse signal.

印字ヘッドが起l1llさnて定常走行に移る前の一定
時間はn釦検出を禁止するので、タト部から制動力が印
字ヘッドに加わったり、モータ駆動回路等に異常が生じ
たときのみ直ちに精度よく仁nを検出できる。また本実
施例のようにこの検出出力をCPUに割り込み信号とし
て直接入力すると、 CPUは実行中の命令を中断して
あらかじめ定められた別プログラムを実行処理するため
、応答性が早く、その効果は顕著である。
Since the n button detection is prohibited for a certain period of time before the print head wakes up and moves to normal running, the accuracy can be immediately checked only when braking force is applied to the print head from the print head or an abnormality occurs in the motor drive circuit, etc. It can be easily detected. Furthermore, when this detection output is directly input to the CPU as an interrupt signal as in this embodiment, the CPU interrupts the instruction being executed and executes another predetermined program, resulting in faster response and less effective results. Remarkable.

【図面の簡単な説明】 N1図は本発明の一実施例のブロックダイヤグラム、j
Iz図はその要部の電気回路内、第8因はタイムチャー
トであるC (i)−タイミングパルス発生部、(2)・・・オーバ
ーロード検出回路、 (3) −CPIJ 、 (4)
モータ駆動回路1(5J−$ −/(−ロードキャンセ
ヲ回路
[Brief Description of the Drawings] Figure N1 is a block diagram of an embodiment of the present invention.
The Iz diagram shows the main part of the electrical circuit, and the eighth factor is the time chart.
Motor drive circuit 1 (5J-$ -/(-load cancel circuit

Claims (1)

【特許請求の範囲】[Claims] 1、印字ヘッドの走行に同期してlタイミングパルスを
発生するパルス発生部を設け、ヘッドの走行時の異常を
前記タイミングパルスの周期を利用して検出する検出回
路を設け、印字ヘッドが定常走行中のみ前記検出回路が
動作するようにしたことを特徴とする印字装置。
1. A pulse generator is provided that generates a timing pulse in synchronization with the running of the print head, and a detection circuit is provided that uses the period of the timing pulse to detect an abnormality when the head is running, so that the print head is running normally. A printing device characterized in that the detection circuit operates only inside.
JP56157835A 1981-10-02 1981-10-02 Printer Pending JPS5857986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56157835A JPS5857986A (en) 1981-10-02 1981-10-02 Printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56157835A JPS5857986A (en) 1981-10-02 1981-10-02 Printer

Publications (1)

Publication Number Publication Date
JPS5857986A true JPS5857986A (en) 1983-04-06

Family

ID=15658369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56157835A Pending JPS5857986A (en) 1981-10-02 1981-10-02 Printer

Country Status (1)

Country Link
JP (1) JPS5857986A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60187578A (en) * 1984-03-07 1985-09-25 Fujitsu Ltd Printer
JPS61110561A (en) * 1984-11-06 1986-05-28 Matsushita Electric Ind Co Ltd Printer controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60187578A (en) * 1984-03-07 1985-09-25 Fujitsu Ltd Printer
JPH0354638B2 (en) * 1984-03-07 1991-08-20
JPS61110561A (en) * 1984-11-06 1986-05-28 Matsushita Electric Ind Co Ltd Printer controller

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