JPS5856527A - Logical circuit - Google Patents

Abstract

PURPOSE:To simply connect devices with different bits, by providing a multiplexer selecting an arbitrary data from a plurality of data and a demultiplexer giving an output the data to an arbitrary output erminal for a logical circuit having a bidirectional driver. CONSTITUTION:With a terminal CS0 at L level, control inputs 44 and 45 of tri-state buffers TSB14, 18 inputted via an inverter IV39 go to H and the TSB14, 18 output signals inputted from a terminal C to terminals D0, D1. Since a control input 47 of a TSB28 is at L via an IV42, the output of a TSB28 has a high impedance. With the terminal CS0 at H level and a terminal CS1 at L level, signals given to the terminal D0 are outputted to the terminal C via an AND gate 12, an OR gate 34 and the TSB28, and with the terminal CS1 at H level, signals given to the terminal D1 are outputted to the terminal C via an AND gate 16, a gate 34 and the TSB28. Thus, the circuit performs the operation of a multiplexer or demultiplexer depending on the H, L level of the terminal CS0.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit having a bidirectional line of data nodes 9. Conventionally, in a device having a 16-pit data node line, a memory such as a random access memory (RA) is used.
When using M), it was necessary to prepare a dedicated 16-pit memory. However, manufacturing a new memory board has the problem of increasing costs. In addition, for example, 8
This was disadvantageous compared to using bits of memory.

Furthermore, when an 8-bit input/output device is controlled by a 16-bit control device, only 8 bits out of 16 bits are used to control the input/output device, or 16-bit, 8-bit, etc.
A bit converter had to be used. The former has a problem in that the efficiency of the pass line is low because there are 8 unused bits, and the latter requires dedicated converters each having a multiplexer and a demultiplexer.

The present invention solves these problems, and its purpose is to provide a logic circuit that allows a device having, for example, a 16-bit bidirectional path line to be used with an 8-bit bidirectional path line. It's about doing.

The feature of the present invention resides in a logic circuit having a bidirectional driver, which includes a multiplexer for selecting arbitrary data from several pieces of data, and a demultiplexer for outputting the data to an arbitrary output terminal.

Hereinafter, detailed explanation will be given using examples of the present invention.

FIG. 1 shows logic elements used in the logic circuit of the present invention.
Figure 1 a) is a tri-state buffer, and as shown in Figure 1 (8), when the control input l is L, the output 3 is high impedance (Hlgh-Z) regardless of the input 2 signal.
), and when the control force 1 is H, the output 3 becomes the same signal as the signal input to the input 2.

That is, when input 2 is L, output 3 is L1, and when input 2 is H, output 3 is H.

Figure 1b) is a two-person combination r-h, and the truth value is the first
As shown in Table b), when the first input 4 and the second input 5 are both H, the output 6 is H; otherwise, the output 6 is ! : ru.

Figure 1 a) V12 human power or agut, truth value is 1st
As shown in Table C), when the first input cuff and the second input 8 are both L, the output 9 becomes L; otherwise, the output 9
becomes H.

Figure 1 d) shows that the output is in the output mode, and as shown in Table 1 d), when the human power 10 is H, the output 11 is
When the input 10 is low, the output 11 is high.

FIG. 2 shows a first embodiment of the invention. Terminal D is connected to the first input 13 of the ANDFF-) 12 and to the output 15 of the DRY state gate FF 14.

The terminals R and R are connected to the first input 17 of the ANDR gate 16 and the output 19 of the triste amplifier 18.

Terminal C8I is input to the input 21 of the inverter 20, and its output 22 is input to the second input 23 of the ANDff-to 12 and the input 25 of the inverter 24.

The output 26 of the inverter 24 is the second
enters input 27 of. Terminal C is tri-state buffer 2
8 and inputs 30 and 31 of the dry state buffers 14 and 18, respectively.

'T7'F"?'-1" 12, 16+Z) Output 32
．． 33Fi#7r-to 34's 1st. Second input 35.3
6 respectively, and their outputs 37 enter inputs 38 of tristate/cutoff 28. Terminal C8O goes into input 40 of inverter 39, and its output 41 goes to inverter 4
2 input 43 and dry state node 7714 r1
8 control input 44.45. The output 46 of the inverter 42 is connected to the control input 47 of the tri-state buffer 28.

When terminal C8O is L, tri-state buffer 14°18
Since the control inputs 44, 45 of the tri-state buffers 14, 18 output the signal input from the terminal C to the terminal D6tD1. At this time, since the human power 47 for controlling the tri-stepper and fan 28 is L, the output is high impedance.

When the terminal C8O is at H, the tri-state sofa 28 outputs to the terminal C, contrary to when C8O is at L.

In other words, the terminal DolD1 is switched by the signal input from the terminal C8I to output the terminal CK ratio, and the terminal C
When the terminal C81 is L, the signal input to the terminal Do is output to the terminal C, and when the terminal C81 is H, the signal input to the terminal D1 is output.

Table 2 shows the truth values of FIG.

jig2 table The circuit shown in Figure 2 has terminal C as is clear from Table 2.
When 8O is LO, multiplexer, terminal cs.

When is H, it operates as a multiplexer.

FIG. 3 is a @2 embodiment of the present invention. The points that differ from Fig. 2 are the dry state and control inputs 4 for F14 and F18.
4.45 is input via AND gates 48 and 49.

That is, the output 41 of the inverter 39 is the AND gate 4
8.49 first dart 50.51, inverter 20
．． How to get 24 22.26 is and f-? 48.49 is connected to the second dart 52.53 and further its output 54
．． 55 are respectively connected to control inputs 44.45 of tri-state buffers 14.18.

The second embodiment operates in the same way as the first embodiment (FIG. 2) when the terminal cso is at H, that is, when it is a multiplexer.

When CSO is L, unlike the first embodiment, the output terminal can be selected by the Cal input signal.

Table 3 shows the truth table of the second embodiment.

Table 3: When terminal C8O is L and terminal C81 is L, terminal C is input and terminal RI is output. When terminal C8.0 is L and terminal C8I is H, terminal C is input and terminal DI is is the output.

FIG. 4 shows an application example of the present invention, in which the address Add of the arithmetic and control block 56 is connected to the memory block 58 via the read/write R1/vS chip select csFi path line 57. The 16-bit data input/output 59 of the calculation and control block 56 is connected to the logic circuit 60 of the present invention.
is connected to D.~D1-. Memory processor, 8 pins of ri 58, tome data input/output 61 are C to C of logic circuit 60
Connected to 1. Further, from the arithmetic and control processor 56, a signal for controlling pits is input to C81, and a signal for controlling the data direction is input to C8O. Arithmetic and Control Pro, Ri5
6 has a 16-bit input/output, that is, a data node, but the memory 58 has an 8-bit data node.In this way, devices with different bidirectional data bus bits can be used. The logic circuit 60 of the present invention is configured to couple the data direction control signal and the bit control signal with C8O and 08.
1 can be easily combined by inputting K.

In addition, 1st. In the second embodiment, the data terminal FiDo a
D, , C, but as in the application example, it is also possible to convert multiple data into halves, that is, 16-bit data bus and 8-bit data bus. Rather than converting to a bit data bus, for example, 16 bits can be converted to 4 bits.

It is also possible to convert 32 bits to 4 bits.

As explained above, the present invention is intended to easily connect devices that cannot be connected due to differences in bidirectional path bits. By doing so, a more simplified logic circuit is possible.

[Brief explanation of drawings]

FIG. 1 is a logic element diagram showing a logic element, FIGS. 2 and 3 are circuit diagrams showing embodiments 1 and 2 of the present invention, and FIG. 4 is a configuration diagram showing an application example of the present invention. 14.18.28... Tri-state buffer, 12
．． 16.48.49...and dirt, 34...or dirt, 20,24,39.42...inverter. Figure 2

Claims (1)

[Claims] 1) A logic circuit having a bidirectional driver, characterized in that it has a multiplexer that selects arbitrary data from several pieces of data, and a demultiplexer that outputs the data to an arbitrary output terminal.・2) The logic circuits are the same as No.9. The logic circuit according to claim 1, wherein the logic circuit is housed in a cage.