JPS5856453A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable to manufacture a semiconductor memory with an ordinary process by simplifying the structure of the memory having memory cells of the type for detecting the presence or absence of a stored charge as the variation in the gate voltage of a transistor. CONSTITUTION:(1) When the fourth conductive wiring 22 as writing time wiring bit line is at high voltage and the first conductive wiring 15 as writing word line is at high voltage, the electrons at the first impurity injection region 16 as n<+> type information storage region become positive high voltage state. (2) When the wiring 15 is reduced to low voltage in the state that the holding time-impurity region 16 and the second conductive wire 17 become high voltage, the state can be maintained. (3) When the conductive wiring 22 as X-direction read- out line is at high voltage while the reading-out time-conductive wiring 15 is maintained at low voltage and the third conductive wiring 20 as Y-direction read-out line is reduced to low voltage, a current flows between the second impurity region 18 and the third impurity region 19. The presence and absence of the current may be corresponded to ''1'',''0''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides MIS dynamic RAM (Random
This invention relates to an improvement of a semiconductor memory device called AccyzMa*ory.

Conventionally, typical semiconductor memory devices of this type include:
A so-called memory cell having one transistor and one capacitor is known.

In general, semiconductor devices are becoming more and more densely packed, and the storage devices are no exception. One way to increase the density of this type of storage device is to make memory cells smaller, and as a result, memory capacitors have also become smaller.

However, if the memory capacitor is made smaller, the amount of stored information charge will naturally decrease. Therefore, it is difficult to read information accurately due to the influence of parasitic capacitance of the bit line.
:Become. Therefore, increasing the sensitivity of the sense amplifier, countermeasures against noise, etc. become problem C2, but there are limits to countermeasure C2 that depends on this. In addition, making memory capacitors smaller is also important because electrons and
This results in a loss of resistance to the destruction of stored information due to the generation of hole pairs.

Other types of storage devices that overcome these shortcomings have been actively developed, examples of which are shown in FIGS. 1 and 2.

Note that FIG. 2 is a sectional view of FIG. 1 viewed from the side.

In the figure, 1 is a P-type silicon semiconductor substrate, 2 is a silicon dioxide insulating film for a field, 3 is a rectangular layer, 4 is a P-type low concentration channel layer, 5 is a gate insulating film, and 6 is a polycrystalline film. A silicon gate electrode, 7 a 1-type source region, and 8 a ♂-type drain region, respectively.

In this device, voltages of various levels are applied to the gate electrode 6. For example, it is in a neutral state at zero volts, but when this is changed to a negative voltage C2, the channel layer 4
The holes in the insulating film 2 flow out across the taper (of the junction formed between the substrate 1 and the well 3) of the insulating film 2, as shown by the arrow in FIG. So,
The channel layer 4 is in a state where there are few holes. Therefore, the threshold voltage vth of the transistor changes between the neutral state and the state with few holes, and by sensing this, information "1" and "0" are known. be.

However, this memory device requires power supplies of various levels to operate, the structure of the memory cell is complex, and pack gate bias cannot be applied. Just enough to ground.

The present invention simplifies the structure of a semiconductor memory device having a memory cell of a type in which the presence or absence of accumulated charge is detected as a change in the gate potential of a transistor, so that it can be manufactured using a normal process. will be explained in detail.

FIG. 3 is a plan view of essential parts of an embodiment of the present invention, and FIG. 4 is a sectional view taken along line AA' in FIG.

In the figure, 11 is a P-type silicon semiconductor substrate, 12 is a P-type silicon semiconductor substrate, and 12 is a P-type silicon semiconductor substrate.
+ type channel stopper, 13 is a field silicon dioxide insulating film, 14 is a gate insulating film, 15 is a first conductive line made of polycrystalline silicon and is a write word line, 16
is the first impurity-introduced region which is an n+ type information storage region, 1
7 has one end connected to the information storage area 16 and the other end connected to the electrical C
2. A second conductive line made of polycrystalline silicon which is a floating readout gate electrode; 18 is a second impurity doped region which is a C-type information writing and reading operation common region; 19;
20 is a third conductive line made of polycrystalline silicon which is a Y-direction read line, 21 is a phosphosilicate glass film, and 22 is a write bit line. A fourth conductive line made of aluminum, which also serves as an X-direction readout line, is shown. It is also possible to increase the capacitance by forming a P-type region close to the bottom of the first impurity-introduced region 16, which is a --type information storage region.

The operation of this embodiment is as follows.

(1) When writing, if the fourth conductive line 22, which is a write bit line, is at a high potential, and the first conductive line 15, which is a write word line, is at a high potential C2, the first impurity, which is a - type information storage region, is Introduction area 16 (
Since the electrons in the second impurity introduction region 18C are sucked out, the first impurity introduction region 16 becomes in an electron-deficient state, that is, in a positive high potential state. First impurity region 16
6: is connected to one end of the second conductive line 17, which is a successive gate electrode, so it also has a high potential.

(2) When holding, the first impurity region 16 and the second conductive line 17 are at a high potential 6 as described above, and the first conductive line 15, which is a write word line, is set to a low potential. Therefore, maintain that state.

(3) At the time of continuous reading, while keeping the first conductive line 15 at a low potential, the fourth conductive line 22, which is an When the conductive wire 20 is placed at a low potential (=
The second conductive line 17, which is a read gate electrode, is at a high potential C:
Therefore, a channel is formed between the second impurity region 18 and the third impurity region 19, and a current flows.

Whether or not the current 6 flows by applying a voltage between the fourth conductive wire 22 and the third conductive wire 20 is determined by the second conductive wire 17.
Since it depends on whether the current is at high or low level, the presence or absence of the current can be made to correspond to the information "1" and "O1'."

FIG. 5 is a plan view of the main part of another embodiment, and this embodiment has a smaller size as a whole by sharing a part of the area for two memory cells, and also has a simpler structure. It has become. In addition, in FIG. 3 and FIG. 4C, the same symbol as the one shown indicates the same part, and the part indicated by adding "'" to the symbol indicates the same part of the other memory cell. ing.

In this way, only one third impurity region 19 is required for every two memory cells.

As can be seen from the above description, according to the present invention, the first, second, . A third impurity doped region is provided, the first impurity doped region and the second impurity doped region. A conductive line of IJl corresponding to the third impurity introduced region (Ni-gate electrode C) is provided, and one end is connected to the impurity introduced region of $1 between the second impurity introduced region and the third impurity introduced region. A second conductive line corresponding to the gate electrode is provided, and separate C'-4th and third conductive lines are connected to the second and third impurity-introduced regions to form a memory cell. Changing the threshold voltage of the transistor formed in the third impurity doped region depending on the presence or absence of information charge in the first impurity doped region and detecting it 1:
” and “0”.The effects obtained by this are listed below.

C) The level difference between the "0" state and the "1" state is large, and the resistance to noise is large.

((b) Since the successive output of information depends on the detection of electric potential, there is almost no effect even if the amount of charge handled becomes minute. Therefore, it is necessary to reduce the size, especially the information storage area. I can do it.

(c) Information is read out non-destructively.

2) Since the structure is simple, special processes such as forming a well of the opposite conductivity type to the substrate are not required.

(e) Since the information storage area may be small, it is highly resistant to soft errors caused by alpha rays.

(f) The operating principle is relatively simple and does not require a special level of voltage.

[Brief explanation of the drawing]

1 and 2 are sectional views of the main parts of the conventional example, FIGS. 3 and 4 are a plan view and sectional view of the main parts of one embodiment of the present invention, and FIG. 5 is a sectional view of the main parts of another embodiment. FIG. Figure 4: 11 is a substrate, 12 is a channel stopper, 13 is an insulating film, 14 is a gate insulating film, 15 is a first conductive line, 16 is a first impurity doped region, 17 is a second conductive film 18 is an impurity introduced region of IJ2, 19 is a third impurity introduced region, 20 is a third conductive line, and 22 is a fourth conductive line. Patent applicant Fujitsu Ltd. Agent Patent attorney Gobe Tamamushi (5 others) Figure 1 Figure 2 Figure 3 Figure 4 Figure 0 Figure 5

Claims (1)

[Claims] a semiconductor substrate of one conductivity type; first, second, and third impurity doped regions of opposite conductivity types formed on the semiconductor substrate and facing each other with a predetermined interval; the first impurity doped region; a first conductive line for forming a channel between the region and the second and third impurity doped regions, one end connected to the first impurity doped region and the other end electrically floating; Between the second impurity introduced region and the third impurity introduced region (=second conductive line for forming a channel, said sixth impurity introduced region) A semiconductor memory device comprising a fourth conductive line connected to the second impurity doped region and acting during information convolution and when information is successively output.