JPS5856448U - flat semiconductor stack - Google Patents

flat semiconductor stack

Info

Publication number
JPS5856448U
JPS5856448U JP14994681U JP14994681U JPS5856448U JP S5856448 U JPS5856448 U JP S5856448U JP 14994681 U JP14994681 U JP 14994681U JP 14994681 U JP14994681 U JP 14994681U JP S5856448 U JPS5856448 U JP S5856448U
Authority
JP
Japan
Prior art keywords
flat semiconductor
semiconductor stack
flat
insulator
cooling bodies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14994681U
Other languages
Japanese (ja)
Inventor
武仲 雅弘
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP14994681U priority Critical patent/JPS5856448U/en
Publication of JPS5856448U publication Critical patent/JPS5856448U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

・第1図は従来の平形半導体スタン′りの側面図、第2
図は本考案の実施例による平形半導体スタックの側面図
である。     − 1・・・・・・平形半導体素子、2・・・・・・冷却体
、3・・・・・・絶縁物、4・・・・・・枠体、5・・
・・・・絶縁軸、6・・・・・・ナツト、7・・・−・
・押し板、8・・・・・・弾性体絶縁カバー。
・Figure 1 is a side view of a conventional flat semiconductor stand, Figure 2 is a side view of a conventional flat semiconductor stand.
The figure is a side view of a flat semiconductor stack according to an embodiment of the present invention. - 1... Flat semiconductor element, 2... Cooling body, 3... Insulator, 4... Frame, 5...
...Insulated shaft, 6...Nut, 7...-
- Push plate, 8...Elastic insulation cover.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 両端の電極面に冷却体を当接した平形半導体素子を絶縁
物を介して締合わせてなる平形半導体スタックにおいて
、両端が上記冷却体に取付けられた弾性材よりなる絶縁
物カバーにより前記平形半導体素子の外周を覆うように
したことを特徴とする平形半導体スタック。     
  −
In a flat semiconductor stack formed by tightening flat semiconductor elements with cooling bodies in contact with the electrode surfaces at both ends via an insulator, the flat semiconductor elements are held at both ends by insulator covers made of an elastic material attached to the cooling bodies. A flat semiconductor stack characterized by covering the outer periphery of the semiconductor stack.
JP14994681U 1981-10-08 1981-10-08 flat semiconductor stack Pending JPS5856448U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14994681U JPS5856448U (en) 1981-10-08 1981-10-08 flat semiconductor stack

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14994681U JPS5856448U (en) 1981-10-08 1981-10-08 flat semiconductor stack

Publications (1)

Publication Number Publication Date
JPS5856448U true JPS5856448U (en) 1983-04-16

Family

ID=29942699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14994681U Pending JPS5856448U (en) 1981-10-08 1981-10-08 flat semiconductor stack

Country Status (1)

Country Link
JP (1) JPS5856448U (en)

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