JPS585601B2 - Hatsushin Kinokan Shiseigiyosouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monitoring and control device for an oscillator equipped with main and sub oscillation frequency sources.

In general, high-precision timekeeping devices use some kind of checking means to monitor frequency fluctuations.For example, in devices that use a crystal oscillator as a frequency source, the oscillation frequency is lowered to an appropriate value by a frequency divider. Set the maximum permissible amount of fluctuation frequency in advance on a preset counter, etc.

Then, each of the multiple digits, for example, six digits, of the frequency that has dropped above is compared with the set value, and if the set value is exceeded, an alarm is issued to notify that there has been a frequency fluctuation that exceeds the permissible value. It was something.

However, although this is highly accurate, it requires a preset counter with many digits and a comparator circuit for it, which makes the circuit complex.

The present invention eliminates the above deficiencies and provides a device that calculates the difference in the oscillation frequencies of the main and sub oscillators, monitors the frequency fluctuation error, and switches to the sub oscillator when the main oscillator stops.

This will be explained below based on the drawings.

1 is a crystal oscillator for the main oscillator that generates the reference frequency;
2 is a crystal oscillator for use as a sub-oscillator that generates an oscillation frequency similar to that of the crystal oscillator 1;

3 and 4 are frequency dividers that divide the positive and secondary oscillation frequencies, respectively; 5 is a one-digit counter; 6 is a latch circuit; and 7 is a preset counter that sets the maximum frequency of allowable error.

Reference numeral 8 denotes a comparison circuit that generates an output when the fluctuating frequency stored in the latch circuit 6 exceeds the set value of the preset counter 7.

9 is a display device that displays the fluctuating frequency stored in the latch circuit 6; 10 is an alarm device that receives the output of the comparator circuit 8 and generates an alarm.

11 is an oscillation stop detection circuit of the crystal oscillator 1, which includes diodes d1 and b2, an inverter v1, and capacitors C1 and C.
2, resistors R1 and R2, and a gate circuit G1.

12 is an oscillation stop detection circuit for the crystal oscillator 2, which includes diodes d3 and d4, an inverter v2, and capacitors C3 and C.
4, resistors R3 and R4, and a gate circuit G2.

13 is a frequency difference detection circuit that generates a difference output between the divided output frequencies of the primary and secondary crystal oscillators 1 and 2, and is composed of a gate circuit G3 having an exclusive NOR function and a low-pass filter circuit consisting of a resistor R5 and a capacitor C5. .

G4...G3 is a gate circuit, v3 is an inverter, 14
is an alarm notification device that generates an alarm when either one of the crystal oscillators 1 and 2 stops oscillating.

15 is an external device such as a counter.

Next, the operation will be explained.

First, the operation of switching to the other crystal oscillator when one of the crystal oscillators 1 and 2 stops oscillating will be described.

During normal oscillation of crystal oscillator 1, capacitor C1 and resistor R
A logically high level DC voltage is generated at the output of each integrating circuit of 1, capacitor C2, and resistor R2, and gate circuit G
1 output is held at a low level.

When the crystal oscillator 1 stops oscillating, its output becomes either a high voltage level or a low voltage level.

When the voltage is at a high voltage level, a charging voltage is applied to the capacitor C1, and the output is maintained at the same high voltage level as during normal oscillation.

However, since the output of the crystal oscillator 1 is inverted by the inverter v1 and the application of the charge voltage to the capacitor C2 is blocked by the diode d2, the charge charged in the oscillator is discharged.
The input of gate circuit G1 becomes low level.

Therefore, its output becomes high level and activates the alarm notification device 14 via the gate circuit G4 to notify that the oscillation has stopped.

Note that if the output of the crystal oscillator 1 is at a low level when the crystal oscillator 1 is stopped, the level applied to the input of the gate circuit G1 is reversed, and the output of the gate circuit G1 becomes high level and generates an alarm as described above.

On the other hand, the high level output of the gate circuit G1 is the gate circuit G7.
is opened to allow the divided output of the crystal oscillator 2 to pass through.

Since a low level obtained by inverting the output of the gate circuit G1 by the inverter v3 is applied to one input of the gate circuit G5, the output of the gate circuit G5 is at a high level.

Therefore, the gate of the gate circuit G6 is opened by the output thereof, and the oscillation output of the crystal oscillator 2 that has passed through the gate circuit G7 described above passes through the gate circuit G6 and is supplied to an external device 15 such as an external counter.

Next, a case where a fluctuation occurs in the oscillation frequency of the crystal oscillators 1 and 2 will be explained.

In order to simplify the explanation, the explanation will be given below based on specific numerical values.

The oscillation frequency of crystal oscillator 1 is 5 MHz, the oscillation frequency of crystal oscillator 2 is 5 MHz during normal operation, and its fluctuation frequency is 50 MHz.
It is assumed that the frequency is 0 Hz and the frequency division ratio of frequency dividers 3 and 4 is 1/102.

The frequencies of crystal oscillators 1 and 2 are divided by frequency dividers 3 and 4, respectively, to 5×104Hz and (5×104+5)H.
Becomes z.

These frequencies are mixed in a frequency difference detection circuit 13 to generate a frequency of 5 Hz at its output.

Take out a 1 second width pulse from frequency divider 3 and gate circuit G
8 for the same time, and the counter 5 receives 5Hz, i.e. 5
Count the pulses.

After this counting, the above counted value is read into the latch circuit 6, and this value is displayed on the display device 9.

Further, the output of the latch circuit 6 is compared with a set value of a preset counter 7 in a comparator circuit 8, and when it exceeds the set value, an output is generated in the comparator circuit 8 and an alarm is generated in an alarm device 10.

By repeating the cycle, an accuracy of 10-4 can be measured by monitoring any part of the range with a single digit value.

As described in detail above, the present invention divides the frequency of an oscillator whose frequency accuracy is approximated by a predetermined ratio and lowers the number of digits to detect accuracy. Alternatively, it is possible to easily detect a deviation in the frequency division of a frequency divider, and there is no need to synchronize the oscillation frequency, which has extremely remarkable effects.

Furthermore, when one oscillator stops, the other oscillator quickly switches to avoid frequency interruption.

[Brief explanation of drawings]

The drawing is an electrical circuit diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Crystal oscillator, 2... Crystal oscillator, 3... Frequency divider, 4... Frequency divider, 5... Counter, 6... Latch circuit, 9... Display device, 13...Frequency difference detection circuit.

Claims (1)

[Claims] 1 A main oscillator and a sub oscillator whose frequency accuracy is close to each other, a frequency divider that reduces the output frequency of both oscillators to a predetermined frequency division ratio according to the set frequency accuracy, and a frequency divider that reduces the output frequency of both oscillators to a predetermined frequency division ratio according to the set frequency accuracy. A frequency difference detection circuit that extracts the difference frequency, a counter that counts the output frequency of this frequency difference detection circuit, an oscillation stop detection circuit that detects the output state when the main oscillator stops oscillating and generates an output, and a counter that counts the output frequency of the frequency difference detection circuit. An oscillator monitoring and control device consisting of a gate circuit that allows the output of the sub-oscillator to pass through the output of the circuit.