JPS585574B2 - Fukabuntan Seigiyo Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a load sharing control circuit in a parallel operation system for power supplies such as an inverter, a DC stabilized power source, and an AC stabilized power source.

When a plurality of power supply devices supply power to a common load, it may be desirable to share the load at a predetermined ratio, for example, equally.

In such a case, the load current is generally detected by a current transformer CT or the like, and the load current is adjusted to a predetermined ratio.

FIG. 1 schematically shows a circuit for operating inverters in parallel.

In this drawing, 1 and 2 are inverters, 3 is a common load, 4 and 5 are switches for selectively connecting inverters 1 and 2 to load 3, and 6 and 7 are for detecting load current. A current transformer, 8 is a load sharing amount detection circuit, 9 and 10 are inverter control circuits, respectively, and a differential amplifier 11.
, a comparator circuit 12, a differential circuit 13, and a phase shifter 14.

FIG. 2 shows an example of inverters 1 and 2 in FIG. 1, in which four thyristors 23a, 23b, 23ct23a are connected in a bridge configuration between DC power supply terminals 21 and 22. One end of the output transformer 24 is the thyristor 2
Commutation reactor 25 connected between 3a and 23b
The other end of the output transformer 24 is connected to the intermediate tap 28 of a commutation reactor 27 connected between the thyristors 23c and 23d.

In addition, 29at29b, 29c and 29a are commutating capacitors 30at30b730c and 30d are diodes,
30 is an output terminal.

To operate this inverter, thyristors 23a to 2
A gate signal as shown in FIGS. 3A to 3D is applied to the gate 3d.

As a result, the output voltage in the first direction is obtained from the terminal 31 when both thyristors 23a and 23a are in the on state, and the output voltage in the second direction is obtained when both the thyristors 23b and 23c are in the on state. is obtained.

That is, an output voltage as shown in FIG. 3E is obtained.

When controlling the pulse width with this circuit, the thyristor 23
The phases of the gate signals of thyristors a and 23b are fixed, and the phases of the gate signals of thyristors 23c and 23d are changed based on the fixed phase gate signals of thyristors 23a and 23b.

As a result, the output pulse width changes from the waveform shown by the solid line to the waveform shown by the dotted line, for example.

When changing from the state shown by the solid line to the state shown by the dotted line in FIG. 3E, the phase is delayed and the load sharing becomes smaller.

Therefore, load sharing is adjusted by adjusting the phase.

FIG. 4 is a circuit diagram showing in detail the conventional load sharing amount detection circuit 8 shown in FIG.

The schematic configuration of this load sharing amount detection circuit 8 includes a current transformer 6,
Voltage E012Eo based on each load current detected in 7
2 generates an output voltage el)e2 that commands load sharing.

In Fig. 4, ECJjE02 is a voltage corresponding to the current value detected by current transformers 6 and 7, D and ~D8 are rectifying diodes, R and ~R8 are resistances %Cj, and C2 is a smoothing capacitor. 41 is an output terminal that outputs the voltage e1 across the resistor R4, and 42 is an output terminal that outputs the voltage e2 across the resistor R5.

Further, S1 and S2 are switches that operate in conjunction with switches 4 and 5 in FIG. 1, and DET1 and DET2 shown surrounded by dotted lines are first and second detection circuits.

Next, the operation K will be described when the conventional load sharing amount detection circuit 8 shown in FIG. 4 is used in the circuit shown in FIG.

Now, if power is being supplied to the load 3 only by the inverter 1, the switch 4 is closed and the switch S1 is closed.
is closed.

Ikegata, switch 5 and switch S2 are open.

In this case, the voltage Eol from the output of the current transformer 6 is rectified by diodes D1 to D4, divided by a voltage dividing circuit made up of resistors R1 and L2, and then smoothed by a smoothing circuit made up of resistor R3 and capacitor C1 to create a direct current. becomes.

Therefore, a DC voltage appears at point A, but since switch S2 is open, no current flows through resistors R, , R, and voltages e1 and e2 at output terminals 41 and 42 are zero.

Therefore, load sharing control is not performed.

Next, the explanation at the time of starting load sharing will be left behind, and the operation during load sharing will be described first.

When the switches 4 and 5 and the switches S1 and S2 are respectively closed to perform load sharing control, the output currents of the inverters 1 and 2 are detected by the current transformers 6 and 1, respectively, and the corresponding voltages Eol and Eo2 is load sharing detection circuit 8
added to.

The voltages Eo1 and Eo2 are converted into DC voltages through a rectifier circuit and a smoothing circuit.

The voltage VA at point A corresponds to voltage Eo1, and the voltage VB at point B corresponds to voltage Eo2.

As a result, the voltage source at point A, switch S1, resistor R4,
A closed circuit is formed consisting of the resistor R5, the switch S2, and the voltage source at point B.

Now, if Eol and Eo2 are equal, the voltage VA at point A and the voltage VB at point B are equal (<<, these cancel each other out, no current flows through resistors R4 and R5, and output terminals 41 and 42
The voltages e1 and e2 are each zero volts.

This state is maintained when the load sharing is balanced.

From this state, if the load current of the inverter 1 increases and Eo1 becomes larger, the voltage vA at point A will be lower than the voltage VB at point B.

Therefore, current flows from point A in the direction of resistors R, , R5,
Point A has a higher potential than point C, and point B has a lower potential than point C.

When e and e2 are detected with the polarities shown in the figure, output terminal 4
1, a positive voltage e1 is generated at the output terminal 42, and a negative voltage e2 is generated at the output terminal 42.

When the positive voltage e1 is generated, it is compared and amplified with a reference level in the differential amplifier 11, and becomes an input to the input terminal b of the comparator circuit 12.

In FIG. 6A, Lb and Lb2 indicate the level of the input negative pressure at the input terminal b of the comparator circuit 12.

This level changes depending on load sharing, and since it is assumed that e1 has increased, it changes from Lb1 to Lb2.

A sawtooth wave voltage indicated by La in FIG. 6A is applied to the other input terminal a of the comparator circuit 12, and the output changes when this voltage crosses the level Lb1 or Lb2.

FIG. 6C shows the output of the comparator circuit 12, and FIG. 6B shows the output of fixed oscillation, that is, the fixed phase signal.

The sawtooth wave voltage is generated in synchronization with the Shingetsu in Figure 6B, and
The gate signal of the fixed phase of the thyristor of the inverter, that is, the third
The signals shown in Figures A and BK are also generated in synchronization with this.

At level Lb, the output is shown by the solid line in FIG. 6C, but at level Lb2, the output is shown by the dotted line.

Therefore, the differential pulse generated from the differential circuit 13 is also
The line changes from a solid line to a dotted line as shown in .

Then, due to this differential pulse, the phase of the pulse generated from the phase shifter 14 changes from a solid line to a dotted line as shown in FIG. 6E.

As a result, the waveform of the output voltage of inverter 1 also changes as shown in FIG.
Control of the pulse width in the thyristor inverter, which changes from a solid line to a dotted line as shown in FIG. 3, is achieved by changing from a solid line to a dotted line in FIG.

That is, by changing the phase of the gate signals of the thyristors 23c and 23d from the solid line to the dotted line, the output voltage is also changed from the solid line to the dotted line.

Now, if the load sharing of inverter 1 increases, e1 becomes thicker, and the output pulse width of inverter 1 becomes as shown by the dotted line as shown in Figure 6F, it means that the phase of the output voltage of inverter 1 is delayed. This reduces load sharing.

In this case, the output voltage becomes higher, but this has little effect on load sharing, and the phase of the output voltage affects load sharing.

Although the control of the inverter 1 has been described above, the operation of the inverter 2 is opposite to that of the inverter 1.

That is, since e2 of the output terminal 42 becomes negative, the phase of the output voltage of the inverter 2 is advanced, thereby increasing the load sharing, and finally the load sharing of the inverters 1 and 2 becomes equal.

During parallel operation of inverters 1 and 2, no problem occurs even with the conventional circuit shown in FIG.

However, a problem arose when parallel operation started.

This will be explained next.

Assume that inverter 1 is operated under load first, and then switch 5 and switch s2 are turned on to operate inverter 2 in parallel.

At the time of parallel input, a parallel input circuit (not shown) starts operation so that inverters 1 and 2 share the load in a balanced state.

Therefore, if the load sharing is set equally during parallel input, Eol and Eo2 are equal.

However, even if Eo2 occurs, a predetermined voltage is not immediately generated across the capacitor C2 due to a delay in response between the smoothing circuit resistor R6 and the capacitor c2.

Therefore, at the moment switch s2 closes in parallel, the voltage of capacitor C of inverter 1 causes 01-81-
A current flows through the closed circuit of R4-R5-82-02, and voltages e and e2 are generated across R4 and R5.

In this case, when point C is used as a reference, point A is higher than point C, so e1 becomes a positive voltage and e2 becomes a negative voltage.

Figure 5 A, B, C, and D show the voltage changes of VA, VB, e1, and e2. When the voltages are turned on in parallel at t1, VA decreases, VB gradually increases, and e1 increases instantaneously. , e
2 decreases instantaneously.

Although the load sharing between inverters 1 and 2 is equal, the load sharing momentarily becomes unbalanced due to fluctuations in e1 and e2.

That is, an increase in e1 causes the control to reduce the load sharing of the inverter 1, and a decrease in e2 causes the control to increase the load share of the inverter 2.

As a result, not only the load sharing becomes unbalanced, but one inverter may be overloaded or commutation may fail.

SUMMARY OF THE INVENTION The present invention has been made in order to correct the above-mentioned defects, and it is an object of the present invention to provide a load sharing control circuit that prevents variations in load sharing during parallel input.

A load sharing control circuit according to the present invention capable of achieving the above object includes a plurality of capacitors each connected to a voltage corresponding to a load amount of each of a plurality of power supplies; A plurality of signal detection resistors for load sharing control connected in series via at least one switch, which operate in conjunction with the parallel application of the power supply, are connected between one end of the capacitor, and the terminals of the plurality of capacitors are connected in common. a charging circuit having a common connection line to be connected, a control circuit connected in parallel to the capacitor corresponding to the power supply that is turned on in parallel, and the capacitor corresponding to the power supply in a no-load state among the plurality of power supplies. and a circuit for controlling the control circuit so that the charging circuit charges the capacitor up to a charging voltage of the capacitor corresponding to a power supply in a loaded state among the plurality of power supplies, and before parallel power supply, In this case, the plurality of capacitors are charged to the same voltage, and after parallel input, the plurality of capacitors are charged to a voltage corresponding to the load sharing of each of the plurality of power supplies, regardless of the charging circuit, and A load sharing control signal is detected from both ends of each of the plurality of load sharing control signal detection resistors.

If configured as described above, there will be no disturbance in load sharing during parallel input.

Next, one embodiment of the present invention will be described.

FIG. 7 shows an improved load sharing amount detection circuit, showing the same parts as the circuit of FIG.

Therefore, the same reference numerals are given to the parts common to those in FIG. 4, and the explanation thereof will be omitted.

The circuit in Figure T newly includes DC power supplies E1 and E2, switches S3 and S4A, field effect transistors FET1 and FET.
2, and resistances R,,R,.

has been added. Switch S3, S, is switch S1
1S2, and when switches S1 and S2 close, switches S3 and S4 open.

Next, the operation when the load sharing amount detection circuit of FIG. T is used in FIG. 1 will be described.

When power is being supplied to the load 3 only from the inverter 1, Eo2 is zero and only Eo1 is detected.

As a result, capacitor C1
is charged, and point D becomes VD.

If inverter 1 is connected to a load, switch S
1 and 84 are closed, while switches S2 and 83 are open.

Therefore, in this example, 8,-R4-R5-R
, o, a voltage is applied to the gate of FET2.

FET2 is a source follower circuit, and capacitor C2 is charged by power source E2 until the source potential becomes equal to the gate potential.

As a result, the charging voltage of the capacitor C2, ie, the voltage VE at point E, and the charging voltage of the capacitor C, ie, the voltage VD at point D, become equal.

In this state, no current flows through resistors R4 and R5, so voltages e1 and e2 at output terminals 41 and 42 are respectively zero volts.

The portions before 12 in FIG. 8 indicate the above-mentioned state.

Therefore, the inverter 1 is operated under load without being subjected to load sharing control.

In the load operating state of the inverter 1 as described above, if the switch 5 is turned on and the inverter 2 is turned on in parallel, the switches S2 and S3 are also closed.

Therefore, as in the case of Fig. 4, 01-8, -R4-
A closed circuit of F5-02 is formed.

However, in the case of the present invention, since capacitors C and 02 are charged to the same voltage, no current flows through this closed circuit.

Therefore, e1 and e2 are zero volts. Therefore, even if the input is made in parallel at t2, the state of equal load sharing will not be disturbed.
, maintained.

With equal load sharing, each inverter output voltage decreases and Eo11E02 decreases, resulting in C1, C
Although the voltage activation voltages of 2 are lowered, they are kept at the same voltage as shown in FIGS. 8A and 8H, and e1 and e2 are maintained at zero volts.

Therefore, the phases of the gate signals of inverters 1 and 2 are not changed, and both inverters maintain stable parallel operation with equal load sharing.

This state is shown after t2 in FIG.

If the load sharing becomes unbalanced for some reason after parallel input, for example, if the load sharing of inverter 1 increases,
Bo1>Eo2, and VD>VE.

Then, as explained in FIG. 4, e1 becomes a positive voltage, Ikegata and e2 become a negative voltage, and control is performed so that the load sharing of inverter 1 decreases and the load sharing of inverter 2 increases. .

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment and can be modified.

For example, it is also applicable when three or more units are operated in parallel.

Further, although the embodiment has described a case where the load is shared equally, it is also applicable to a case where the load is shared at a predetermined ratio.

Further, although the charging voltage of the capacitors C1 and C2 is controlled by the FET and FET2, it may be controlled by a vacuum tube, a bipolar transistor, or the like.

Also, in FIG. 7, the gate electrode of FET 2 may be directly connected to point D, and the gate electrode of FET 2 may be directly connected to point E.

In addition, in the embodiment, the voltages e1 and e2 of the output terminals 41 and 42
is used for inverter load sharing control, but this e
11e2 can also be applied to parallel operation of rectifiers, DC stabilized power supplies, etc.

Further, the inverter may have a configuration other than that shown in FIG. 2.

For example, in the circuit shown in Fig. 1, if it is designed so that inverter 1 is always operated first and inverter 2 is turned on in parallel, a control circuit including switches S and FETs is provided. Na《Tomoyoshi.

That is, it is sufficient to provide a control circuit only in the circuit for parallel input.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the inverter parallel operation system, Figure 2 is a specific circuit diagram of the inverter in Figure 1, and Figure 3 is a block diagram showing the inverter parallel operation system.
The figure is a waveform diagram showing the gate signal and output voltage for the thyristor of the inverter in Figure 2, Figure 4 is a circuit diagram showing a conventional load sharing amount detection circuit, and Figure 5 is a waveform diagram showing the conventional circuit of Figure 4. A diagram showing the voltage change of VA, VB2e1)e2,
6 is a waveform diagram of each part for explaining the load sharing change state in the circuit of FIG. 1, FIG. 7 is a circuit diagram showing a load sharing amount detection circuit according to an embodiment of the present invention, and FIG. The figure is a diagram showing voltage changes of VD, VE, e1, and e2 in the circuit of Figure T. Also, in the symbols used in the drawings, 1 and 2 are inverters, 3 is a load, 4 and 5 are switches, 6 and 7 are current transformers, 8 is a load sharing detection circuit, 14 is a phase shifter, 4L, 42 is an output terminal, C1, C2 are capacitors, R4JR5 is a resistor, 81, 82, 83, 84 are switches, FET1, FE
T2 is a field effect transistor, and El and E2 are DC power supplies.

Claims (1)

[Scope of Claims] 1. A plurality of capacitors connected to each other so as to be charged to a voltage corresponding to the load amount of each of the plurality of power supplies, and a capacitor connected to one end of the plurality of capacitors in conjunction with the parallel application of the power supplies. a plurality of signal detection resistors for load sharing control connected in series via at least one switch, which are closed by a switch, and a common connection line that commonly connects the terminals of the plurality of capacitors; a control circuit having a control circuit connected in parallel to the capacitor corresponding to the power supply; and a control circuit having a control circuit connected in parallel to the capacitor corresponding to the power supply, and the capacitor corresponding to the power supply in the no-load state among the plurality of power supplies being in the load state among the plurality of power supplies. and a circuit for controlling the control circuit so that the charging circuit charges the capacitors to a charging voltage corresponding to a power source located at After being charged in parallel, the plurality of capacitors are charged to a voltage corresponding to the load sharing of each of the plurality of power supplies, regardless of the charging circuit, and each of the plurality of load sharing control signal detection resistors is charged. A load sharing control circuit in a parallel operation system for a power supply device, characterized in that a load sharing control signal is detected from both ends.