JPS585394B2 - densid cay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and in particular to a time adjustment circuit.

Conventionally, time adjustment for electronic watches has been achieved by using standard signal generators and conventional means.

That is, in a tuning fork watch, this is done by changing the tip mass of the tuning fork, or in a crystal watch, by inserting a trimmer capacitor into the oscillator and changing the value of this trimmer capacitor.

However, with such a configuration, it is necessary to add some extra means to the standard oscillator part, which reduces stability, and also makes it difficult to adjust the resonant frequency of the resonator itself. It had the disadvantage that it had to be built into a narrow space and could not be manufactured at a low cost.

These drawbacks become more noticeable as the frequency becomes higher.

The present invention provides a standard time signal f.

The purpose of the present invention is to provide an electronic timepiece which eliminates the above-mentioned drawbacks by performing time adjustment with equal constraints during frequency division when descending to a more determined signal f.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows a specific example of the present invention.

A is a standard signal generator made of a crystal oscillator or the like, which sends out a standard signal fo.

Both B-1 and B-4 are frequency dividers having addition/subtraction functions, and when a certain reference state is reached, a pulse f is generated.

1. I'll take fo2 to each winter mountain.

N is an OR circuit which obtains a signal f from the outputs fol and f02 from the frequency divider B-1°B-n.

Here, to simplify the explanation, fl is assumed to be a 1 second signal.

C is a decoder for controlling the time display section consisting of a mechanical display or an electrical display device such as a liquid crystal or a light emitting diode, and a decoder for displaying minutes, hours, days, days, etc. as necessary. Includes a frequency divider circuit that divides the frequency.

However, C includes a converter such as a motor when the display section is of a mechanical display type.

F receives the 1-second signal f, and sends the signal ab from addition or subtraction to the frequency dividers of B-1 and B-■,
Frequency dividers B-1 and B-■ each have an addition effect, or
This is a control signal generator for performing subtraction operations.

However, the addition and subtraction signals are output alternately.

The addition signal a1 and the subtraction signal b1 to the frequency divider B-I are alternate, and the addition signal a2 and the subtraction signal b to the frequency divider B-■
2 is alternating.

Furthermore, when al comes out, b2 comes out, and when bl comes out, a
It is controlled so that 2 is output, and its period is determined by a 1 second signal f1.

Now, by some means, a standard signal f corresponding to exactly 1 second is now applied to the frequency divider B-I.

A state that is subtracted from the reference state, for example, the O state, by that amount is written.

At that time, the frequency divider B-1 becomes capable of adding function,
Frequency divider B-■ is designed to perform subtraction.

Therefore, the control signals include the addition control signal a1 in the frequency divider B-I and the subtraction signal b2 in the division frequency B-■.

Standard signal f.

enters frequency dividers B-1 and B-n. Just one second later,
Frequency divider B-I returns to the reference state (0 state) and outputs a pulse f.

Roll 1. At this time, frequency divider B-n is in the initial state of frequency divider B-I.

Output signal f from frequency divider B-1. 1 passes through the OR circuit N and emits a 1-second signal f1. The 1-second signal f1 enters the control circuit F, and the control pulses a, b2 are reversed, and the frequency divider B-1
The subtraction control pulse b1 is input to the frequency divider B-■, and the addition control pulse a2 is input to the frequency divider B-■, so that the frequency divider B-I has a subtraction function and B-n has an addition function. .

This time, exactly one second later, the frequency divider B-n goes into the O state and outputs a pulse f.

2 is sent out. At this time, frequency divider B-I has recorded the earliest contents of frequency divider B-n, ie, is in its initial state.

Output pulse f from frequency divider B-■. 2 is an OR circuit, which passes through N and outputs a 1-second signal f1.

The one second signal f1 causes the control circuit F to reverse the control signal.

That is, the addition signal a1 is sent to the frequency divider B-1, and the frequency divider B-■
Then, the subtraction signal b2 is sent out, and the above operation is repeated thereafter.

Output from the frequency divider, fol. So, the standard signal f.

However, it is possible to obtain a signal for exactly 1 second.

Further, contrary to the above embodiment, a standard signal f corresponding to one second is applied to the frequency divider B-I.

Write the state of addition by the frequency divider B-I.
Even if the frequency divider B-I is made to be able to perform subtraction and the frequency divider B-I is made to be capable of addition, exactly one second later, the frequency divider B-I becomes 0 and the output pulse f.

issue. In this way, the frequency dividers B-■ and B-■ are configured to generate an output pulse when they reach a certain predetermined reference state, and one of the frequency dividers is set in advance to the desired output f1.
By subtracting or adding from state M the number of standard pulses corresponding to the period of , an output f1 of an arbitrary period can be obtained.

Let us explain how to give the initial state to the frequency divider B-I with reference to FIG.

Various means can be considered, and this is one specific example.

Standard signal f. The gate G is opened for exactly 1 second by a pulse S lasting exactly 1 second, and the standard signal f
1 goes into divider B, divider B is in subtraction state, and 0
Subtracted from the state.

That is, the above-mentioned initial state is obtained.

Of course, the present invention is not limited to what has been described above, and various modifications can be made.

Further, the circuit used is a C-MOS IC.

When the frequency is high, a C-MOS IC using Si-gate technology or even SO8 technology is advantageous.

For example, when SO8 technology is used in Si-gate, each element can be separated and made thinner, so the capacitance and stray capacitance at the gate and drain parts are reduced. This is advantageous in terms of power consumption because power consumption is extremely small.

Further, the present invention is more advantageous as the frequency is higher.

For example, the standard signal f.

When is IMHz, the minimum time delay accuracy can be obtained as 10-6.

As explained above, in the electronic timepiece according to the present invention, high stability can be obtained because no extra components are added to the standard signal oscillation section from the outside.

Furthermore, the frequency of the standard oscillator is relatively free and has a wide tolerance range.

For example, it has the advantage that it only needs to be 1 to 2 MHz, and therefore inexpensive standard oscillators can be mass-produced.

[Brief explanation of the drawing]

FIG. 1 shows a specific example of the present invention. FIG. 2 shows a specific example of means for providing an initial state in the specific example of FIG.

Claims (1)

[Claims] 1. In an electronic timepiece having a standard signal generator, a frequency divider, and a display section, the frequency divider is composed of two series of frequency dividers each connected to the standard signal generator, and the two series The frequency dividers each have an addition function, a subtraction function, and a function of generating an output pulse when a predetermined reference state is reached, and for controlling the addition function or subtraction function of the two series frequency dividers. and a logic circuit that forms an output signal from the output pulses of the two series of frequency dividers, and the control signal generator adds or subtracts the two series of frequency dividers, respectively. The addition or subtraction functional state of the frequency divider is reversed by the output signal while maintaining the functional state opposite to that of the frequency divider, and the initial state of one of the two series of frequency dividers is An electronic timepiece characterized in that the frequency divider is set to a reference state, and the initial state of the other frequency divider is set to a value separated by a certain value from the reference state.