JPS585394B2 - densid cay - Google Patents
densid cayInfo
- Publication number
- JPS585394B2 JPS585394B2 JP48047039A JP4703973A JPS585394B2 JP S585394 B2 JPS585394 B2 JP S585394B2 JP 48047039 A JP48047039 A JP 48047039A JP 4703973 A JP4703973 A JP 4703973A JP S585394 B2 JPS585394 B2 JP S585394B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency divider
- frequency
- signal
- series
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
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- Electric Clocks (AREA)
Description
【発明の詳細な説明】
本発明は、電子時計、特に、時間緩急回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and in particular to a time adjustment circuit.
従来、電子時計に関する時間緩急は、標準信号発生器に
、伺らかの手段を用いることによってなされて来た。Conventionally, time adjustment for electronic watches has been achieved by using standard signal generators and conventional means.
即ち、音叉時計では、音叉の先端質量を変化させるとか
、水晶時計に於ては、トリマコンデンサを発振器中に挿
入し、このトリマコンデンサの値を変えて行う等である
。That is, in a tuning fork watch, this is done by changing the tip mass of the tuning fork, or in a crystal watch, by inserting a trimmer capacitor into the oscillator and changing the value of this trimmer capacitor.
しかし、このような構成を取る限りに於ては、標準発振
器部分に、何らかの余分な手段を附加しなければならな
い為に、安定性が低下し、又、共振子そのものの共振周
波数を、緩急出来る狭い中白に作り込まねばならず、安
価に製作出来ない等の欠点があった。However, with such a configuration, it is necessary to add some extra means to the standard oscillator part, which reduces stability, and also makes it difficult to adjust the resonant frequency of the resonator itself. It had the disadvantage that it had to be built into a narrow space and could not be manufactured at a low cost.
これらの欠点は、周波数が高くなる程、目立って来る欠
点である。These drawbacks become more noticeable as the frequency becomes higher.
本発明は、標準時間信号f。The present invention provides a standard time signal f.
より定められた信号f、迄逓降していく際の周波数分周
中に、時間緩急を等制約に行うようにして上記欠点を取
り除いた電子時計を提供するものである。The purpose of the present invention is to provide an electronic timepiece which eliminates the above-mentioned drawbacks by performing time adjustment with equal constraints during frequency division when descending to a more determined signal f.
以下、本発明を図面をもってさらに詳しく説明しよう。Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第1図は、本発明の一具体例を示す。FIG. 1 shows a specific example of the present invention.
Aは、水晶振動子等よりなる標準信号発生器で、標準信
号foを送り出す。A is a standard signal generator made of a crystal oscillator or the like, which sends out a standard signal fo.
B−1,B−4は、共に、加・減算機能を有する、周波
数分周器で、ある定められた基準状態になった時に、パ
ルスf。Both B-1 and B-4 are frequency dividers having addition/subtraction functions, and when a certain reference state is reached, a pulse f is generated.
1.fo2を各冬山す。1. I'll take fo2 to each winter mountain.
NはOR回路で、周波数分周器B−1゜B−nからの出
力、fol、f02より、信号f、を得る。N is an OR circuit which obtains a signal f from the outputs fol and f02 from the frequency divider B-1°B-n.
ここで説明を簡単にする為に、flは1秒信号とする。Here, to simplify the explanation, fl is assumed to be a 1 second signal.
Cは、機械的表示、又は液晶、発光ダイオード等の電気
的表示装置よりなる時間表示部りを制御する為のデコー
ダ、及び、表示する、分、時、日、曜等、必要とすると
ころ迄分周する分周回路を含む。C is a decoder for controlling the time display section consisting of a mechanical display or an electrical display device such as a liquid crystal or a light emitting diode, and a decoder for displaying minutes, hours, days, days, etc. as necessary. Includes a frequency divider circuit that divides the frequency.
但し、Cは表示部りが機械的表示方式の場合は、モータ
等の変換器を含む。However, C includes a converter such as a motor when the display section is of a mechanical display type.
Fは、1秒信号f、を受けて、B−1、及び、B−■の
周波数分周器に加算か減算からの信号abを送り出し、
周波数分周器B−1,B−■、各々が加算作用、又は、
減算作用を行える様にする為の制御信号発生器である。F receives the 1-second signal f, and sends the signal ab from addition or subtraction to the frequency dividers of B-1 and B-■,
Frequency dividers B-1 and B-■ each have an addition effect, or
This is a control signal generator for performing subtraction operations.
但し、加算、及び、減算信号は、交互に出される。However, the addition and subtraction signals are output alternately.
分周器B−Iへの加算信号a1、減算信号b1は交互で
あり、又、分周器B−■への加算信号a2、減算信号b
2は交互である。The addition signal a1 and the subtraction signal b1 to the frequency divider B-I are alternate, and the addition signal a2 and the subtraction signal b to the frequency divider B-■
2 is alternating.
さらに、alが出る時はb2が出、blが出る時は、a
2が出る様に制御され、又その周期は1秒信号f1によ
ってなされる。Furthermore, when al comes out, b2 comes out, and when bl comes out, a
It is controlled so that 2 is output, and its period is determined by a 1 second signal f1.
さて、何らかの手段により、今、分周器B−Iに、ちょ
うど、1秒間に相当する標準信号f。Now, by some means, a standard signal f corresponding to exactly 1 second is now applied to the frequency divider B-I.
の分だけ、基準状態たとえばO状態より減じられた状態
を書き込んでおく。A state that is subtracted from the reference state, for example, the O state, by that amount is written.
しかる時、分周器B−1は加算作用が出来る様になり、
分周器B−■は、減算作用が出来る様にされている。At that time, the frequency divider B-1 becomes capable of adding function,
Frequency divider B-■ is designed to perform subtraction.
従って、制御信号は、分周器B−Iには、加算制御信号
a1が、分周期B−■には減算信号b2が入っている。Therefore, the control signals include the addition control signal a1 in the frequency divider B-I and the subtraction signal b2 in the division frequency B-■.
標準信号f。Standard signal f.
は、分周器B−1,B−nに入る。ちょうと1秒後に、
分周器B−Iは基準状態(0状態)にもどり、出力パル
スf。enters frequency dividers B-1 and B-n. Just one second later,
Frequency divider B-I returns to the reference state (0 state) and outputs a pulse f.
1を出す。この時、分周器B−nは、分周器B−Iの最
初の状態になっている。Roll 1. At this time, frequency divider B-n is in the initial state of frequency divider B-I.
分周器B−1からの出力信号f。1はOR回路Nを通り
、1秒信号f1を発し1秒信号f1は、制御回路Fに入
り、制御パルス、a、、b2は逆となり、分周器B−1
には減算制御パルスb1が、分周器B−■には加算制御
パルスa2が入って分周器B−Iは減算機能、B−nは
加算機能を有することになり、又、標準信号f。Output signal f from frequency divider B-1. 1 passes through the OR circuit N and emits a 1-second signal f1. The 1-second signal f1 enters the control circuit F, and the control pulses a, b2 are reversed, and the frequency divider B-1
The subtraction control pulse b1 is input to the frequency divider B-■, and the addition control pulse a2 is input to the frequency divider B-■, so that the frequency divider B-I has a subtraction function and B-n has an addition function. .
によって演算が行なわれ、今度はちょうど1秒後に分周
器B−nがO状態となり出力パルスf。This time, exactly one second later, the frequency divider B-n goes into the O state and outputs a pulse f.
2が送り出される。この時には分周器B−Iは、分周器
B−nの最初期の内容を記録していることになり、即ち
最初の状態になる。2 is sent out. At this time, frequency divider B-I has recorded the earliest contents of frequency divider B-n, ie, is in its initial state.
分周器B−■からの出力パルスf。2はOR回路、Nを
通って1秒信号f1を出す。Output pulse f from frequency divider B-■. 2 is an OR circuit, which passes through N and outputs a 1-second signal f1.
1秒信号f1により、制御回路Fは制御信号を逆にする
。The one second signal f1 causes the control circuit F to reverse the control signal.
即ち分周器B−1へは、加算信号a1に、分周器B−■
には、減算信号b2を送り出し、以後以上の動作がくり
返される。That is, the addition signal a1 is sent to the frequency divider B-1, and the frequency divider B-■
Then, the subtraction signal b2 is sent out, and the above operation is repeated thereafter.
分周器からの出力、fol。で、標準信号f。Output from the frequency divider, fol. So, the standard signal f.
が何であわ、正確に1秒信号を得ることかできる。However, it is possible to obtain a signal for exactly 1 second.
また、上記実施例とは逆に分周器B−Iに1秒間に相当
する標準信号f。Further, contrary to the above embodiment, a standard signal f corresponding to one second is applied to the frequency divider B-I.
の分だけ加算した状態を書き込んでおき、分周器B−I
は減算作用が出来る様にし、分周器B−■は加算作用が
出来るようにしても、ちょうど1秒後に分周器B−Iが
0となり、出力パルスf。Write the state of addition by the frequency divider B-I.
Even if the frequency divider B-I is made to be able to perform subtraction and the frequency divider B-I is made to be capable of addition, exactly one second later, the frequency divider B-I becomes 0 and the output pulse f.
を出す。このように、分周器B−■、B−■がある定め
られた基準状態になった時に出力パルスを生ずるように
構成し、一方の分周器にあらかじめ目的とする出力f1
の周期に相当する標準パルスの数を状態Mから減じ又は
加算しておくことにより任意の周期の出力f1を得るこ
とができる。issue. In this way, the frequency dividers B-■ and B-■ are configured to generate an output pulse when they reach a certain predetermined reference state, and one of the frequency dividers is set in advance to the desired output f1.
By subtracting or adding from state M the number of standard pulses corresponding to the period of , an output f1 of an arbitrary period can be obtained.
分周器B−Iへの初期状態の与え方を第2図で説明しよ
う。Let us explain how to give the initial state to the frequency divider B-I with reference to FIG.
色々な手段が考えられるが、これはその1つの具体例で
ある。Various means can be considered, and this is one specific example.
標準信号f。は、ちょうど1秒間に当るパルスSによっ
てゲートGは、ちょうど1秒間だけ開かれ、標準信号f
1は、分周器Bに入り、分周器Bは減算状態であり、0
状態より減算される。Standard signal f. The gate G is opened for exactly 1 second by a pulse S lasting exactly 1 second, and the standard signal f
1 goes into divider B, divider B is in subtraction state, and 0
Subtracted from the state.
即ち上述した初期状態が得られる。That is, the above-mentioned initial state is obtained.
勿論、以上説明して来たところのみに、本発明は限定さ
れず、種々なる変形が考えられる。Of course, the present invention is not limited to what has been described above, and various modifications can be made.
又、使用される回路は、C−MOS・ICが使用される
。Further, the circuit used is a C-MOS IC.
周波数が高い場合には、Si−gate技術、さらには
SO8技術を使ったC−MOS・ICが有利となる。When the frequency is high, a C-MOS IC using Si-gate technology or even SO8 technology is advantageous.
これは、例えば、Si−gateでSO8技術を使った
場合、各素子が各々分離独立させることが出来、又、薄
く作り込めるので、ゲート、及びドレイン部での容量及
び浮遊容量が小さくなり容量による電力消費がきわめて
小さくなる為に消費電力の上から有利である。For example, when SO8 technology is used in Si-gate, each element can be separated and made thinner, so the capacitance and stray capacitance at the gate and drain parts are reduced. This is advantageous in terms of power consumption because power consumption is extremely small.
又、本発明は、周波数が高い程有利となる。Further, the present invention is more advantageous as the frequency is higher.
例えば、標準信号f。For example, the standard signal f.
がIMHzの場合、最小時間緩急精度は、10−6を得
ることができる。When is IMHz, the minimum time delay accuracy can be obtained as 10-6.
以上説明して来た如く、本発明による電子時計では、標
準信号発振部に何ら外部より、余分なものを附加するこ
とがない為に高い安定度が得られる。As explained above, in the electronic timepiece according to the present invention, high stability can be obtained because no extra components are added to the standard signal oscillation section from the outside.
又標準発振子の周波数は、比較的自由で、その許容範囲
が広い。Furthermore, the frequency of the standard oscillator is relatively free and has a wide tolerance range.
例えば1〜2MHzであればよいとか、従って安価な標
準発振子を多量生産できる等の利点を有するものである
。For example, it has the advantage that it only needs to be 1 to 2 MHz, and therefore inexpensive standard oscillators can be mass-produced.
第1図は、本発明の一具体例。
第2図は、第1図の具体例中に於て、初期状態を与える
手段の一具体例を示す。FIG. 1 shows a specific example of the present invention. FIG. 2 shows a specific example of means for providing an initial state in the specific example of FIG.
Claims (1)
電子時計に於いて、前記周波数分周器はそれぞれ前記標
準信号発生器に接続された二系列の周波数分周器よりな
り、前記二系列の周波数分周器はそれぞれ加算機能及び
減算機能とあらかじめ定められた基準状態になった時に
出力パルスを生じる機能を有し、前記二系列の周波数分
周器の加算機能又は減算機能を制御するための制御信号
発生器と、前記二系列の周波数分周器の出力パルスより
出力信号を形成する論理回路を具備し、前記制御信号発
生器は、前記二系列の周波数分周器をそれぞれ加算又は
減算の逆の機能状態に保ちながら、前記出力信号により
前記画周波数分周器の加算又は減算機能状態を逆転させ
、前記二系列の周波数分周器のうち一方の周波数分周器
の初期状態は前記基準状態に設定され、他方の周波数分
周器の初期状態は前記基準状態から一定値隔った値に設
定されたことを特徴とする電子時計。1. In an electronic timepiece having a standard signal generator, a frequency divider, and a display section, the frequency divider is composed of two series of frequency dividers each connected to the standard signal generator, and the two series The frequency dividers each have an addition function, a subtraction function, and a function of generating an output pulse when a predetermined reference state is reached, and for controlling the addition function or subtraction function of the two series frequency dividers. and a logic circuit that forms an output signal from the output pulses of the two series of frequency dividers, and the control signal generator adds or subtracts the two series of frequency dividers, respectively. The addition or subtraction functional state of the frequency divider is reversed by the output signal while maintaining the functional state opposite to that of the frequency divider, and the initial state of one of the two series of frequency dividers is An electronic timepiece characterized in that the frequency divider is set to a reference state, and the initial state of the other frequency divider is set to a value separated by a certain value from the reference state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP48047039A JPS585394B2 (en) | 1973-04-25 | 1973-04-25 | densid cay |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP48047039A JPS585394B2 (en) | 1973-04-25 | 1973-04-25 | densid cay |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS49134369A JPS49134369A (en) | 1974-12-24 |
JPS585394B2 true JPS585394B2 (en) | 1983-01-31 |
Family
ID=12764008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP48047039A Expired JPS585394B2 (en) | 1973-04-25 | 1973-04-25 | densid cay |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS585394B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH501959A (en) * | 1968-12-20 | 1970-08-31 | Ebauches Sa | Electronic frequency converter |
-
1973
- 1973-04-25 JP JP48047039A patent/JPS585394B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH501959A (en) * | 1968-12-20 | 1970-08-31 | Ebauches Sa | Electronic frequency converter |
Also Published As
Publication number | Publication date |
---|---|
JPS49134369A (en) | 1974-12-24 |
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