JPS5853859B2 - Pinhole measurement method for thin films - Google Patents

Pinhole measurement method for thin films

Info

Publication number
JPS5853859B2
JPS5853859B2 JP2584078A JP2584078A JPS5853859B2 JP S5853859 B2 JPS5853859 B2 JP S5853859B2 JP 2584078 A JP2584078 A JP 2584078A JP 2584078 A JP2584078 A JP 2584078A JP S5853859 B2 JPS5853859 B2 JP S5853859B2
Authority
JP
Japan
Prior art keywords
thin film
pinholes
measured
film
pinhole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2584078A
Other languages
Japanese (ja)
Other versions
JPS54118890A (en
Inventor
操 佐賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2584078A priority Critical patent/JPS5853859B2/en
Publication of JPS54118890A publication Critical patent/JPS54118890A/en
Publication of JPS5853859B2 publication Critical patent/JPS5853859B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/91Investigating the presence of flaws or contamination using penetration of dyes, e.g. fluorescent ink

Description

【発明の詳細な説明】 本発明は薄膜のピンホール測定方法に係り、特に気相成
長法、スパッタリング法、蒸着法などによって基板上に
堆積させた金属あるいは絶縁物の薄膜のピンホールを検
出し、測定する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring pinholes in thin films, and in particular to detecting pinholes in thin films of metal or insulators deposited on a substrate by vapor growth, sputtering, vapor deposition, etc. , regarding how to measure.

例えば、半導体素子の製造工程において、半導体基板上
に堆積された絶縁薄膜にピンホールが存在すると具合が
悪いので、絶縁薄膜に生じたピンホールの有無を検査し
なげればならない。
For example, in the manufacturing process of semiconductor devices, the presence of pinholes in an insulating thin film deposited on a semiconductor substrate causes problems, so it is necessary to inspect the insulating thin film for the presence of pinholes.

ところがピンホールは肉眼では検出が困難であるので、
従来は、試験用の半導体基板の表面に絶縁薄膜を堆積さ
せた後、これを水中において通電し、水の電気分解現象
を利用してピンホールから水素の気泡が発生するかどう
かを観察したり、あるいは、半導体基板の表面に薄膜を
形成したものをメッキ液中に浸漬しピンホールを通して
金属が析出するか否かを観察することにより、ピンホー
ルの有無を検査していた。
However, pinholes are difficult to detect with the naked eye, so
Conventionally, an insulating thin film was deposited on the surface of a semiconductor substrate for testing, and then electricity was applied to the film in water to observe whether hydrogen bubbles were generated from pinholes using water electrolysis. Alternatively, the presence or absence of pinholes has been inspected by immersing a semiconductor substrate with a thin film formed on the surface in a plating solution and observing whether metal is deposited through the pinholes.

しかしながら、上述した従来の方法のうち、前者におい
ては微小なピンホール部から水素ガスの発生が起こりに
くいため正確な検査を期待することができず、また、後
者にあっては検査設備が大損りなものとなって検査の簡
易さに欠けるという欠点を有していた。
However, among the conventional methods mentioned above, accurate inspection cannot be expected with the former because it is difficult for hydrogen gas to be generated from minute pinholes, and with the latter, inspection equipment may be seriously damaged. However, it has the disadvantage that it lacks the simplicity of inspection.

そこで本発明の目的&L基板の表面に被着された金属あ
るいは絶縁物の薄膜に発生したピンホールの有無を簡易
かつ正確に測定することができる薄膜のピンホール測定
方法を提供することにある。
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for measuring pinholes in a thin film that can easily and accurately measure the presence or absence of pinholes generated in a thin film of metal or insulator deposited on the surface of a &L substrate.

しかして、上記目的を達成する本発明による薄膜のピン
ホール測定方法は、特定のエツチング液に対するエツチ
ング速度が測定対象となる薄膜に対してよりも早い下地
薄膜を基板上に形成し、その上にピンホールを測定すべ
き測定対象となる薄膜を重ねて形成し、次いでエツチン
グ処理を施すことにより測定対象となる薄膜中のピンホ
ールを下地薄膜上に拡大転写し、ピンホールの数や位置
を測定するようにしたことを特徴としている。
Therefore, in the thin film pinhole measuring method according to the present invention which achieves the above object, a base thin film is formed on a substrate, and the etching rate with respect to a specific etching solution is faster than that of the thin film to be measured. Thin films to be measured with pinholes are layered and then etched to enlarge and transfer the pinholes in the thin film to be measured onto the underlying thin film to measure the number and position of the pinholes. It is characterized by the fact that it is made to do so.

以下本発明による薄膜のピンホール測定方法を半導体素
子の製造を例にとって図面を参照して説明する。
The method for measuring pinholes in thin films according to the present invention will be described below with reference to the drawings, taking the manufacture of semiconductor devices as an example.

先ず測定対象となる薄膜がシリコン窒化膜である場合を
例にとって説明する。
First, a case where the thin film to be measured is a silicon nitride film will be described as an example.

a)シリコンウェハ1の表面に下地薄膜としての酸化膜
2を被着する。
a) An oxide film 2 is deposited on the surface of a silicon wafer 1 as a base thin film.

この酸化膜2を形成するにはシリコンウェハ1を酸化雰
囲気中で加熱してその表面を熱酸化すれば良い。
This oxide film 2 can be formed by heating the silicon wafer 1 in an oxidizing atmosphere to thermally oxidize its surface.

b)上記酸化膜2の上に測定対象となる薄膜としてのシ
リコン窒化膜3を被着する。
b) A silicon nitride film 3 as a thin film to be measured is deposited on the oxide film 2.

このシリコン窒化膜3にはピンホールがあるものと仮定
し、このピンホールを図中符号4で示すことにする。
It is assumed that this silicon nitride film 3 has a pinhole, and this pinhole is indicated by reference numeral 4 in the figure.

C) シリコンウェー・1をフッ化水素酸バッファ液
中に浸してエツチング処理を行う。
C) Perform etching treatment by immersing silicon wafer 1 in a hydrofluoric acid buffer solution.

この時、シリコン窒化膜3にピンホール4が生じている
ために、ピンホール4を通してフッ化水素酸バッファ液
が下地薄膜2の表面に入り込む。
At this time, since pinholes 4 are formed in the silicon nitride film 3, the hydrofluoric acid buffer solution enters the surface of the underlying thin film 2 through the pinholes 4.

すると、下地薄膜に対するフッ化水素酸バッファ液のエ
ツチング速度は非常に大きいので、図Cに示すようにピ
ンホール4の直下の部分が図示のように浸食されること
になる。
Then, since the etching rate of the hydrofluoric acid buffer solution on the underlying thin film is very high, the portion immediately below the pinhole 4 is eroded as shown in Figure C.

d)次いで測定対象となった薄膜をリン酸を使って除去
し、酸化膜2上転写されたピンホールの数や位置を測定
する。
d) Next, the thin film to be measured is removed using phosphoric acid, and the number and position of pinholes transferred onto the oxide film 2 are measured.

次に測定対象となる薄膜が金の薄膜である場合を例にと
って説明すると、こ1合にはエツチング液として塩酸水
溶液が使用される。
Next, an example will be explained in which the thin film to be measured is a gold thin film.In this case, an aqueous hydrochloric acid solution is used as the etching liquid.

この塩酸水溶液に対するエツチング速度が金の薄膜に対
してよりも早くなるような下地薄膜としてはクロム膜が
考えられる。
A chromium film can be considered as a base thin film whose etching rate for this hydrochloric acid aqueous solution is faster than that for a gold thin film.

そこで、この実施例においては、シリコンウェハの上に
下地薄膜としてのクロム膜を被着し、その上に測定対象
となる金の薄膜を重ねて被着する。
Therefore, in this embodiment, a chromium film is deposited as a base thin film on a silicon wafer, and a gold thin film to be measured is superimposed thereon.

そして、上記C)と同様、シリコンウェハを塩酸水溶液
中に浸してエツチング処理を行えば良い。
Then, as in C) above, the silicon wafer may be immersed in an aqueous hydrochloric acid solution to perform the etching process.

この場合にも金の薄膜中にピンホールが存在した場合、
塩酸水溶液はピンホールを通してクロム膜に対しピンホ
ールの直下部分を浸食させる。
In this case too, if a pinhole exists in the gold thin film,
The hydrochloric acid aqueous solution passes through the pinhole and erodes the chromium film directly below the pinhole.

そこで、ヨウ化カリウムとヨウ素の混合液を使って測定
対象となった金の薄膜を除去し、クロム膜上に転写され
たピンホールの数ヤ寸法ヲ測定すれば良い。
Therefore, the thin gold film to be measured is removed using a mixture of potassium iodide and iodine, and the dimensions of the pinholes transferred onto the chromium film are measured.

このように本発明によれば、特定のエツチング液に対す
るエツチング速度が測定対象となる薄膜に対してよりも
早いような下地薄膜を基板上に形成し、その上に測定対
象となる薄膜を被着し、所定のエツチング液を使ってエ
ツチング処理を行なうと、測定対象となる薄膜のピンホ
ールよりエツチング液が下地薄膜上に達し、エツチング
液は下地薄膜上に大きなどンホールを転写形成すること
になる。
As described above, according to the present invention, a base thin film is formed on a substrate such that the etching speed of a specific etching solution is faster than that of the thin film to be measured, and the thin film to be measured is deposited on top of the base thin film. However, when etching is performed using a specified etching solution, the etching solution reaches the base thin film through pinholes in the thin film to be measured, and the etching solution transfers and forms large holes on the base thin film. .

その結果、測定対象となる薄膜中のピンホールは下地薄
膜の上に拡大転写することができ、測定対象となる膜の
ピンホールの検出がきわめて容易となり、ピンホールの
数、発生位置を正確につかむことができる。
As a result, pinholes in the thin film to be measured can be enlarged and transferred onto the underlying thin film, making it extremely easy to detect pinholes in the film to be measured, and accurately determining the number and location of pinholes. You can grab it.

したがって、この測定結果に基いて、ピンホールのない
金属または絶縁物の薄膜を形成する技術を確立すること
が可能となる。
Therefore, based on this measurement result, it becomes possible to establish a technique for forming a pinhole-free metal or insulator thin film.

【図面の簡単な説明】[Brief explanation of drawings]

図中a乃至dは本発明による測定対象となる薄膜のピン
ホールの測定方法を示す工程図である。 1・・・シリコンウェハ、2・・・酸化膜、3・・・測
定対象となる薄膜、4・・・ピンホール。
In the figure, a to d are process diagrams showing a method for measuring pinholes in a thin film to be measured according to the present invention. 1... Silicon wafer, 2... Oxide film, 3... Thin film to be measured, 4... Pinhole.

Claims (1)

【特許請求の範囲】[Claims] 1 %定のエツチング液に対するエツチング速度が測定
対象となる薄膜に対してよりも早い下地薄膜を基板上に
形成し、その上にピンホールを測定すべき測定対象とな
る金属あるいは絶縁物の薄膜を重ねて形成し、次いでエ
ツチング処理を施すことにより測定対象となる薄膜中の
ピンホールを下地薄膜上に拡大転写し、ピンホールを測
定するようにしたことを特徴とする薄膜のピンホール測
定方法。
Form a base thin film on the substrate whose etching rate with a constant 1% etching solution is faster than that of the thin film to be measured, and then place a thin film of the metal or insulator to be measured for pinholes on top of it. 1. A method for measuring pinholes in a thin film, characterized in that the pinholes in the thin film to be measured are enlarged and transferred onto a base thin film by forming overlapping layers and then performing an etching process to measure the pinholes.
JP2584078A 1978-03-07 1978-03-07 Pinhole measurement method for thin films Expired JPS5853859B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2584078A JPS5853859B2 (en) 1978-03-07 1978-03-07 Pinhole measurement method for thin films

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2584078A JPS5853859B2 (en) 1978-03-07 1978-03-07 Pinhole measurement method for thin films

Publications (2)

Publication Number Publication Date
JPS54118890A JPS54118890A (en) 1979-09-14
JPS5853859B2 true JPS5853859B2 (en) 1983-12-01

Family

ID=12177040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2584078A Expired JPS5853859B2 (en) 1978-03-07 1978-03-07 Pinhole measurement method for thin films

Country Status (1)

Country Link
JP (1) JPS5853859B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810195B2 (en) * 1986-11-04 1996-01-31 松下電子工業株式会社 Pinhole inspection method

Also Published As

Publication number Publication date
JPS54118890A (en) 1979-09-14

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