JPS5853533B2 - stereo demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvement of a stereo demodulation circuit, and particularly aims to improve the SN ratio (signal-to-noise ratio) when receiving weak electric field signals.

It is known that in an FM broadcast receiver, the SN ratio is worse when receiving a weak electric field signal than when receiving a residual electric field signal, and in particular, it is worse in a stereo reception state than in a monaural reception state.

Particularly in vehicle-mounted FM receivers, the electric field strength changes rapidly, and the SN ratio worsens when the electric field is weak, resulting in uncomfortable listening conditions.

Conventionally, in order to prevent the SN ratio from deteriorating, when a stereo signal is received in a weak electric field, the receiver is forcibly put into a monaural state in order to improve the SN ratio.

As shown in Fig. 1, when the input signal becomes small and the output signal (solid line A in Fig. 1) also becomes small, the SN ratio in the stereo reception state (dotted chain line in Fig. 1) is higher than the mono signal. This method focuses on the fact that the SN ratio in the reception state (dotted line C in Figure 1) is better. For example, by switching the receiver to the monaural state at point B in Figure 1, a large SN ratio can be achieved.
An improvement in the ratio is made.

However, in the conventional method, since the stereo reception state is forcibly and abruptly switched to the monaural state, it gives a strange feeling to the listener and, for example, when the input signal is smaller than point A in Figure 1, the mono Even in the receiving state, the signal-to-noise ratio deteriorated so much that it was difficult to listen to.

Furthermore, a method of substantially improving the signal-to-noise ratio by cutting unpleasant high-frequency noise is also conventionally known.

For example, as shown in FIG. 2, capacitors 4 and 5 for cutting high-frequency components are connected to the left and right output terminals 2 and 3 of the stereo demodulation circuit 1 via switches 6 and 7, respectively.
When the electric field strength of the input signal falls below a predetermined level, the switch is turned on to improve the S/N ratio.

However, such a method has the disadvantage that the S/N ratio changes rapidly before and after the switch is turned on, and the frequency characteristics also change rapidly.Moreover, in the case of a car-mounted receiver, it is difficult to respond to changes in electric field strength. As a result, switching is performed frequently, which has the disadvantage of being extremely jarring to listeners.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a circuit that can be easily integrated into an integrated circuit (IC) in order to improve the SN ratio particularly in the case of a weak electric field.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, in which 8 is a demodulation circuit for demodulating the sub-channel signal ((LR) sin ωt).

The demodulation circuit 8 includes a first differential circuit 13 consisting of first and second transistors 11 and 12 controlled by positive and negative 38 KHz switching signals applied to first and second control terminals 9 and 10; 3 and 4th transistor 1
4 and 15, a fifth transistor 17 whose collector is connected to the first differential circuit 13 and whose base is connected to the bias power supply; consists of a sixth transistor 19 connected to the stereo composite signal input terminal 18 and a constant current transistor 20, and the sixth transistor 19
The third transistor 14 is switched by switching the sub-channel signal in the stereo composite signal applied to the base of the
The first stereo difference signal (L-R) is sent to the collector of
A second stereo difference signal (L) is obtained at the collector of the transistor 15.

Further, 21 and 22 are first and second sum signal circuits for adding the main channel signal (stereo sum signal (L+R)) to the first and second stereo difference signals, respectively, and the first sum signal circuit υ is , a third differential circuit generator consisting of seventh and eighth transistors 23 and 24 controlled by third and fourth control signals t1 and t2, and a ninth and tenth transistor 26.
and 27, and a transistor 2 whose collector is connected to the third differential circuit υ and whose base is connected to the stereo composite signal input terminal 18.
9, and a twelfth transistor 33 whose collector is connected to the fourth differential circuit 28 and whose base is connected to the stereo composite signal input terminal 18 via a high-frequency cut circuit U consisting of a resistor 30 and a capacitor 31, It is arranged to add the main channel signal to the first stereo difference signal (LR) obtained at the collector of the third transistor 14 of the second differential circuit U.

The second sum signal circuit t2 receives a second stereo difference signal (
RL), and its configuration and operation are the same as those of the first summation signal circuit υ, so further explanation will be omitted.

Note that the circuit elements of the second sum signal circuit U are indicated by adding a dash to the figure number of the corresponding circuit element of the first sum signal circuit U.

Next, the operation will be explained.

When the electric field strength of the received signal is sufficiently large, that is, within a range where the input signal is smaller than point B in FIG.
The first stereo difference signal (LR) obtained at the collector of the third transistor 14 of the second differential circuit U and the stereo difference signal (L+R) from the first sum signal circuit are added, and the first
A left (2L) stereo signal is supplied to the output terminal 34, a second stereo difference signal (R-L) obtained at the collector of the fourth transistor 15 of the second differential circuit tJ, and a stereo signal from the second sum signal circuit U. The sum signal (L+R) is added, and a right (2R) stereo signal is obtained at the second output terminal 35.

The third and fourth control signals t and t2 applied to the third and fourth control terminals 36 and 37 are an antenna 38, an RF amplification circuit 11, a mixing circuit 01, a local oscillation circuit 0, an IF amplification circuit as shown in FIG. Circuit u1 IP amplifier circuit generator 1 of FM stereo receiver consisting of FM detection circuit 0 and stereo demodulation circuit U
taken from.

The signal passing through the IF amplification circuit has an amplitude proportional to the electric field strength.

Therefore, if the signal is extracted by the detection circuit and the control signal generation circuit generator 1 generates third and fourth control signals t and t2 having a predetermined relationship, the third and fourth control signals t and t2 is a signal related to electric field strength.

Incidentally, the relationship between the third control signal t1 and the fourth control signal t2 is set so that t2=(A-tl).

(However, A is a constant). In the first operating state, the electric field strength is sufficiently large, so that the relationship tl>''2 holds. Therefore, regarding the first sum signal circuit υ, the seventh transistor 23 of the third differential circuit υ and the fourth The first part of “Differential circuit”
Since the zero transistor 27 is conductive and the eighth and ninth transistors 24 and 26 are non-conductive, the signal is applied from the stereo composite signal input terminal 18 to the third differential circuit L5 via the base-collector path of the eleventh transistor 29. The resulting stereo sum signal (L+R) is transmitted to the seventh transistor 23
is supplied to the collector of the third transistor 14 of the second differential circuit U from which the first stereo difference signal (L-R) is obtained, and the left stereo signal (2L) is supplied to the first output terminal 34.
is obtained.

The same applies to the second sum signal circuit t1, and the third sum signal circuit t1 in the above state
By applying the fourth control signals t1 and t2, a stereo sum signal (L+R) is obtained at the output terminal, which is a second stereo difference signal obtained at the collector of the fourth transistor 15 of the second differential circuit U. (R−L), and a right stereo signal (2R) is obtained at the second output terminal 35.

When the electric field strength decreases and the input signal becomes smaller than point B in FIG. 1, the output signal of the difference signal demodulation circuit 8 becomes smaller.

That is, the signals obtained at the first and second output terminals 47 and 48 of the 38 KHz switching signal level control circuit shown in FIG. 5 are applied to the first and second control terminals 9 and 10 in FIG. 3.

The level control circuit includes differentially connected transistors 49 and 50, a constant current transistor 51, and a control terminal 52 to which a signal for controlling the collector current of the constant current transistor 51 is applied. Control terminal 52
38 applied to the bases of differentially connected transistors 49 and 50, respectively, in response to a control signal applied to
This is for attenuating KHz switching signals.

The control signal corresponds to the electric field strength of the received signal, and is taken out from the IP amplifier circuit U in FIG. 4 to the output terminal 54 via the detection circuit generator 5 and the processing circuit Σ3.

Therefore, when the input signal becomes smaller than the point B in FIG. The phase 38KHz switching signal also becomes small, and the demodulated first and second stereo difference signals (L-R) and (R-L)
The value of is also small.

Therefore, when added to the stereo sum signal (L+R) from the first and second sum signal circuits and tl, the first output terminal 34
The right stereo signal remains at the second output terminal 35, and the left stereo signal remains at the second output terminal 35 as a crosstalk component, deteriorating the degree of separation.

As the input signal further decreases, the crosstalk component increases further, and eventually the generation of the stereo difference signal stops, and the stereo sum signal (L+R) is output to the first and second output terminals 34 and 35. They occur equally, resulting in a monaural listening condition.

The output signals generated at the first and second output terminals 34 and 35 continuously transition from a stereo state to a monaural state, and accordingly, the SN ratio also continuously transitions from a stereo state to a monaural state, and the SN ratio changes continuously from a stereo state to a monaural state. Since the improvement can be made smoothly rather than suddenly, it is possible to prevent the listener from feeling uncomfortable or uncomfortable.

During this time, the state of the sum signal circuit does not change at all.

In the range (A-B) in FIG. 1, an improvement in the SN ratio is achieved by transitioning from a stereo state to a monaural state and maintaining the monaural state, as described above.

When the electric field strength of the received signal becomes even smaller and the deterioration of the S/N ratio becomes noticeable even in the monaural state, the first and second
The states of the sum signal circuits υ and tl begin to change.

That is, when the input signal reaches point A in FIG. 24
, and the ninth transistor 26 of the fourth differential circuit i'' start conducting.

Then, with the start of conduction of the ninth transistor 26,
The high-frequency cut main channel signal applied from the stereo composite signal input terminal 18 to the base of the twelfth transistor 33 via the high-frequency cut circuit U begins to be led out to the collector of the ninth transistor 26, and the first sum signal circuit υ
The high-frequency cut main channel signal is obtained in the output signal of the third differential circuit 25 along with the main channel signal led out to the colefter of the seventh transistor 23 of the third differential circuit 25.

In response to a decrease in the level of the input signal, the third control signal t1
decreases more and more, and the fourth control signal t2 increases the profit, so
The proportion of the high-frequency cut main channel signal included in the output signal of the first sum signal circuit υ increases more and more.

For example, when t1=t2, the ratio of the high frequency cut main channel signal to the main channel signal is l:1.

When the input signal becomes extremely small, 1. (<12, and the third
The seventh transistor 23 of the differential circuit becomes non-conductive, and the ninth transistor 26 of the fourth differential circuit becomes saturated.

Therefore, the output signal of the first sum signal circuit υ is only the high-frequency cut main channel signal, and a sufficient improvement in the SN ratio is achieved.

FIG. 6 is a characteristic diagram showing the relationship between the ratio of the third control signal t1 to the main channel signal and the high frequency cut main channel signal, where the dashed line C represents the main channel signal and the solid line 2 represents the high frequency cut main channel signal. shows.

The second sum signal circuit z1 operates in exactly the same way as the first sum signal circuit 1 and provides the same output signal, so a description thereof will be omitted.

As described above, the stereo demodulation circuit according to the present invention exhibits a very large effect in improving the S/N ratio in a weak electric field.

In particular, in the present invention, as is clear from the embodiment shown in FIG. 3, the first and second summation signal circuits are configured as a balanced type using differential circuits, and therefore can be easily integrated into an IC. It has the advantage that variations in IC production can be absorbed.

[Brief explanation of drawings]

Fig. 1 is a characteristic diagram for explaining the present invention, Fig. 2 is a circuit diagram showing a conventional example, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is for explaining the present invention. Block diagram provided, No. 5
This figure is a circuit diagram showing a circuit for generating signals applied to the first and second control terminals in FIG. 3, and FIG. 6 is a characteristic diagram for explaining the present invention. Explanation of the main drawing numbers: Difference signal demodulation circuit lJ. IJ, 2. t, 28, 25', 2J'・
・−・−Slow circuit, υ. Ll...sum signal circuit.

Claims (1)

[Claims] 1. A difference signal demodulation circuit that generates the first and second stereo difference signals by demodulating the sub-channel signal, and (1) controlled by a control signal corresponding to the amplitude of the IF signal passing through the F amplifier circuit. a circuit for supplying a main channel signal to the first differential circuit; and a circuit for supplying a main channel signal to the first differential circuit;
a first sum signal circuit comprising a circuit that supplies a main channel signal with a high frequency cut to the differential circuit; a second sum signal circuit having the same configuration as the first sum signal circuit; and a second sum signal circuit of the difference signal demodulation circuit. a circuit that generates a left stereo signal by adding one stereo difference signal and an output signal of the first sum signal circuit; and a second stereo difference signal of the difference signal demodulation circuit and an output signal of the second sum signal circuit. and a circuit that generates a right stereo signal by adding the above, and depending on the state of the control signal, either one of the main channel signal and the main channel signal with the high frequency cut, or a signal that is a mixture of both. is obtained at the output terminals of the first and second summation signal circuits, and when the amplitude of the IF signal is large, the proportion of the main channel signal in the output signals of the first and second summation signal circuits is is a dog, and when the amplitude of the IF signal is small, the first and second
A stereo demodulation circuit characterized in that a main channel signal from which high frequencies are cut accounts for a large proportion of the output signal of a sum signal circuit. 2. The sieve IJ control signals are a pair of signals t1 and t2 that are applied to the bases of the first and second differential circuits, respectively, and have a relationship of t2=A-tl with respect to a constant A. Claim 1
Stereo demodulation circuit described in section.