JPS5853084A - Storage circuit - Google Patents

Abstract

PURPOSE:To speed up access time with short wire, by constituting the circuit is located separately into a write circuit and a readout circuit via write signal lines and readout signal lines at both sides of a memory section at the center. CONSTITUTION:One side of a memory section 5 having a plurality of memory cells 1 in matrix shape is provided with a sense circuit 2 for data readout and another side is provided with a write circuit 3, they are respectively connected to bus lines BL and BL' and to input I/O circuit via a readout signal line RSL and a write signal line RSL. Thus, wirings between each signal line and circuit can be decreased to reduce capacitance, resistance and time constant of wirings, allowing to speed up the access time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed memory circuit formed of an integrated circuit.

FIG. 1 shows an example of the configuration of a conventional memory circuit. This circuit is
This is a circuit that uses two pass lines to write or read data on one pin and one pin, and the data is 4 bits. In the figure, 1 is a memory cell that stores data, and multiple memory cells 1 are paired The pass lines BL and BL are commonly connected to each other. Also, 2 is this memory cell 1
This sense circuit 2 is a data reading sense circuit that detects data read out onto the path lines BL and BI from the path lines BL and BI.
It has a function of amplifying the potential difference between 1 and 1 and shortening the data establishment time. J is a write circuit for writing data to memory cell 1, WSL is a write signal line, R8L is a read signal line, and 4 is an input/output (Ilo) circuit that controls data transfer between memory cell I and an external circuit. It is.

Note that in the above circuit, the address line of the memory cell 1 or other control signals are omitted.

A simple circuit example of the write circuit 3 is shown in FIG. This circuit includes pass lines BL each having a pair of drains,
It has a transistor TI + TM which is connected to BL, whose source is connected to the write signal signal WSLK via an inverter Il'+Il, and whose r-to is connected to the signal line SL. This signal line SLt/Cld is supplied with a control signal that turns on the transistor T1*'' when data is written into the memory cell 1, and at this time, the pair of /4' line BL, BL is supplied with a control signal that turns on the transistor T1*'' when data is written into the memory cell 1. Mutually complementary information is transmitted.On the other hand, F Runnosta T1 *
'r, is off, the write data is on the pass line B.
It is not transmitted to L and BL.

FIG. 3 shows a specific circuit example of the memory cell 1.

In this memory cell, there is a fritnoflora 7''FF consisting of an inverter xse I4, and transistors TI and T4 that receive address data from the address line AL and transfer data between the fritfrog FF and the pass lines BL, BL. When memory cell 1 receives address designation, address line AL becomes 1#,
In the case of data writing, the r-waves transmitted to the pass lines BL and BL are stored in the fritsnoflora 7'FF via the transistor Tl*T4.

On the other hand, in the case of data reading, the free lag frog F
The data stored in FK is transmitted to the pass lines BL, BL via transistors Tm+T4. The data detected by the sense circuit 2 is sent to the read signal line R8.
The data is input to the I10 circuit 4 via L, and the data is transmitted from this to an external circuit. Furthermore, data from the external circuit is transmitted to the write signal line WSL via the I10 circuit 4 and inputted to the write circuit 3.

The circuit example shown in Figure 1 above is for a case where the data is 4 bits, so a total of 8 data signal lines are required: 4 write signal lines WSL and 4 alignment signal lines R8L. . As mentioned above, I10 circuit 4 from sense circuit 2
Data transfer (reading) from the I10 circuit 4 to the write circuit 3 (writing color writing) is performed via these eight data signal lines. Here, in order to shorten the write time and read time, it is conceivable to reduce the time constant of this data signal line.

Therefore, FIG. 4 shows an actual configuration diagram of the input and readout signal lines in the circuit of FIG. 1, and the time constants of these signal lines will be discussed. In FIG. 4, the write signal line W8L and the read signal line R8L are formed of metal wiring such as aluminum, and the write circuit 3,
Data signal line DL for sense circuit 2 and I10 circuit 4 is formed of polycrystalline silicon wiring, and contact hole CH is provided between these metal wiring and polycrystalline silicon wiring for electrical contact. During data writing, the data to be written is transmitted from the I10 circuit 4 to the data signal line DL3, the write signal line WSL1, and the data signal line DLl, and is input to the write circuit 3. On the other hand, during reading, data detected by the sense circuit 2 is sent to the data signal line DL.

It is input to the I10 circuit 4 via the read signal line R8Ll and the data signal line DL4. i.e. write,
In either case of reading, data passes through a polycrystalline silicon wiring having a length corresponding to the distance of eight metal wirings. Incidentally, the time constant of a signal line is approximately proportional to the product of the resistance value of the signal line and the capacitance associated with the signal line. Therefore, in order to reduce this time constant, it is sufficient to reduce either one or both of the above-mentioned resistance value and capacitance.

Here, as the capacitance added to the signal line, the signal line W in FIG.
SL, the capacitance between the metal wiring WSL1 and the substrate via the insulating layer and the polycrystalline silicon wiring DL1. DLs
On the other hand, the resistance of the signal line can be considered to be the wiring resistance of polycrystalline silicon, the resistance of metal wiring, and the contact resistance at CH. The specific resistance of this polycrystalline silicon can be increased to υ number 100 by doping with ions. Since the resistivity of the metal wiring can be lowered to about cIR and the specific resistance of the metal wiring is about the same as that of the π plane of polycrystalline silicon, the resistance of the metal wiring can be ignored. Therefore,
The best way to reduce the capacitance and resistance of the signal line is to make the polycrystalline silicon wiring portion as small as possible. This reduces the time constant of the signal line, making it possible to speed up memory.

The present invention has been made in view of the above circumstances, and includes a write circuit and a read circuit arranged separately on both sides of the memory section in the center, and a write signal line and a read signal line corresponding to the write circuit and read circuit. By adopting a circuit configuration in which the lines are separated from each other on both sides of the memory section, the wiring between the read signal line and write signal line and the read circuit and write circuit can be shortened and their capacitances can be reduced. and reduce resistance,
It is an object of the present invention to provide a memory circuit in which access time is increased by reducing the time constant of wiring.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In the memory circuit shown in FIG. 5, the same reference numerals are used for the same parts as in FIG. 1 described above.

It is formed. 2 is a sense circuit for a read circuit that detects data from this memory cell through the pass lines BL and BL; 3 is a write-in circuit for saving data into 4/1 (this memory section); 4 is a memory section. An input/output (Ilo) circuit transfers data between the loop 1 and an external circuit, WSL is a write signal line, and R8L is a read signal line. The feature of this circuit is that the sense circuit 2 is connected to the memory cell 1.
The write circuit 3 is placed on the other side of the memory cell 1 (on the opposite side from the sense circuit 2) and connected to the pass lines BL and BL, respectively. By doing this, the write signal line W
The SL and the read signal line R8L can be separately arranged on both sides of the memory section 5 (in which a plurality of memory cells 1 are arranged in a matrix).

Write signal line WSL and read signal line R in FIG. 5 above
8L, a circuit in which the data signal line DL is represented by metal wiring and polycrystalline silicon wiring as described above is shown in FIG. 6. Referring to FIG.
The output data detected at is input to the I10 circuit 4 via the data signal line DL1, read signal line R8LI and data signal line DL4. In this case, the total length of both data signal lines DL, DL, formed of polycrystalline silicon wiring corresponds to the width of four read signal lines R8L formed of metal wiring. , which is 1/2 the length of the conventional 8 pieces. Similarly, in the case of writing, data is supplied to the write circuit 3 via the I10 circuit 4, data signal line DL3, write signal line WSLI, and data signal line DL4.
In this case as well, the length of the polycrystalline silicon wirings DLs and DL4 corresponds to the width of four metal wirings t-L, which is also about 1/2 of the conventional length. Therefore, the resistance value due to polycrystalline silicon wiring is about 172 compared to the conventional one, so
The time constant of the signal line for writing or the signal line for reading is approximately V2 compared to the conventional one, and signal delay due to wiring is improved by fJ2 compared to the conventional one. As a result, the access time to the memory section 5 can be made into a high-speed memory circuit that is about twice as fast as that of the conventional one.

In the above embodiment, a 4-bit memory circuit is explained, but this can be 8 bits, ) = 12 bits, or any other number of pins.
It is also possible to use a separate memory circuit.

Further, although the readout circuit (sense circuit) 2 is provided above the memory section 5 (top of the drawing) and the write circuit 4 is provided below (bottom of the drawing), these may be arranged in opposite directions. They may be arranged on the left and right sides of the memory section instead of above and below. Furthermore, although polycrystalline silicon wiring is used for the data lines DL1 to DL4, this can be similarly applied to diffusion wiring.

As explained above, according to the present invention, a write circuit and a read circuit are arranged separately from each other on both sides of the memory section with the memory section at the center, and write signal lines and read circuits are arranged in correspondence with the write circuit and read circuit. The circuit configuration has signal lines separated from each other on both sides of the memory section, so
The wiring between the write signal line and the read signal line and the write circuit and the read circuit can be combed to reduce the space and resistance thereof, and the time constant of the wiring can be reduced to speed up the access time. It can provide a memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional memory circuit, FIG. 2 is a circuit block diagram showing an example of the write circuit in FIG. 1, FIG. 3 is a circuit block diagram showing an example of the memory cell in FIG. 1, and FIG. The figure is a specific configuration diagram of the wiring section shown in FIG. 1, FIG. 5 is a configuration diagram of a memory circuit according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating the wiring section of the circuit shown in FIG. FIG. 1... Memory cell, 2... Sense circuit (readout circuit), 3... Saving circuit, 4... Input/output (Ilo
) circuit, 5... memory section, BL, BL... pass line, WSL... write signal line, R8L... read signal line, DL... data signal line. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4

Claims (4)

[Claims] (1) A memory section having a plurality of memory cells in a matrix for storing data, a readout circuit arranged separately on both sides of this memory section for reading data from the memory cells, and the memory. It is equipped with a write circuit for writing data to the cell, an input/output circuit for transferring data between these write circuits, read circuits, and external circuits, and a read signal line for outputting the data and a data transfer circuit. Write signal lines for writing are arranged separately on both sides of the memory section corresponding to the read circuit and write circuit, and between these read signal lines and write signal lines and the read circuit and write circuit. A memory circuit characterized in that the wiring between the read signal line and the write signal line and the input/output circuit is shortened to reduce the time constant of the wiring, thereby speeding up data reading and writing. (2) The memory circuit according to claim 1, wherein the wiring is formed of polycrystalline silicon wiring. (3) The memory circuit according to claim 1, wherein the wiring is formed by a diffusion wiring. (4) Claim 1, wherein the input signal line and the read signal line are formed of metal wiring.
Memory circuit described in section.